#endif /* CONFIG_OMAP_DSP */
/*-------------------------------------------------------------------------*/
+#if !defined(CONFIG_ARCH_OMAP243X)
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
#define OMAP1_I2C_BASE 0xfffb3800
#define OMAP1_I2C_INT INT_I2C
#define OMAP2_I2C_INT1 56
+static u32 omap2_i2c1_clkrate = 100;
+
static struct resource i2c_resources1[] = {
{
.start = 0,
.id = 1,
.num_resources = ARRAY_SIZE(i2c_resources1),
.resource = i2c_resources1,
+ .dev = {
+ .platform_data = &omap2_i2c1_clkrate,
+ },
};
/* See also arch/arm/mach-omap2/devices.c for second I2C on 24xx */
static void omap_init_i2c(void)
{
- if (cpu_is_omap24xx()) {
+ if (cpu_is_omap242x()) {
i2c_resources1[0].start = OMAP2_I2C_BASE1;
i2c_resources1[0].end = OMAP2_I2C_BASE1 + OMAP_I2C_SIZE;
i2c_resources1[1].start = OMAP2_I2C_INT1;
* either don't wire up I2C, or chips that mux it differently...
* it can include clocking and address info, maybe more.
*/
- if (cpu_is_omap24xx()) {
+ if (cpu_class_is_omap2()) {
if (machine_is_omap_h4()) {
omap_cfg_reg(M19_24XX_I2C1_SCL);
omap_cfg_reg(L15_24XX_I2C1_SDA);
#else
static inline void omap_init_i2c(void) {}
#endif
-
+#endif
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
static void omap_init_kp(void)
{
/* REVISIT: 2430 keypad is on TWL4030 */
- if (cpu_is_omap2430())
+ if (cpu_is_omap2430() || cpu_is_omap34xx())
return;
if (machine_is_omap_h2() || machine_is_omap_h3()) {
static u64 mmc2_dmamask = 0xffffffff;
+
static struct resource mmc2_resources[] = {
{
.start = OMAP_MMC2_BASE,
const struct omap_mmc_conf *mmc;
/* REVISIT: 2430 has HS MMC */
- if (cpu_is_omap2430())
+ if (cpu_is_omap2430() || cpu_is_omap34xx())
return;
/* NOTE: assumes MMC was never (wrongly) enabled */
omap_cfg_reg(MMC_DAT3);
}
}
+ if (mmc->internal_clock) {
+ /*
+ * Use internal loop-back in MMC/SDIO
+ * Module Input Clock selection
+ */
+ if (cpu_is_omap24xx()) {
+ u32 v = omap_readl(OMAP2_CONTROL_DEVCONF);
+ v |= (1 << 24);
+ omap_writel(v, OMAP2_CONTROL_DEVCONF);
+ }
+ }
mmc1_conf = *mmc;
(void) platform_device_register(&mmc_omap_device1);
}
#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
#ifdef CONFIG_ARCH_OMAP24XX
+
+#ifdef CONFIG_ARCH_OMAP2430
+/* WDT2 */
+#define OMAP_WDT_BASE 0x49016000
+#else
#define OMAP_WDT_BASE 0x48022000
+#endif
+
#else
#define OMAP_WDT_BASE 0xfffeb000
#endif
omap_init_uwire();
omap_init_wdt();
omap_init_rng();
- omap_init_i2c();
+ if (!cpu_is_omap2430() && !cpu_is_omap34xx()) {
+ omap_init_i2c();
+ }
return 0;
}
arch_initcall(omap_init_devices);