[ARM] Convert set_pte_ext implementions to macros

[linux-2.6-omap-h63xx.git] / arch / arm / mm / proc-v6.S

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index eb42e5b948630d106372b6296d71bdf02e7943d6..70c623534021e3477bf6d323fe7e8be641691d90 100644 (file)
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -17,10 +17,6 @@
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
-#ifdef CONFIG_SMP
-#include <asm/hardware/arm_scu.h>
-#endif
-
 #include "proc-macros.S"
 
 #define D_CACHE_LINE_SIZE      32
@@ -118,46 +114,10 @@ ENTRY(cpu_v6_switch_mm)
  *               (hardware version is stored at -1024 bytes)
  *     - pte   - PTE value to store
  *     - ext   - value for extended PTE bits
- *
- *     Permissions:
- *       YUWD  APX AP1 AP0     SVC     User
- *       0xxx   0   0   0      no acc  no acc
- *       100x   1   0   1      r/o     no acc
- *       10x0   1   0   1      r/o     no acc
- *       1011   0   0   1      r/w     no acc
- *       110x   0   1   0      r/w     r/o
- *       11x0   0   1   0      r/w     r/o
- *       1111   0   1   1      r/w     r/w
  */
 ENTRY(cpu_v6_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       bic     r3, r1, #0x000003f0
-       bic     r3, r3, #0x00000003
-       orr     r3, r3, r2
-       orr     r3, r3, #PTE_EXT_AP0 | 2
-
-       tst     r1, #L_PTE_WRITE
-       tstne   r1, #L_PTE_DIRTY
-       orreq   r3, r3, #PTE_EXT_APX
-
-       tst     r1, #L_PTE_USER
-       orrne   r3, r3, #PTE_EXT_AP1
-       tstne   r3, #PTE_EXT_APX
-       bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
-
-       tst     r1, #L_PTE_YOUNG
-       biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
-
-       tst     r1, #L_PTE_EXEC
-       orreq   r3, r3, #PTE_EXT_XN
-
-       tst     r1, #L_PTE_PRESENT
-       moveq   r3, #0
-
-       str     r3, [r0]
-       mcr     p15, 0, r0, c7, c10, 1 @ flush_pte
+       armv6_set_pte_ext
 #endif
        mov     pc, lr
 
@@ -187,19 +147,9 @@ cpu_v6_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-       /* Set up the SCU on core 0 only */
-       mrc     p15, 0, r0, c0, c0, 5           @ CPU core number
-       ands    r0, r0, #15
-       ldreq   r0, =SCU_BASE
-       ldreq   r5, [r0, #SCU_CTRL]
-       orreq   r5, r5, #1
-       streq   r5, [r0, #SCU_CTRL]
-
-#ifndef CONFIG_CPU_DCACHE_DISABLE
        mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
        orr     r0, r0, #0x20
        mcr     p15, 0, r0, c1, c0, 1
-#endif
 #endif
 
        mov     r0, #0
@@ -233,6 +183,7 @@ v6_crval:
        .type   v6_processor_functions, #object
 ENTRY(v6_processor_functions)
        .word   v6_early_abort
+       .word   pabort_noifar
        .word   cpu_v6_proc_init
        .word   cpu_v6_proc_fin
        .word   cpu_v6_reset