]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - arch/arm/mm/flush.c
Merge with ../linux-2.6
[linux-2.6-omap-h63xx.git] / arch / arm / mm / flush.c
index 828950727298bac9d0564e8bdecc2813887da011..1fc2b1da55602c4d94a3297cffad7dddfe6f241d 100644 (file)
 #include <asm/tlbflush.h>
 
 #ifdef CONFIG_CPU_CACHE_VIPT
+
+void flush_cache_mm(struct mm_struct *mm)
+{
+       if (cache_is_vivt()) {
+               if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
+                       __cpuc_flush_user_all();
+               return;
+       }
+
+       if (cache_is_vipt_aliasing()) {
+               asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
+               "       mcr     p15, 0, %0, c7, c5, 0\n"
+               "       mcr     p15, 0, %0, c7, c10, 4"
+                   :
+                   : "r" (0)
+                   : "cc");
+       }
+}
+
+void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
+{
+       if (cache_is_vivt()) {
+               if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
+                       __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
+                                               vma->vm_flags);
+               return;
+       }
+
+       if (cache_is_vipt_aliasing()) {
+               asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
+               "       mcr     p15, 0, %0, c7, c5, 0\n"
+               "       mcr     p15, 0, %0, c7, c10, 4"
+                   :
+                   : "r" (0)
+                   : "cc");
+       }
+}
+
+void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
+{
+       if (cache_is_vivt()) {
+               if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
+                       unsigned long addr = user_addr & PAGE_MASK;
+                       __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
+               }
+               return;
+       }
+
+       if (cache_is_vipt_aliasing())
+               flush_pfn_alias(pfn, user_addr);
+}
+
 #define ALIAS_FLUSH_START      0xffff4000
 
 #define TOP_PTE(x)     pte_offset_kernel(top_pmd, x)