/*
* Forces OMAP into idle state
*
- * omap242x_idle_loop_suspend() - This bit of code just executes the WFI
+ * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
* for normal idles.
*
* Note: This code get's copied to internal SRAM at boot. When the OMAP
* wakes up it continues execution at the point it went to sleep.
*/
-ENTRY(omap242x_idle_loop_suspend)
+ENTRY(omap24xx_idle_loop_suspend)
stmfd sp!, {r0, lr} @ save registers on stack
- mov r0, #0x0 @ clear for mrc call
+ mov r0, #0 @ clear for mcr setup
mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
ldmfd sp!, {r0, pc} @ restore regs and return
-ENTRY(omap242x_idle_loop_suspend_sz)
- .word . - omap242x_idle_loop_suspend
+ENTRY(omap24xx_idle_loop_suspend_sz)
+ .word . - omap24xx_idle_loop_suspend
/*
- * omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing
+ * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
* SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
* SDRC.
*
* Input:
* R0 : DLL ctrl value pre-Sleep
+ * R1 : SDRC_DLLA_CTRL
+ * R2 : SDRC_POWER
*
* The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
* when we get called, but the DLL probably isn't. We will wait a bit more in
* The DLL load value is not kept in RETENTION or OFF. It needs to be restored
* at wake
*/
-ENTRY(omap242x_cpu_suspend)
+ENTRY(omap24xx_cpu_suspend)
stmfd sp!, {r0 - r12, lr} @ save registers on stack
- mov r3, #0x0 @ clear for mrc call
+ mov r3, #0x0 @ clear for mcr call
mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
nop
nop
- ldr r3, omap2_ocs_sdrc_power @ addr of sdrc power
- ldr r4, [r3] @ value of sdrc power
+ ldr r4, [r2] @ read SDRC_POWER
orr r4, r4, #0x40 @ enable self refresh on idle req
mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
- str r4, [r3] @ make it so
+ str r4, [r2] @ make it so
mov r2, #0
nop
mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
subs r5, r5, #0x1 @ awake, wait just a bit
bne loop
- /* The DPLL has on before we take the DDR out of self refresh */
+ /* The DPLL has to be on before we take the DDR out of self refresh */
bic r4, r4, #0x40 @ now clear self refresh bit.
- str r4, [r3] @ put vlaue back.
+ str r4, [r2] @ write to SDRC_POWER
ldr r4, A_SDRC0 @ make a clock happen
- ldr r4, [r4]
+ ldr r4, [r4] @ read A_SDRC0
nop @ start auto refresh only after clk ok
movs r0, r0 @ see if DDR or SDR
- ldrne r1, omap2_ocs_sdrc_dlla_ctrl @ get addr of DLL ctrl
strne r0, [r1] @ rewrite DLLA to force DLL reload
addne r1, r1, #0x8 @ move to DLLB
strne r0, [r1] @ rewrite DLLB to force DLL reload
/* resume*/
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
-omap2_ocs_sdrc_power:
- .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
A_SDRC0:
.word A_SDRC0_V
-omap2_ocs_sdrc_dlla_ctrl:
- .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-
-ENTRY(omap242x_cpu_suspend_sz)
- .word . - omap242x_cpu_suspend
+ENTRY(omap24xx_cpu_suspend_sz)
+ .word . - omap24xx_cpu_suspend