Merge current mainline tree into linux-omap tree

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / sdrc2xxx.c

diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/sdrc2xxx.c
similarity index 71%
rename from arch/arm/mach-omap2/memory.c
rename to arch/arm/mach-omap2/sdrc2xxx.c
index 6b49cc9cbdcbcb31a03e674524cd27eb26e4139e..0723e59b587f95eddb4aebeceb7925504ae4e18e 100644 (file)
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -1,13 +1,14 @@
 /*
  * linux/arch/arm/mach-omap2/memory.c
  *
- * Memory timing related functions for OMAP24XX
+ * Memory timing related functions for OMAP2xxx
  *
- * Copyright (C) 2005 Texas Instruments Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (C) 2005, 2008 Texas Instruments Inc.
+ * Copyright (C) 2005, 2008 Nokia Corporation
  *
- * Copyright (C) 2005 Nokia Corporation
  * Tony Lindgren <tony@atomide.com>
+ * Paul Walmsley
+ * Richard Woodruff <r-woodruff2@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -21,8 +22,7 @@
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 #include <mach/common.h>
 #include <mach/clock.h>
@@ -30,26 +30,30 @@
 
 #include "prm.h"
 
-#include "memory.h"
+#include <mach/sdrc.h>
 #include "sdrc.h"
 
-void __iomem *omap2_sdrc_base;
-void __iomem *omap2_sms_base;
+/* Memory timing, DLL mode flags */
+#define M_DDR          1
+#define M_LOCK_CTRL    (1 << 2)
+#define M_UNLOCK       0
+#define M_LOCK         1
+
 
 static struct memory_timings mem_timings;
 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
 
-u32 omap2_memory_get_slow_dll_ctrl(void)
+static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
 {
        return mem_timings.slow_dll_ctrl;
 }
 
-u32 omap2_memory_get_fast_dll_ctrl(void)
+static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
 {
        return mem_timings.fast_dll_ctrl;
 }
 
-u32 omap2_memory_get_type(void)
+static u32 omap2xxx_sdrc_get_type(void)
 {
        return mem_timings.m_type;
 }
@@ -58,7 +62,7 @@ u32 omap2_memory_get_type(void)
  * Check the DLL lock state, and return tue if running in unlock mode.
  * This is needed to compensate for the shifted DLL value in unlock mode.
  */
-u32 omap2_dll_force_needed(void)
+u32 omap2xxx_sdrc_dll_is_unlocked(void)
 {
        /* dlla and dllb are a set */
        u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
@@ -73,8 +77,10 @@ u32 omap2_dll_force_needed(void)
  * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
  * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
  * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ *
+ * Used by the clock framework during CORE DPLL changes
  */
-u32 omap2_reprogram_sdrc(u32 level, u32 force)
+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
 {
        u32 dll_ctrl, m_type;
        u32 prev = curr_perf_level;
@@ -83,18 +89,18 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
        if ((curr_perf_level == level) && !force)
                return prev;
 
-       if (level == CORE_CLK_SRC_DPLL) {
-               dll_ctrl = omap2_memory_get_slow_dll_ctrl();
-       } else if (level == CORE_CLK_SRC_DPLL_X2) {
-               dll_ctrl = omap2_memory_get_fast_dll_ctrl();
-       } else {
+       if (level == CORE_CLK_SRC_DPLL)
+               dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
+       else if (level == CORE_CLK_SRC_DPLL_X2)
+               dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
+       else
                return prev;
-       }
 
-       m_type = omap2_memory_get_type();
+       m_type = omap2xxx_sdrc_get_type();
 
        local_irq_save(flags);
-       __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
+       prm_write_mod_reg(0xffff, OMAP24XX_GR_MOD,
+                         OMAP24XX_PRCM_VOLTSETUP_OFFSET);
        omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
        curr_perf_level = level;
        local_irq_restore(flags);
@@ -102,12 +108,14 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
        return prev;
 }
 
-void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
+/* Used by the clock framework during CORE DPLL changes */
+void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
 {
        unsigned long dll_cnt;
        u32 fast_dll = 0;
 
-       mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
+       /* DDR = 1, SDR = 0 */
+       mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
 
        /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
         * In the case of 2422, its ok to use CS1 instead of CS0.
@@ -154,25 +162,3 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
        /* 90 degree phase for anything below 133Mhz + disable DLL filter */
        mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 }
-
-void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
-{
-       omap2_sdrc_base = omap2_globals->sdrc;
-       omap2_sms_base = omap2_globals->sms;
-}
-
-/* turn on smart idle modes for SDRAM scheduler and controller */
-void __init omap2_init_memory(void)
-{
-       u32 l;
-
-       l = sms_read_reg(SMS_SYSCONFIG);
-       l &= ~(0x3 << 3);
-       l |= (0x2 << 3);
-       sms_write_reg(l, SMS_SYSCONFIG);
-
-       l = sdrc_read_reg(SDRC_SYSCONFIG);
-       l &= ~(0x3 << 3);
-       l |= (0x2 << 3);
-       sdrc_write_reg(l, SDRC_SYSCONFIG);
-}