]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - arch/arm/mach-omap2/powerdomains34xx.h
[ARM] OMAP3: update ES level flags to discriminate between post-ES2 revisions
[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / powerdomains34xx.h
index f573f71083983c28f22b88737c3b3ab6770a9760..78acfce8bbdcaeaf0cad400376fac7a1b324cc09 100644 (file)
@@ -236,14 +236,19 @@ static struct powerdomain dss_pwrdm = {
        },
 };
 
+/*
+ * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
+ * possible SGX powerstate, the SGX device itself does not support
+ * retention.
+ */
 static struct powerdomain sgx_pwrdm = {
        .name             = "sgx_pwrdm",
        .prcm_offs        = OMAP3430ES2_SGX_MOD,
-       .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+       .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
        .wkdep_srcs       = gfx_sgx_wkdeps,
        .sleepdep_srcs    = cam_gfx_sleepdeps,
        /* XXX This is accurate for 3430 SGX, but what about GFX? */
-       .pwrsts           = PWRSTS_OFF_RET_ON,
+       .pwrsts           = PWRSTS_OFF_ON,
        .pwrsts_logic_ret = PWRDM_POWER_RET,
        .banks            = 1,
        .pwrsts_mem_ret   = {
@@ -307,11 +312,12 @@ static struct powerdomain neon_pwrdm = {
 static struct powerdomain usbhost_pwrdm = {
        .name             = "usbhost_pwrdm",
        .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
-       .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+       .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
        .wkdep_srcs       = per_usbhost_wkdeps,
        .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRDM_POWER_RET,
+       .flags            = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */
        .banks            = 1,
        .pwrsts_mem_ret   = {
                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
@@ -321,6 +327,37 @@ static struct powerdomain usbhost_pwrdm = {
        },
 };
 
+static struct powerdomain dpll1_pwrdm = {
+       .name           = "dpll1_pwrdm",
+       .prcm_offs      = MPU_MOD,
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll2_pwrdm = {
+       .name           = "dpll2_pwrdm",
+       .prcm_offs      = OMAP3430_IVA2_MOD,
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll3_pwrdm = {
+       .name           = "dpll3_pwrdm",
+       .prcm_offs      = PLL_MOD,
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll4_pwrdm = {
+       .name           = "dpll4_pwrdm",
+       .prcm_offs      = PLL_MOD,
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll5_pwrdm = {
+       .name           = "dpll5_pwrdm",
+       .prcm_offs      = PLL_MOD,
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
+};
+
+
 #endif    /* CONFIG_ARCH_OMAP34XX */