Merge current mainline tree into linux-omap tree

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / id.c

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a5d4526ac4d6debdb1f0a0e0393bc37443e00bac..a526c0fc628d94553dfef5d23ce0773be9127aa2 100644 (file)
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -14,27 +14,17 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
-
+#include <mach/common.h>
 #include <mach/control.h>
 #include <mach/cpu.h>
 
-#if defined(CONFIG_ARCH_OMAP2420)
-#define TAP_BASE       io_p2v(0x48014000)
-#elif defined(CONFIG_ARCH_OMAP2430)
-#define TAP_BASE       io_p2v(0x4900A000)
-#elif defined(CONFIG_ARCH_OMAP34XX)
-#define TAP_BASE       io_p2v(0x4830A000)
-#endif
+static u32 class;
+static void __iomem *tap_base;
+static u16 tap_prod_id;
 
 #define OMAP_TAP_IDCODE                0x0204
-#if defined(CONFIG_ARCH_OMAP34XX)
-#define OMAP_TAP_PROD_ID       0x0210
-#else
-#define OMAP_TAP_PROD_ID       0x0208
-#endif
-
 #define OMAP_TAP_DIE_ID_0      0x0218
 #define OMAP_TAP_DIE_ID_1      0x021C
 #define OMAP_TAP_DIE_ID_2      0x0220
@@ -93,18 +83,24 @@ static u32 __init read_tap_reg(int reg)
         * it means its Cortex r0p0 which is 3430 ES1
         */
        if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
+
+               if (reg == tap_prod_id) {
+                       regval = 0x000F00F0;
+                       goto out;
+               }
+
                switch (reg) {
                case OMAP_TAP_IDCODE  : regval = 0x0B7AE02F; break;
                /* Making DevType as 0xF in ES1 to differ from ES2 */
-               case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
                case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
                case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
                case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
                case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
                }
        } else
-               regval = __raw_readl(TAP_BASE + reg);
+               regval = __raw_readl(tap_base + reg);
 
+out:
        return regval;
 
 }
@@ -203,7 +199,7 @@ void __init omap2_check_revision(void)
        u8  rev;
 
        idcode = read_tap_reg(OMAP_TAP_IDCODE);
-       prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
+       prod_id = read_tap_reg(tap_prod_id);
        hawkeye = (idcode >> 12) & 0xffff;
        rev = (idcode >> 28) & 0x0f;
        dev_type = (prod_id >> 16) & 0x0f;
@@ -268,3 +264,39 @@ void __init omap2_check_revision(void)
 
 }
 
+#ifdef CONFIG_ARCH_OMAP3
+/*
+ * OMAP3 has L2 cache which has to be enabled by bootloader.
+ */
+static int __init omap3_check_l2cache(void)
+{
+       u32 val;
+
+       if (class < OMAP3430_REV_ES1_0)
+               return -ENODEV;
+
+       /* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
+       asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
+
+       if ((val & 0x2) == 0)
+               printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
+                      "your bootloader. L2 off results in performance loss\n");
+       else
+               pr_info("OMAP3 L2 cache enabled\n");
+
+       return 0;
+}
+
+arch_initcall(omap3_check_l2cache);
+#endif /* CONFIG_ARCH_OMAP3 */
+
+void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
+{
+       class = omap2_globals->class;
+       tap_base = omap2_globals->tap;
+
+       if (class == 0x3430)
+               tap_prod_id = 0x0210;
+       else
+               tap_prod_id = 0x0208;
+}