Adding csi2_fck declaration to clock34xx.h

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / cm-regbits-34xx.h

diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index ee4c0ca1a7087af06ad8bb45498accbeb67f2cea..1b5d1230b80009b4a22814fe7a8a8fbd5704785e 100644 (file)
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -96,7 +96,8 @@
 #define OMAP3430_CLKTRCTRL_IVA2_MASK                   (0x3 << 0)
 
 /* CM_CLKSTST_IVA2 */
-#define OMAP3430_CLKACTIVITY_IVA2                      (1 << 0)
+#define OMAP3430_CLKACTIVITY_IVA2_SHIFT                        0
+#define OMAP3430_CLKACTIVITY_IVA2_MASK                 (1 << 0)
 
 /* CM_REVISION specific bits */
 
@@ -140,7 +141,8 @@
 #define OMAP3430_CLKTRCTRL_MPU_MASK                    (0x3 << 0)
 
 /* CM_CLKSTST_MPU */
-#define OMAP3430_CLKACTIVITY_MPU                       (1 << 0)
+#define OMAP3430_CLKACTIVITY_MPU_SHIFT                 0
+#define OMAP3430_CLKACTIVITY_MPU_MASK                  (1 << 0)
 
 /* CM_FCLKEN1_CORE specific bits */
 
@@ -188,11 +190,12 @@
 #define OMAP3430_ST_MSPRO                              (1 << 23)
 #define OMAP3430_ST_HDQ                                        (1 << 22)
 #define OMAP3430ES1_ST_FAC                             (1 << 8)
+#define OMAP3430ES2_ST_SSI_IDLE                                (1 << 8)
 #define OMAP3430ES1_ST_MAILBOXES                       (1 << 7)
 #define OMAP3430_ST_OMAPCTRL                           (1 << 6)
 #define OMAP3430_ST_SDMA                               (1 << 2)
 #define OMAP3430_ST_SDRC                               (1 << 1)
-#define OMAP3430_ST_SSI                                        (1 << 0)
+#define OMAP3430_ST_SSI_STDBY                          (1 << 0)
 
 /* CM_IDLEST2_CORE */
 #define OMAP3430_ST_PKA                                        (1 << 4)
@@ -206,6 +209,10 @@
 #define OMAP3430ES2_ST_USBTLL_MASK                     (1 << 2)
 
 /* CM_AUTOIDLE1_CORE */
+#define OMAP3430ES2_AUTO_MMC3                          (1 << 30)
+#define OMAP3430ES2_AUTO_MMC3_SHIFT                    30
+#define OMAP3430ES2_AUTO_ICR                           (1 << 29)
+#define OMAP3430ES2_AUTO_ICR_SHIFT                     29
 #define OMAP3430_AUTO_AES2                             (1 << 28)
 #define OMAP3430_AUTO_AES2_SHIFT                       28
 #define OMAP3430_AUTO_SHA12                            (1 << 27)
@@ -274,6 +281,9 @@
 #define OMAP3430_AUTO_DES1_SHIFT                       0
 
 /* CM_AUTOIDLE3_CORE */
+#define        OMAP3430ES2_AUTO_USBHOST                        (1 << 0)
+#define        OMAP3430ES2_AUTO_USBHOST_SHIFT                  0
+#define        OMAP3430ES2_AUTO_USBTLL                         (1 << 2)
 #define OMAP3430ES2_AUTO_USBTLL_SHIFT                  2
 #define OMAP3430ES2_AUTO_USBTLL_MASK                   (1 << 2)
 
@@ -300,9 +310,12 @@
 #define OMAP3430_CLKTRCTRL_L3_MASK                     (0x3 << 0)
 
 /* CM_CLKSTST_CORE */
-#define OMAP3430ES1_CLKACTIVITY_D2D                    (1 << 2)
-#define OMAP3430_CLKACTIVITY_L4                                (1 << 1)
-#define OMAP3430_CLKACTIVITY_L3                                (1 << 0)
+#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT              2
+#define OMAP3430ES1_CLKACTIVITY_D2D_MASK               (1 << 2)
+#define OMAP3430_CLKACTIVITY_L4_SHIFT                  1
+#define OMAP3430_CLKACTIVITY_L4_MASK                   (1 << 1)
+#define OMAP3430_CLKACTIVITY_L3_SHIFT                  0
+#define OMAP3430_CLKACTIVITY_L3_MASK                   (1 << 0)
 
 /* CM_FCLKEN_GFX */
 #define OMAP3430ES1_EN_3D                              (1 << 2)
@@ -323,7 +336,8 @@
 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK                 (0x3 << 0)
 
 /* CM_CLKSTST_GFX */
-#define OMAP3430ES1_CLKACTIVITY_GFX                    (1 << 0)
+#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT              0
+#define OMAP3430ES1_CLKACTIVITY_GFX_MASK               (1 << 0)
 
 /* CM_FCLKEN_SGX */
 #define OMAP3430ES2_EN_SGX_SHIFT                       1
@@ -333,6 +347,14 @@
 #define OMAP3430ES2_CLKSEL_SGX_SHIFT                   0
 #define OMAP3430ES2_CLKSEL_SGX_MASK                    (0x7 << 0)
 
+/* CM_CLKSTCTRL_SGX */
+#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT                        0
+#define OMAP3430ES2_CLKTRCTRL_SGX_MASK                 (0x3 << 0)
+
+/* CM_CLKSTST_SGX */
+#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT              0
+#define OMAP3430ES2_CLKACTIVITY_SGX_MASK               (1 << 0)
+
 /* CM_FCLKEN_WKUP specific bits */
 #define OMAP3430ES2_EN_USIMOCP_SHIFT                   9
 
@@ -435,8 +457,12 @@
 #define OMAP3430_CORE_DPLL_MULT_MASK                   (0x7ff << 16)
 #define OMAP3430_CORE_DPLL_DIV_SHIFT                   8
 #define OMAP3430_CORE_DPLL_DIV_MASK                    (0x7f << 8)
-#define OMAP3430_SOURCE_54M                            (1 << 5)
-#define OMAP3430_SOURCE_48M                            (1 << 3)
+#define OMAP3430_SOURCE_96M_SHIFT                      6
+#define OMAP3430_SOURCE_96M_MASK                       (1 << 6)
+#define OMAP3430_SOURCE_54M_SHIFT                      5
+#define OMAP3430_SOURCE_54M_MASK                       (1 << 5)
+#define OMAP3430_SOURCE_48M_SHIFT                      3
+#define OMAP3430_SOURCE_48M_MASK                       (1 << 3)
 
 /* CM_CLKSEL2_PLL */
 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT                        8
@@ -479,7 +505,9 @@
 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT            0
 
 /* CM_IDLEST_DSS */
-#define OMAP3430_ST_DSS                                        (1 << 0)
+#define OMAP3430ES2_ST_DSS_IDLE                                (1 << 1)
+#define OMAP3430ES2_ST_DSS_STDBY                       (1 << 0)
+#define OMAP3430ES1_ST_DSS                             (1 << 0)
 
 /* CM_AUTOIDLE_DSS */
 #define OMAP3430_AUTO_DSS                              (1 << 0)
@@ -498,9 +526,12 @@
 #define OMAP3430_CLKTRCTRL_DSS_MASK                    (0x3 << 0)
 
 /* CM_CLKSTST_DSS */
-#define OMAP3430_CLKACTIVITY_DSS                       (1 << 0)
+#define OMAP3430_CLKACTIVITY_DSS_SHIFT                 0
+#define OMAP3430_CLKACTIVITY_DSS_MASK                  (1 << 0)
 
 /* CM_FCLKEN_CAM specific bits */
+#define OMAP3430_EN_CSI2                               (1 << 1)
+#define OMAP3430_EN_CSI2_SHIFT                         1
 
 /* CM_ICLKEN_CAM specific bits */
 
@@ -522,7 +553,8 @@
 #define OMAP3430_CLKTRCTRL_CAM_MASK                    (0x3 << 0)
 
 /* CM_CLKSTST_CAM */
-#define OMAP3430_CLKACTIVITY_CAM                       (1 << 0)
+#define OMAP3430_CLKACTIVITY_CAM_SHIFT                 0
+#define OMAP3430_CLKACTIVITY_CAM_MASK                  (1 << 0)
 
 /* CM_FCLKEN_PER specific bits */
 
@@ -598,7 +630,8 @@
 #define OMAP3430_CLKTRCTRL_PER_MASK                    (0x3 << 0)
 
 /* CM_CLKSTST_PER */
-#define OMAP3430_CLKACTIVITY_PER                       (1 << 0)
+#define OMAP3430_CLKACTIVITY_PER_SHIFT                 0
+#define OMAP3430_CLKACTIVITY_PER_MASK                  (1 << 0)
 
 /* CM_CLKSEL1_EMU */
 #define OMAP3430_DIV_DPLL4_SHIFT                       24
@@ -623,7 +656,8 @@
 #define OMAP3430_CLKTRCTRL_EMU_MASK                    (0x3 << 0)
 
 /* CM_CLKSTST_EMU */
-#define OMAP3430_CLKACTIVITY_EMU                       (1 << 0)
+#define OMAP3430_CLKACTIVITY_EMU_SHIFT                 0
+#define OMAP3430_CLKACTIVITY_EMU_MASK                  (1 << 0)
 
 /* CM_CLKSEL2_EMU specific bits */
 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT              8
@@ -658,6 +692,8 @@
 #define OMAP3430ES2_EN_USBHOST_MASK                    (1 << 0)
 
 /* CM_IDLEST_USBHOST */
+#define OMAP3430ES2_ST_USBHOST_IDLE                    (1 << 1)
+#define OMAP3430ES2_ST_USBHOST_STDBY                   (1 << 0)
 
 /* CM_AUTOIDLE_USBHOST */
 #define OMAP3430ES2_AUTO_USBHOST_SHIFT                 0
@@ -673,6 +709,8 @@
 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT            0
 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK             (3 << 0)
 
-
+/* CM_CLKSTST_USBHOST */
+#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT          0
+#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK           (1 << 0)
 
 #endif