[ARM] OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains; mark clocks

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clockdomains.h

diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index e17c3693542cec8cdeafd41a1bd79778990e3c4a..9eb73432810716fb8c93d037d0aacd177feaae72 100644 (file)
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -14,6 +14,11 @@
 
 /*
  * OMAP2/3-common clockdomains
+ *
+ * Even though the 2420 has a single PRCM module from the
+ * interconnect's perspective, internally it does appear to have
+ * separate PRM and CM clockdomains.  The usual test case is
+ * sys_clkout/sys_clkout2.
  */
 
 /* This is an implicit clockdomain - it is never defined as such in TRM */
@@ -23,6 +28,18 @@ static struct clockdomain wkup_clkdm = {
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
 
+static struct clockdomain prm_clkdm = {
+       .name           = "prm_clkdm",
+       .pwrdm          = { .name = "wkup_pwrdm" },
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain cm_clkdm = {
+       .name           = "cm_clkdm",
+       .pwrdm          = { .name = "core_pwrdm" },
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+};
+
 /*
  * 2420-only clockdomains
  */
@@ -239,6 +256,36 @@ static struct clockdomain emu_clkdm = {
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
+static struct clockdomain dpll1_clkdm = {
+       .name           = "dpll1_clkdm",
+       .pwrdm          = { .name = "dpll1_pwrdm" },
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll2_clkdm = {
+       .name           = "dpll2_clkdm",
+       .pwrdm          = { .name = "dpll2_pwrdm" },
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll3_clkdm = {
+       .name           = "dpll3_clkdm",
+       .pwrdm          = { .name = "dpll3_pwrdm" },
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll4_clkdm = {
+       .name           = "dpll4_clkdm",
+       .pwrdm          = { .name = "dpll4_pwrdm" },
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll5_clkdm = {
+       .name           = "dpll5_clkdm",
+       .pwrdm          = { .name = "dpll5_pwrdm" },
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+};
+
 #endif   /* CONFIG_ARCH_OMAP34XX */
 
 /*
@@ -266,6 +313,8 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
 static struct clockdomain *clockdomains_omap[] = {
 
        &wkup_clkdm,
+       &cm_clkdm,
+       &prm_clkdm,
 
 #ifdef CONFIG_ARCH_OMAP2420
        &mpu_2420_clkdm,
@@ -299,6 +348,11 @@ static struct clockdomain *clockdomains_omap[] = {
        &usbhost_clkdm,
        &per_clkdm,
        &emu_clkdm,
+       &dpll1_clkdm,
+       &dpll2_clkdm,
+       &dpll3_clkdm,
+       &dpll4_clkdm,
+       &dpll5_clkdm,
 #endif
 
        NULL,