[ARM] OMAP2/3: Add non-CORE DPLL rate set code and M, N programming

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.h

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 6bd8c6d5a4e7db1e5ab40f2bad39e47a6fb509bc..f811a0978512f4305564875ca6113bd6c2be306b 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -32,6 +32,8 @@ static void omap3_clkoutx2_recalc(struct clk *clk);
 static void omap3_dpll_allow_idle(struct clk *clk);
 static void omap3_dpll_deny_idle(struct clk *clk);
 static u32 omap3_dpll_autoidle_read(struct clk *clk);
+static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
 
 /* Maximum DPLL multiplier, divider values for OMAP3 */
 #define OMAP3_MAX_DPLL_MULT            2048
@@ -254,6 +256,7 @@ static struct dpll_data dpll1_dd = {
        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
+       .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -276,6 +279,7 @@ static struct clk dpll1_ck = {
        .dpll_data      = &dpll1_dd,
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
+       .set_rate       = &omap3_noncore_dpll_set_rate,
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -321,6 +325,7 @@ static struct dpll_data dpll2_dd = {
        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
+       .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
@@ -344,6 +349,7 @@ static struct clk dpll2_ck = {
        .dpll_data      = &dpll2_dd,
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
+       .set_rate       = &omap3_noncore_dpll_set_rate,
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -378,6 +384,7 @@ static struct dpll_data dpll3_dd = {
        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
+       .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
@@ -558,6 +565,7 @@ static struct dpll_data dpll4_dd = {
        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+       .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
@@ -580,6 +588,7 @@ static struct clk dpll4_ck = {
        .dpll_data      = &dpll4_dd,
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
+       .set_rate       = &omap3_dpll4_set_rate,
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -864,6 +873,7 @@ static struct dpll_data dpll5_dd = {
        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+       .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
@@ -886,6 +896,7 @@ static struct clk dpll5_ck = {
        .dpll_data      = &dpll5_dd,
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
+       .set_rate       = &omap3_noncore_dpll_set_rate,
        .recalc         = &omap3_dpll_recalc,
 };