[ARM] OMAP3 clock: avoid invalid FREQSEL values during DPLL rate rounding

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.h

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c265cdcc86aaf3945d5a5a70c17cc2d2b795a913..aadd296c05a2d230122192e399a0437491cca694 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -266,8 +266,9 @@ static struct dpll_data dpll1_dd = {
        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-       .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
+       .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -280,6 +281,7 @@ static struct clk dpll1_ck = {
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_noncore_dpll_set_rate,
+       .clkdm_name     = "dpll1_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -292,6 +294,7 @@ static struct clk dpll1_x2_ck = {
        .ops            = &clkops_null,
        .parent         = &dpll1_ck,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll1_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -314,6 +317,7 @@ static struct clk dpll1_x2m2_ck = {
        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll1_x2m2_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll1_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -336,8 +340,9 @@ static struct dpll_data dpll2_dd = {
        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
-       .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
+       .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -350,6 +355,7 @@ static struct clk dpll2_ck = {
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_noncore_dpll_set_rate,
+       .clkdm_name     = "dpll2_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -372,6 +378,7 @@ static struct clk dpll2_m2_ck = {
        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll2_m2x2_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll2_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -392,7 +399,10 @@ static struct dpll_data dpll3_dd = {
        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
+       .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+       .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -404,6 +414,7 @@ static struct clk dpll3_ck = {
        .dpll_data      = &dpll3_dd,
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -416,6 +427,7 @@ static struct clk dpll3_x2_ck = {
        .ops            = &clkops_null,
        .parent         = &dpll3_ck,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -473,6 +485,7 @@ static struct clk dpll3_m2_ck = {
        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div31_dpll3m2_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -507,6 +520,7 @@ static struct clk dpll3_m2x2_ck = {
        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .clksel         = dpll3_m2x2_ck_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -526,6 +540,7 @@ static struct clk dpll3_m3_ck = {
        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
        .clksel         = div16_dpll3_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -537,6 +552,7 @@ static struct clk dpll3_m3x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -555,6 +571,7 @@ static struct clk emu_core_alwon_ck = {
        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .clksel         = emu_core_alwon_ck_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -575,8 +592,9 @@ static struct dpll_data dpll4_dd = {
        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-       .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
+       .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -589,6 +607,7 @@ static struct clk dpll4_ck = {
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_dpll4_set_rate,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -602,6 +621,7 @@ static struct clk dpll4_x2_ck = {
        .ops            = &clkops_null,
        .parent         = &dpll4_ck,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -620,6 +640,7 @@ static struct clk dpll4_m2_ck = {
        .clksel_mask    = OMAP3430_DIV_96M_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -631,6 +652,7 @@ static struct clk dpll4_m2x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -704,6 +726,7 @@ static struct clk dpll4_m3_ck = {
        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -716,6 +739,7 @@ static struct clk dpll4_m3x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -810,7 +834,10 @@ static struct clk dpll4_m4_ck = {
        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
@@ -821,6 +848,7 @@ static struct clk dpll4_m4x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -834,6 +862,7 @@ static struct clk dpll4_m5_ck = {
        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -845,6 +874,7 @@ static struct clk dpll4_m5x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -858,6 +888,7 @@ static struct clk dpll4_m6_ck = {
        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -870,6 +901,7 @@ static struct clk dpll4_m6x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -878,6 +910,7 @@ static struct clk emu_per_alwon_ck = {
        .ops            = &clkops_null,
        .parent         = &dpll4_m6x2_ck,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &followparent_recalc,
 };
 
@@ -899,8 +932,9 @@ static struct dpll_data dpll5_dd = {
        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
-       .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
+       .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -913,6 +947,7 @@ static struct clk dpll5_ck = {
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_noncore_dpll_set_rate,
+       .clkdm_name     = "dpll5_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -930,6 +965,7 @@ static struct clk dpll5_m2_ck = {
        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
        .clksel         = div16_dpll5_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll5_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -991,6 +1027,7 @@ static struct clk clkout2_src_ck = {
        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
        .clksel         = clkout2_src_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "core_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1030,8 +1067,15 @@ static struct clk corex2_fck = {
 
 /* DPLL power domain clock controls */
 
-static const struct clksel div2_core_clksel[] = {
-       { .parent = &core_ck, .rates = div2_rates },
+static const struct clksel_rate div4_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+       { .div = 2, .val = 2, .flags = RATE_IN_343X },
+       { .div = 4, .val = 4, .flags = RATE_IN_343X },
+       { .div = 0 }
+};
+
+static const struct clksel div4_core_clksel[] = {
+       { .parent = &core_ck, .rates = div4_rates },
        { .parent = NULL }
 };
 
@@ -1046,7 +1090,7 @@ static struct clk dpll1_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
-       .clksel         = div2_core_clksel,
+       .clksel         = div4_core_clksel,
        .flags          = RATE_PROPAGATES,
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1121,7 +1165,7 @@ static struct clk dpll2_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
-       .clksel         = div2_core_clksel,
+       .clksel         = div4_core_clksel,
        .flags          = RATE_PROPAGATES,
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1157,6 +1201,11 @@ static struct clk iva2_ck = {
 
 /* Common interface clocks */
 
+static const struct clksel div2_core_clksel[] = {
+       { .parent = &core_ck, .rates = div2_rates },
+       { .parent = NULL }
+};
+
 static struct clk l3_ick = {
        .name           = "l3_ick",
        .ops            = &clkops_null,