[ARM] OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains; mark clocks

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.h

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index f811a0978512f4305564875ca6113bd6c2be306b..9dec69860ba78b23e6b96434bcd1c5c45faf22be 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -280,6 +280,7 @@ static struct clk dpll1_ck = {
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_noncore_dpll_set_rate,
+       .clkdm_name     = "dpll1_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -292,6 +293,7 @@ static struct clk dpll1_x2_ck = {
        .ops            = &clkops_null,
        .parent         = &dpll1_ck,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll1_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -314,6 +316,7 @@ static struct clk dpll1_x2m2_ck = {
        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll1_x2m2_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll1_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -350,6 +353,7 @@ static struct clk dpll2_ck = {
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_noncore_dpll_set_rate,
+       .clkdm_name     = "dpll2_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -372,6 +376,7 @@ static struct clk dpll2_m2_ck = {
        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll2_m2x2_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll2_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -404,6 +409,7 @@ static struct clk dpll3_ck = {
        .dpll_data      = &dpll3_dd,
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -416,6 +422,7 @@ static struct clk dpll3_x2_ck = {
        .ops            = &clkops_null,
        .parent         = &dpll3_ck,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -473,6 +480,7 @@ static struct clk dpll3_m2_ck = {
        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div31_dpll3m2_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -507,6 +515,7 @@ static struct clk dpll3_m2x2_ck = {
        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .clksel         = dpll3_m2x2_ck_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -526,6 +535,7 @@ static struct clk dpll3_m3_ck = {
        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
        .clksel         = div16_dpll3_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -537,6 +547,7 @@ static struct clk dpll3_m3x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -555,6 +566,7 @@ static struct clk emu_core_alwon_ck = {
        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .clksel         = emu_core_alwon_ck_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll3_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -589,6 +601,7 @@ static struct clk dpll4_ck = {
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_dpll4_set_rate,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -602,6 +615,7 @@ static struct clk dpll4_x2_ck = {
        .ops            = &clkops_null,
        .parent         = &dpll4_ck,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -620,6 +634,7 @@ static struct clk dpll4_m2_ck = {
        .clksel_mask    = OMAP3430_DIV_96M_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -631,6 +646,7 @@ static struct clk dpll4_m2x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -640,6 +656,12 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = {
        { .parent = NULL }
 };
 
+/*
+ * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
+ * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
+ * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
+ * CM_96K_(F)CLK.
+ */
 static struct clk omap_96m_alwon_fck = {
        .name           = "omap_96m_alwon_fck",
        .ops            = &clkops_null,
@@ -652,28 +674,38 @@ static struct clk omap_96m_alwon_fck = {
        .recalc         = &omap2_clksel_recalc,
 };
 
-static struct clk omap_96m_fck = {
-       .name           = "omap_96m_fck",
+static struct clk cm_96m_fck = {
+       .name           = "cm_96m_fck",
        .ops            = &clkops_null,
        .parent         = &omap_96m_alwon_fck,
        .flags          = RATE_PROPAGATES,
        .recalc         = &followparent_recalc,
 };
 
-static const struct clksel cm_96m_fck_clksel[] = {
-       { .parent = &sys_ck,        .rates = dpll_bypass_rates },
-       { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+static const struct clksel_rate omap_96m_dpll_rates[] = {
+       { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+       { .div = 0 }
+};
+
+static const struct clksel_rate omap_96m_sys_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+       { .div = 0 }
+};
+
+static const struct clksel omap_96m_fck_clksel[] = {
+       { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
+       { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
        { .parent = NULL }
 };
 
-static struct clk cm_96m_fck = {
-       .name           = "cm_96m_fck",
+static struct clk omap_96m_fck = {
+       .name           = "omap_96m_fck",
        .ops            = &clkops_null,
-       .parent         = &dpll4_m2x2_ck,
+       .parent         = &sys_ck,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-       .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-       .clksel         = cm_96m_fck_clksel,
+       .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
+       .clksel         = omap_96m_fck_clksel,
        .flags          = RATE_PROPAGATES,
        .recalc         = &omap2_clksel_recalc,
 };
@@ -688,6 +720,7 @@ static struct clk dpll4_m3_ck = {
        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -700,6 +733,7 @@ static struct clk dpll4_m3x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -742,13 +776,13 @@ static struct clk omap_54m_fck = {
        .ops            = &clkops_null,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-       .clksel_mask    = OMAP3430_SOURCE_54M,
+       .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
        .clksel         = omap_54m_clksel,
        .flags          = RATE_PROPAGATES,
        .recalc         = &omap2_clksel_recalc,
 };
 
-static const struct clksel_rate omap_48m_96md2_rates[] = {
+static const struct clksel_rate omap_48m_cm96m_rates[] = {
        { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
        { .div = 0 }
 };
@@ -759,7 +793,7 @@ static const struct clksel_rate omap_48m_alt_rates[] = {
 };
 
 static const struct clksel omap_48m_clksel[] = {
-       { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
+       { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
        { .parent = NULL }
 };
@@ -769,7 +803,7 @@ static struct clk omap_48m_fck = {
        .ops            = &clkops_null,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-       .clksel_mask    = OMAP3430_SOURCE_48M,
+       .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
        .clksel         = omap_48m_clksel,
        .flags          = RATE_PROPAGATES,
        .recalc         = &omap2_clksel_recalc,
@@ -794,7 +828,10 @@ static struct clk dpll4_m4_ck = {
        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
@@ -805,6 +842,7 @@ static struct clk dpll4_m4x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -818,6 +856,7 @@ static struct clk dpll4_m5_ck = {
        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -829,6 +868,7 @@ static struct clk dpll4_m5x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -842,6 +882,7 @@ static struct clk dpll4_m6_ck = {
        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -854,6 +895,7 @@ static struct clk dpll4_m6x2_ck = {
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
        .flags          = RATE_PROPAGATES | INVERT_ENABLE,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -862,6 +904,7 @@ static struct clk emu_per_alwon_ck = {
        .ops            = &clkops_null,
        .parent         = &dpll4_m6x2_ck,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll4_clkdm",
        .recalc         = &followparent_recalc,
 };
 
@@ -897,6 +940,7 @@ static struct clk dpll5_ck = {
        .flags          = RATE_PROPAGATES,
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_noncore_dpll_set_rate,
+       .clkdm_name     = "dpll5_clkdm",
        .recalc         = &omap3_dpll_recalc,
 };
 
@@ -914,6 +958,7 @@ static struct clk dpll5_m2_ck = {
        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
        .clksel         = div16_dpll5_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "dpll5_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -958,10 +1003,10 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
 };
 
 static const struct clksel clkout2_src_clksel[] = {
-       { .parent = &core_ck,             .rates = clkout2_src_core_rates },
-       { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
-       { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
-       { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
+       { .parent = &core_ck,           .rates = clkout2_src_core_rates },
+       { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
+       { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
+       { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
        { .parent = NULL }
 };
 
@@ -975,6 +1020,7 @@ static struct clk clkout2_src_ck = {
        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
        .clksel         = clkout2_src_clksel,
        .flags          = RATE_PROPAGATES,
+       .clkdm_name     = "core_clkdm",
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1277,7 +1323,7 @@ static struct clk sgx_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
-       .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+       .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
        .clksel         = sgx_clksel,
@@ -1291,7 +1337,7 @@ static struct clk sgx_ick = {
        .parent         = &l3_ick,
        .init           = &omap2_init_clk_clkdm,
        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
-       .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+       .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
        .clkdm_name     = "sgx_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -2182,6 +2228,17 @@ static struct clk cam_ick = {
        .recalc         = &followparent_recalc,
 };
 
+static struct clk csi2_96m_fck = {
+       .name           = "csi2_96m_fck",
+       .ops            = &clkops_omap2_dflt_wait,
+       .parent         = &core_96m_fck,
+       .init           = &omap2_init_clk_clkdm,
+       .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+       .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
+       .clkdm_name     = "cam_clkdm",
+       .recalc         = &followparent_recalc,
+};
+
 /* USBHOST - 3430ES2 only */
 
 static struct clk usbhost_120m_fck = {
@@ -2218,17 +2275,6 @@ static struct clk usbhost_ick = {
        .recalc         = &followparent_recalc,
 };
 
-static struct clk usbhost_sar_fck = {
-       .name           = "usbhost_sar_fck",
-       .ops            = &clkops_omap2_dflt,
-       .parent         = &osc_sys_ck,
-       .init           = &omap2_init_clk_clkdm,
-       .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
-       .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-       .clkdm_name     = "usbhost_clkdm",
-       .recalc         = &followparent_recalc,
-};
-
 /* WKUP */
 
 static const struct clksel_rate usim_96m_rates[] = {
@@ -2793,8 +2839,8 @@ static struct clk mcbsp4_ick = {
 };
 
 static const struct clksel mcbsp_234_clksel[] = {
-       { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
-       { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
+       { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+       { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
        { .parent = NULL }
 };