[ARM] OMAP3 clock: add omap3_core_dpll_m2_set_rate()

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.h

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 9dec69860ba78b23e6b96434bcd1c5c45faf22be..681acf0427c1fb667d22bd3c7d90b09cebdc99cb 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -34,6 +34,7 @@ static void omap3_dpll_deny_idle(struct clk *clk);
 static u32 omap3_dpll_autoidle_read(struct clk *clk);
 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
+static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
 
 /* Maximum DPLL multiplier, divider values for OMAP3 */
 #define OMAP3_MAX_DPLL_MULT            2048
@@ -266,8 +267,9 @@ static struct dpll_data dpll1_dd = {
        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-       .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
+       .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -339,8 +341,9 @@ static struct dpll_data dpll2_dd = {
        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
-       .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
+       .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -397,7 +400,10 @@ static struct dpll_data dpll3_dd = {
        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
+       .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+       .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -466,11 +472,7 @@ static const struct clksel div31_dpll3m2_clksel[] = {
        { .parent = NULL }
 };
 
-/*
- * DPLL3 output M2
- * REVISIT: This DPLL output divider must be changed in SRAM, so until
- * that code is ready, this should remain a 'read-only' clksel clock.
- */
+/* DPLL3 output M2 - primary control point for CORE speed */
 static struct clk dpll3_m2_ck = {
        .name           = "dpll3_m2_ck",
        .ops            = &clkops_null,
@@ -481,6 +483,8 @@ static struct clk dpll3_m2_ck = {
        .clksel         = div31_dpll3m2_clksel,
        .flags          = RATE_PROPAGATES,
        .clkdm_name     = "dpll3_clkdm",
+       .round_rate     = &omap2_clksel_round_rate,
+       .set_rate       = &omap3_core_dpll_m2_set_rate,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -587,8 +591,9 @@ static struct dpll_data dpll4_dd = {
        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-       .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
+       .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -926,8 +931,9 @@ static struct dpll_data dpll5_dd = {
        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
-       .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
+       .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -1060,8 +1066,15 @@ static struct clk corex2_fck = {
 
 /* DPLL power domain clock controls */
 
-static const struct clksel div2_core_clksel[] = {
-       { .parent = &core_ck, .rates = div2_rates },
+static const struct clksel_rate div4_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+       { .div = 2, .val = 2, .flags = RATE_IN_343X },
+       { .div = 4, .val = 4, .flags = RATE_IN_343X },
+       { .div = 0 }
+};
+
+static const struct clksel div4_core_clksel[] = {
+       { .parent = &core_ck, .rates = div4_rates },
        { .parent = NULL }
 };
 
@@ -1076,7 +1089,7 @@ static struct clk dpll1_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
-       .clksel         = div2_core_clksel,
+       .clksel         = div4_core_clksel,
        .flags          = RATE_PROPAGATES,
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1151,7 +1164,7 @@ static struct clk dpll2_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
-       .clksel         = div2_core_clksel,
+       .clksel         = div4_core_clksel,
        .flags          = RATE_PROPAGATES,
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1187,6 +1200,11 @@ static struct clk iva2_ck = {
 
 /* Common interface clocks */
 
+static const struct clksel div2_core_clksel[] = {
+       { .parent = &core_ck, .rates = div2_rates },
+       { .parent = NULL }
+};
+
 static struct clk l3_ick = {
        .name           = "l3_ick",
        .ops            = &clkops_null,