#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
-#include <asm/arch/control.h>
+#include <mach/control.h>
#include "clock.h"
#include "cm.h"
static int omap3_noncore_dpll_enable(struct clk *clk);
static void omap3_noncore_dpll_disable(struct clk *clk);
static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
/* Maximum DPLL multiplier, divider values for OMAP3 */
#define OMAP3_MAX_DPLL_MULT 2048
static struct clk osc_sys_ck = {
.name = "osc_sys_ck",
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_PRM_CLKSEL,
+ .clksel_reg = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
.clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
.clksel = osc_sys_clksel,
/* REVISIT: deal with autoextclkmode? */
.name = "sys_ck",
.parent = &osc_sys_ck,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
+ .clksel_reg = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
.clksel_mask = OMAP_SYSCLKDIV_MASK,
.clksel = sys_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
static struct clk sys_clkout1 = {
.name = "sys_clkout1",
.parent = &osc_sys_ck,
- .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
+ .enable_reg = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
.enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.recalc = &followparent_recalc,
#define _OMAP34XX_CM_REGADDR(module, reg) \
((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
+#define _OMAP34XX_PRM_REGADDR(module, reg) \
+ ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
+
/* DPLL1 */
/* MPU clock source */
/* Type: DPLL */
{ .parent = NULL }
};
-/*
- * DPLL3 output M2
- * REVISIT: This DPLL output divider must be changed in SRAM, so until
- * that code is ready, this should remain a 'read-only' clksel clock.
- */
+/* DPLL3 output M2 - primary control point for CORE speed */
static struct clk dpll3_m2_ck = {
.name = "dpll3_m2_ck",
.parent = &dpll3_ck,
.clksel = div31_dpll3m2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap3_core_dpll_m2_set_rate,
.recalc = &omap2_clksel_recalc,
};
{ .parent = NULL }
};
+/*
+ * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
+ * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
+ * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
+ * CM_96K_(F)CLK.
+ */
static struct clk omap_96m_alwon_fck = {
.name = "omap_96m_alwon_fck",
.parent = &dpll4_m2x2_ck,
.clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.clksel = omap_96m_alwon_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
- PARENT_CONTROLS_CLOCK,
+ PARENT_CONTROLS_CLOCK,
.recalc = &omap2_clksel_recalc,
};
-static struct clk omap_96m_fck = {
- .name = "omap_96m_fck",
+static struct clk cm_96m_fck = {
+ .name = "cm_96m_fck",
.parent = &omap_96m_alwon_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.recalc = &followparent_recalc,
};
-static const struct clksel cm_96m_fck_clksel[] = {
- { .parent = &sys_ck, .rates = dpll_bypass_rates },
- { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+static const struct clksel_rate omap_96m_dpll_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate omap_96m_sys_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel omap_96m_fck_clksel[] = {
+ { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
+ { .parent = &sys_ck, .rates = omap_96m_sys_rates },
{ .parent = NULL }
};
-static struct clk cm_96m_fck = {
- .name = "cm_96m_fck",
- .parent = &dpll4_m2x2_ck,
+static struct clk omap_96m_fck = {
+ .name = "omap_96m_fck",
+ .parent = &sys_ck,
.init = &omap2_init_clksel_parent,
- .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
- .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
- .clksel = cm_96m_fck_clksel,
+ .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_SOURCE_96M_MASK,
+ .clksel = omap_96m_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.recalc = &omap2_clksel_recalc,
.name = "omap_54m_fck",
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
- .clksel_mask = OMAP3430_SOURCE_54M,
+ .clksel_mask = OMAP3430_SOURCE_54M_MASK,
.clksel = omap_54m_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.recalc = &omap2_clksel_recalc,
};
-static const struct clksel_rate omap_48m_96md2_rates[] = {
+static const struct clksel_rate omap_48m_cm96m_rates[] = {
{ .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
{ .div = 0 }
};
};
static const struct clksel omap_48m_clksel[] = {
- { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
+ { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
{ .parent = &sys_altclk, .rates = omap_48m_alt_rates },
{ .parent = NULL }
};
.name = "omap_48m_fck",
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
- .clksel_mask = OMAP3430_SOURCE_48M,
+ .clksel_mask = OMAP3430_SOURCE_48M_MASK,
.clksel = omap_48m_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
};
static const struct clksel clkout2_src_clksel[] = {
- { .parent = &core_ck, .rates = clkout2_src_core_rates },
- { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
- { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates },
- { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
+ { .parent = &core_ck, .rates = clkout2_src_core_rates },
+ { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
+ { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
+ { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
{ .parent = NULL }
};
.clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
.clksel = clkout2_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
- .clkdm_name = "core_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel = mpu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "mpu_clkdm",
+ .clkdm = { .name = "mpu_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
.clksel = iva2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
- .clkdm_name = "iva2_clkdm",
+ .clkdm = { .name = "iva2_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel = div2_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel = div2_l3_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel = gfx_l3_clksel,
.flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "gfx_3430es1_clkdm",
+ .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.name = "gfx_l3_ick",
.parent = &gfx_l3_ck,
.flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
- .clkdm_name = "gfx_3430es1_clkdm",
+ .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
- .clkdm_name = "gfx_3430es1_clkdm",
+ .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
- .clkdm_name = "gfx_3430es1_clkdm",
+ .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &followparent_recalc,
};
.clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
.clksel = sgx_clksel,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "sgx_clkdm",
+ .clkdm = { .name = "sgx_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "sgx_clkdm",
+ .clkdm = { .name = "sgx_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
- .clkdm_name = "d2d_clkdm",
+ .clkdm = { .name = "d2d_clkdm" },
.recalc = &followparent_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.parent = &omap_96m_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
.clksel = mcbsp_15_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
.clksel = mcbsp_15_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.parent = &omap_48m_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.parent = &omap_12m_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SDRC_SHIFT,
.flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
.parent = &core_l3_ick,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
ENABLE_ON_INIT,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_ICR_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_AES2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_DES2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
.clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.clksel = dss1_alwon_fck_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "cam_clkdm",
+ .clkdm = { .name = "cam_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "cam_clkdm",
+ .clkdm = { .name = "cam_clkdm" },
+ .recalc = &followparent_recalc,
+};
+
+static struct clk csi2_96m_fck = {
+ .name = "csi2_96m_fck",
+ .parent = &core_96m_fck,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_CSI2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "cam_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "usbhost_clkdm",
+ .clkdm = { .name = "usbhost_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "usbhost_clkdm",
+ .clkdm = { .name = "usbhost_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "usbhost_clkdm",
+ .clkdm = { .name = "usbhost_clkdm" },
.recalc = &followparent_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.init = &omap2_init_clk_clkdm,
.parent = &omap_32k_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.name = "wkup_l4_ick",
.parent = &sys_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
static struct clk per_32k_alwon_fck = {
.name = "per_32k_alwon_fck",
.parent = &omap_32k_fck,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};
static const struct clksel mcbsp_234_clksel[] = {
- { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
- { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+ { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+ { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
{ .parent = NULL }
};
.clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_MUX_CTRL_MASK,
.clksel = emu_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
.clksel = pclk_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
.clksel = pclkx2_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
.clksel = atclk_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
.clksel = emu_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
.clksel = traceclk_clksel,
.flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};
.name = "sr_l4_ick",
.parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
&dss_ick,
&cam_mclk,
&cam_ick,
+ &csi2_96m_fck,
&usbhost_120m_fck,
&usbhost_48m_fck,
&usbhost_ick,