/*
* OMAP3 clock framework
*
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
*
* Written by Paul Walmsley
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+#include <asm/arch/control.h>
+
#include "clock.h"
#include "cm.h"
-#include "cm_regbits_34xx.h"
+#include "cm-regbits-34xx.h"
#include "prm.h"
-#include "prm_regbits_34xx.h"
-#include "control.h"
+#include "prm-regbits-34xx.h"
static void omap3_dpll_recalc(struct clk *clk);
static void omap3_clkoutx2_recalc(struct clk *clk);
* DPLL2 supplies clock to the IVA2.
* DPLL3 supplies CORE domain clocks.
* DPLL4 supplies peripheral clocks.
+ * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
*/
/* PRM CLOCKS */
.recalc = &propagate_rate,
};
-/* 3430ES2 only */
static struct clk virt_16_8m_ck = {
.name = "virt_16_8m_ck",
.rate = 16800000,
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
.recalc = &propagate_rate,
};
{ .div = 0 }
};
-/* 3430ES2 only */
static const struct clksel_rate osc_sys_16_8m_rates[] = {
- { .div = 1, .val = 5, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
{ .div = 0 }
};
{ .div = 0 }
};
-static const struct clksel div2_dpll3m2_clksel[] = {
- { .parent = &dpll3_ck, .rates = div2_rates },
+static const struct clksel_rate div31_dpll3_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
+ { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
+ { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
+ { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
+ { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
+ { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
+ { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
+ { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
+ { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
+ { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
+ { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
+ { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
+ { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
+ { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
+ { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
+ { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
+ { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
+ { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
+ { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
+ { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
+ { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
+ { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
+ { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
+ { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
+ { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
+ { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
+ { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
+ { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
+ { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
+ { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
+ { .div = 0 },
+};
+
+static const struct clksel div31_dpll3m2_clksel[] = {
+ { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
{ .parent = NULL }
};
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
- .clksel = div2_dpll3m2_clksel,
+ .clksel = div31_dpll3m2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.recalc = &omap2_clksel_recalc,
.recalc = &followparent_recalc,
};
+/* DPLL5 */
+/* Supplies 120MHz clock, USIM source clock */
+/* Type: DPLL */
+/* 3430ES2 only */
+static const struct dpll_data dpll5_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+ .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+ .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+ .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+ .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+ .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+ .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll5_ck = {
+ .name = "dpll5_ck",
+ .parent = &sys_ck,
+ .dpll_data = &dpll5_dd,
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll5m2_clksel[] = {
+ { .parent = &dpll5_ck, .rates = div16_dpll_rates },
+ { .parent = NULL }
+};
+
+static struct clk dpll5_m2_ck = {
+ .name = "dpll5_m2_ck",
+ .parent = &dpll5_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+ .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
+ .clksel = div16_dpll5m2_clksel,
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk omap_120m_fck = {
+ .name = "omap_120m_fck",
+ .parent = &dpll5_m2_ck,
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+ .recalc = &followparent_recalc,
+};
/* CM EXTERNAL CLOCK OUTPUTS */
/* GFX power domain */
-/* REVISIT: These clocks have disappeared in the 3430 ES2 TRM ?? */
+/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
static const struct clksel gfx_l3_clksel[] = {
{ .parent = &l3_ick, .rates = gfx_l3_rates },
.clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
.clksel = gfx_l3_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
.parent = &l3_ick,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
.name = "gfx_cg1_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
- .enable_bit = OMAP3430_EN_2D_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
.name = "gfx_cg2_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
- .enable_bit = OMAP3430_EN_3D_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .recalc = &followparent_recalc,
+};
+
+/* SGX power domain - 3430ES2 only */
+
+static const struct clksel_rate sgx_core_rates[] = {
+ { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 4, .val = 1, .flags = RATE_IN_343X },
+ { .div = 6, .val = 2, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel_rate sgx_96m_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel sgx_clksel[] = {
+ { .parent = &core_ck, .rates = sgx_core_rates },
+ { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+ { .parent = NULL },
+};
+
+static struct clk sgx_fck = {
+ .name = "sgx_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
+ .clksel = sgx_clksel,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk sgx_ick = {
+ .name = "sgx_ick",
+ .parent = &l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
.recalc = &followparent_recalc,
};
.name = "d2d_26m_fck",
.parent = &sys_ck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP3430_EN_D2D_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
.recalc = &omap2_clksel_recalc,
};
+static struct clk cpefuse_fck = {
+ .name = "cpefuse_fck",
+ .parent = &sys_ck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+ .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk ts_fck = {
+ .name = "ts_fck",
+ .parent = &omap_32k_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+ .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbtll_fck = {
+ .name = "usbtll_fck",
+ .parent = &omap_120m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+ .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
/* CORE 96M FCLK-derived clocks */
static struct clk core_96m_fck = {
.recalc = &followparent_recalc,
};
-static struct clk mmc2_fck = {
- .name = "mmc2_fck",
+static struct clk mmchs3_fck = {
+ .name = "mmchs_fck",
+ .id = 3,
+ .parent = &core_96m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+ .name = "mmchs_fck",
+ .id = 2,
.parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.recalc = &followparent_recalc,
};
-static struct clk mmc1_fck = {
- .name = "mmc1_fck",
+static struct clk mmchs1_fck = {
+ .name = "mmchs_fck",
+ .id = 1,
.parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
};
static struct clk mcspi4_fck = {
- .name = "mcspi4_fck",
+ .name = "mcspi_fck",
+ .id = 4,
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
};
static struct clk mcspi3_fck = {
- .name = "mcspi3_fck",
+ .name = "mcspi_fck",
+ .id = 3,
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
};
static struct clk mcspi2_fck = {
- .name = "mcspi2_fck",
+ .name = "mcspi_fck",
+ .id = 2,
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
};
static struct clk mcspi1_fck = {
- .name = "mcspi1_fck",
+ .name = "mcspi_fck",
+ .id = 1,
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.name = "fshostusb_fck",
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP3430_EN_FSHOSTUSB_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
.recalc = &followparent_recalc,
};
+static struct clk usbtll_ick = {
+ .name = "usbtll_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs3_ick = {
+ .name = "mmchs_ick",
+ .id = 3,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
/* Intersystem Communication Registers - chassis mode only */
static struct clk icr_ick = {
.name = "icr_ick",
.recalc = &followparent_recalc,
};
-static struct clk mmc2_ick = {
- .name = "mmc2_ick",
+static struct clk mmchs2_ick = {
+ .name = "mmchs_ick",
+ .id = 2,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.recalc = &followparent_recalc,
};
-static struct clk mmc1_ick = {
- .name = "mmc1_ick",
+static struct clk mmchs1_ick = {
+ .name = "mmchs_ick",
+ .id = 1,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
};
static struct clk mcspi4_ick = {
- .name = "mcspi4_ick",
+ .name = "mcspi_ick",
+ .id = 4,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
};
static struct clk mcspi3_ick = {
- .name = "mcspi3_ick",
+ .name = "mcspi_ick",
+ .id = 3,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
};
static struct clk mcspi2_ick = {
- .name = "mcspi2_ick",
+ .name = "mcspi_ick",
+ .id = 2,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
};
static struct clk mcspi1_ick = {
- .name = "mcspi1_ick",
+ .name = "mcspi_ick",
+ .id = 1,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.name = "fac_ick",
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
- .enable_bit = OMAP3430_EN_FAC_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
.parent = &l4_ick,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
- .enable_bit = OMAP3430_EN_FSHOSTUSB_SHIFT,
+ .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
- .clksel_mask = OMAP3430_CLKSEL_FSHOSTUSB_MASK,
+ .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
.clksel = usb_l4_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &omap2_clksel_recalc,
};
.recalc = &followparent_recalc,
};
-static struct clk dss_l3_ick = {
- .name = "dss_l3_ick",
- .parent = &l3_ick,
- .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
- .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
- .recalc = &followparent_recalc,
-};
-
-static struct clk dss_l4_ick = {
- .name = "dss_l4_ick",
+static struct clk dss_ick = {
+ /* Handles both L3 and L4 clocks */
+ .name = "dss_ick",
.parent = &l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.recalc = &followparent_recalc,
};
+/* USBHOST - 3430ES2 only */
+
+static struct clk usbhost_120m_fck = {
+ .name = "usbhost_120m_fck",
+ .parent = &omap_120m_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbhost_48m_fck = {
+ .name = "usbhost_48m_fck",
+ .parent = &omap_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbhost_l3_ick = {
+ .name = "usbhost_l3_ick",
+ .parent = &l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbhost_l4_ick = {
+ .name = "usbhost_l4_ick",
+ .parent = &l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbhost_sar_fck = {
+ .name = "usbhost_sar_fck",
+ .parent = &osc_sys_ck,
+ .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
+ .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
/* WKUP */
+static const struct clksel_rate usim_96m_rates[] = {
+ { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 4, .val = 4, .flags = RATE_IN_343X },
+ { .div = 8, .val = 5, .flags = RATE_IN_343X },
+ { .div = 10, .val = 6, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel_rate usim_120m_rates[] = {
+ { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 8, .val = 8, .flags = RATE_IN_343X },
+ { .div = 16, .val = 9, .flags = RATE_IN_343X },
+ { .div = 20, .val = 10, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel usim_clksel[] = {
+ { .parent = &omap_96m_fck, .rates = usim_96m_rates },
+ { .parent = &omap_120m_fck, .rates = usim_120m_rates },
+ { .parent = &sys_ck, .rates = div2_rates },
+ { .parent = NULL },
+};
+
+/* 3430ES2 only */
+static struct clk usim_fck = {
+ .name = "usim_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
+ .clksel = usim_clksel,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &omap2_clksel_recalc,
+};
+
static struct clk gpt1_fck = {
.name = "gpt1_fck",
.init = &omap2_init_clksel_parent,
.recalc = &followparent_recalc,
};
+/* 3430ES2 only */
+/* Never specifically named in the TRM, so we have to infer a likely name */
+static struct clk usim_ick = {
+ .name = "usim_ick",
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
static struct clk wdt2_ick = {
.name = "wdt2_ick",
.parent = &wkup_l4_ick,
static struct clk mcbsp2_fck = {
.name = "mcbsp2_fck",
.init = &omap2_init_clksel_parent,
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
.clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
static struct clk mcbsp3_fck = {
.name = "mcbsp3_fck",
.init = &omap2_init_clksel_parent,
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
.clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
static struct clk mcbsp4_fck = {
.name = "mcbsp4_fck",
.init = &omap2_init_clksel_parent,
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
.clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
&osc_sys_ck,
&sys_ck,
&sys_altclk,
+ &mcbsp_clks,
&sys_clkout1,
&dpll1_ck,
&emu_mpu_alwon_ck,
&dpll4_m5x2_ck,
&dpll4_m6x2_ck,
&emu_per_alwon_ck,
+ &dpll5_ck,
+ &dpll5_m2_ck,
+ &omap_120m_fck,
&clkout2_src_ck,
&sys_clkout2,
&corex2_fck,
&gfx_l3_ick,
&gfx_cg1_ck,
&gfx_cg2_ck,
+ &sgx_fck,
+ &sgx_ick,
&d2d_26m_fck,
&gpt10_fck,
&gpt11_fck,
+ &cpefuse_fck,
+ &ts_fck,
+ &usbtll_fck,
&core_96m_fck,
- &mmc2_fck,
+ &mmchs3_fck,
+ &mmchs2_fck,
&mspro_fck,
- &mmc1_fck,
+ &mmchs1_fck,
&i2c3_fck,
&i2c2_fck,
&i2c1_fck,
&security_l3_ick,
&pka_ick,
&core_l4_ick,
+ &usbtll_ick,
+ &mmchs3_ick,
&icr_ick,
&aes2_ick,
&sha12_ick,
&des2_ick,
- &mmc2_ick,
- &mmc1_ick,
+ &mmchs2_ick,
+ &mmchs1_ick,
&mspro_ick,
&hdq_ick,
&mcspi4_ick,
&dss_tv_fck,
&dss_96m_fck,
&dss2_alwon_fck,
- &dss_l3_ick,
- &dss_l4_ick,
+ &dss_ick,
&cam_mclk,
&cam_l3_ick,
&cam_l4_ick,
+ &usbhost_120m_fck,
+ &usbhost_48m_fck,
+ &usbhost_l3_ick,
+ &usbhost_l4_ick,
+ &usbhost_sar_fck,
+ &usim_fck,
&gpt1_fck,
&wkup_32k_fck,
&gpio1_fck,
&wdt2_fck,
&wkup_l4_ick,
+ &usim_ick,
&wdt2_ick,
&wdt1_ick,
&gpio1_ick,
projects / linux-2.6-omap-h63xx.git / blobdiff