OMAP3 clock: avoid invalid FREQSEL values during DPLL rate rounding

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.h

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 8ce7097544f52063ed61fb54bf222b80ad8ea52f..0b95fcbb51f1987d7087f739efc51f1158310c0e 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -292,6 +292,7 @@ static struct dpll_data dpll1_dd = {
        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
        .bypass_clk     = &dpll1_fck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -367,6 +368,7 @@ static struct dpll_data dpll2_dd = {
        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
        .bypass_clk     = &dpll2_fck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -429,6 +431,7 @@ static struct dpll_data dpll3_dd = {
        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -594,6 +597,7 @@ static struct dpll_data dpll4_dd = {
        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -920,6 +924,7 @@ static struct dpll_data dpll5_dd = {
        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -2304,7 +2309,7 @@ static struct clk dss1_alwon_fck_3430es1 = {
        .prcm_mod       = OMAP3430_DSS_MOD,
        .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X,
+       .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "dss_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -2317,7 +2322,7 @@ static struct clk dss1_alwon_fck_3430es2 = {
        .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
        .idlest_bit     = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
+       .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
        .clkdm          = { .name = "dss_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -2519,8 +2524,8 @@ static struct clk wkup_32k_fck = {
        .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio1_fck = {
-       .name           = "gpio1_fck",
+static struct clk gpio1_dbck = {
+       .name           = "gpio1_dbck",
        .parent         = &wkup_32k_fck,
        .prcm_mod       = WKUP_MOD,
        .enable_reg     = CM_FCLKEN,
@@ -2797,8 +2802,8 @@ static struct clk per_32k_alwon_fck = {
        .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio6_fck = {
-       .name           = "gpio6_fck",
+static struct clk gpio6_dbck = {
+       .name           = "gpio6_dbck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
        .enable_reg     = CM_FCLKEN,
@@ -2809,8 +2814,8 @@ static struct clk gpio6_fck = {
        .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio5_fck = {
-       .name           = "gpio5_fck",
+static struct clk gpio5_dbck = {
+       .name           = "gpio5_dbck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
        .enable_reg     = CM_FCLKEN,
@@ -2821,8 +2826,8 @@ static struct clk gpio5_fck = {
        .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio4_fck = {
-       .name           = "gpio4_fck",
+static struct clk gpio4_dbck = {
+       .name           = "gpio4_dbck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
        .enable_reg     = CM_FCLKEN,
@@ -2833,8 +2838,8 @@ static struct clk gpio4_fck = {
        .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio3_fck = {
-       .name           = "gpio3_fck",
+static struct clk gpio3_dbck = {
+       .name           = "gpio3_dbck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
        .enable_reg     = CM_FCLKEN,
@@ -2845,8 +2850,8 @@ static struct clk gpio3_fck = {
        .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio2_fck = {
-       .name           = "gpio2_fck",
+static struct clk gpio2_dbck = {
+       .name           = "gpio2_dbck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
        .enable_reg     = CM_FCLKEN,
@@ -3545,7 +3550,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
        &usim_fck,
        &gpt1_fck,
        &wkup_32k_fck,
-       &gpio1_fck,
+       &gpio1_dbck,
        &wdt2_fck,
        &wkup_l4_ick,
        &usim_ick,
@@ -3567,11 +3572,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
        &gpt8_fck,
        &gpt9_fck,
        &per_32k_alwon_fck,
-       &gpio6_fck,
-       &gpio5_fck,
-       &gpio4_fck,
-       &gpio3_fck,
-       &gpio2_fck,
+       &gpio6_dbck,
+       &gpio5_dbck,
+       &gpio4_dbck,
+       &gpio3_dbck,
+       &gpio2_dbck,
        &wdt3_fck,
        &per_l4_ick,
        &gpio6_ick,