[ARM] OMAP2 SDRC: move mach-omap2/memory.h into mach/sdrc.h

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.c

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index cb5e068feb56a7e87bafb1a16ab8b1c673901421..52385b1506e02c0eabf5dda9ac00fdf8dc10816a 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -32,7 +32,7 @@
 #include <asm/div64.h>
 #include <asm/clkdev.h>
 
-#include "memory.h"
+#include <mach/sdrc.h>
 #include "clock.h"
 #include "prm.h"
 #include "prm-regbits-34xx.h"
@@ -314,14 +314,12 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
        const struct dpll_data *dd;
        int i = 0;
        int ret = -EINVAL;
-       u32 idlest_mask;
 
        dd = clk->dpll_data;
 
-       state <<= dd->idlest_bit;
-       idlest_mask = 1 << dd->idlest_bit;
+       state <<= __ffs(dd->idlest_mask);
 
-       while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
+       while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
               i < MAX_DPLL_WAIT_TRIES) {
                i++;
                udelay(1);
@@ -400,19 +398,14 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
 
        ai = omap3_dpll_autoidle_read(clk);
 
+       omap3_dpll_deny_idle(clk);
+
        _omap3_dpll_write_clken(clk, DPLL_LOCKED);
 
-       if (ai) {
-               /*
-                * If no downstream clocks are enabled, CM_IDLEST bit
-                * may never become active, so don't wait for DPLL to lock.
-                */
-               r = 0;
+       r = _omap3_wait_dpll_status(clk, 1);
+
+       if (ai)
                omap3_dpll_allow_idle(clk);
-       } else {
-               r = _omap3_wait_dpll_status(clk, 1);
-               omap3_dpll_deny_idle(clk);
-       };
 
        return r;
 }
@@ -563,14 +556,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
        /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
        _omap3_noncore_dpll_bypass(clk);
 
+       /* Set jitter correction */
+       v = __raw_readl(dd->control_reg);
+       v &= ~dd->freqsel_mask;
+       v |= freqsel << __ffs(dd->freqsel_mask);
+       __raw_writel(v, dd->control_reg);
+
+       /* Set DPLL multiplier, divider */
        v = __raw_readl(dd->mult_div1_reg);
        v &= ~(dd->mult_mask | dd->div1_mask);
-
-       /* Set mult (M), div1 (N), freqsel */
        v |= m << __ffs(dd->mult_mask);
-       v |= n << __ffs(dd->div1_mask);
-       v |= freqsel << __ffs(dd->freqsel_mask);
-
+       v |= (n - 1) << __ffs(dd->div1_mask);
        __raw_writel(v, dd->mult_div1_reg);
 
        /* We let the clock framework set the other output dividers later */