]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - arch/arm/mach-omap2/clock24xx.h
projects / linux-2.6-omap-h63xx.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
ARM: OMAP: Update PRCM rate-table entries for 2430
[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock24xx.h
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index d0c406d7f59cbd032aebc234ed028304bd88cb89..e065d88e4e27fe2f077814058c08880ae762f90c 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -244,7 +244,6 @@ struct prcm_config {
 
 /*
  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
- * #2  (ratio1) baseport-target
  * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
  */
 #define M5A_DPLL_MULT_12               (133 << 12)
@@ -252,13 +251,13 @@ struct prcm_config {
 #define M5A_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
                                        M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
                                        MX_APLLS_CLIKIN_12
-#define M5A_DPLL_MULT_13               (266 << 12)
-#define M5A_DPLL_DIV_13                        (12 << 8)
+#define M5A_DPLL_MULT_13               (61 << 12)
+#define M5A_DPLL_DIV_13                        (2 << 8)
 #define M5A_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
                                        M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
                                        MX_APLLS_CLIKIN_13
-#define M5A_DPLL_MULT_19               (180 << 12)
-#define M5A_DPLL_DIV_19                        (12 << 8)
+#define M5A_DPLL_MULT_19               (55 << 12)
+#define M5A_DPLL_DIV_19                        (3 << 8)
 #define M5A_CM_CLKSEL1_PLL_19_VAL      MX_48M_SRC | MX_54M_SRC | \
                                        M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
                                        MX_APLLS_CLIKIN_19_2
@@ -280,7 +279,27 @@ struct prcm_config {
                                        M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
                                        MX_APLLS_CLIKIN_19_2
 /*
- * #4  (ratio2)
+ * #4  (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
+ */
+#define M4_DPLL_MULT_12                        (133 << 12)
+#define M4_DPLL_DIV_12                 (3 << 8)
+#define M4_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                       M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
+                                       MX_APLLS_CLIKIN_12
+
+#define M4_DPLL_MULT_13                        (399 << 12)
+#define M4_DPLL_DIV_13                 (12 << 8)
+#define M4_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                       M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
+                                       MX_APLLS_CLIKIN_13
+
+#define M4_DPLL_MULT_19                        (145 << 12)
+#define M4_DPLL_DIV_19                 (6 << 8)
+#define M4_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                       M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
+                                       MX_APLLS_CLIKIN_19_2
+
+/*
  * #3  (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
  */
 #define M3_DPLL_MULT_12                        (55 << 12)
@@ -288,16 +307,41 @@ struct prcm_config {
 #define M3_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
                                        M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
                                        MX_APLLS_CLIKIN_12
-#define M3_DPLL_MULT_13                        (330 << 12)
-#define M3_DPLL_DIV_13                 (12 << 8)
+#define M3_DPLL_MULT_13                        (76 << 12)
+#define M3_DPLL_DIV_13                 (2 << 8)
 #define M3_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
                                        M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
                                        MX_APLLS_CLIKIN_13
-#define M3_DPLL_MULT_19                        (275 << 12)
-#define M3_DPLL_DIV_19                 (15 << 8)
+#define M3_DPLL_MULT_19                        (17 << 12)
+#define M3_DPLL_DIV_19                 (0 << 8)
 #define M3_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
                                        M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
                                        MX_APLLS_CLIKIN_19_2
+
+/*
+ * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
+ */
+#define M2_DPLL_MULT_12                        (55 << 12)
+#define M2_DPLL_DIV_12                 (1 << 8)
+#define M2_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                       M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
+                                       MX_APLLS_CLIKIN_12
+
+/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
+ * relock time issue */
+/* Core frequency changed from 330/165 to 329/164 MHz*/
+#define M2_DPLL_MULT_13                        (76 << 12)
+#define M2_DPLL_DIV_13                 (2 << 8)
+#define M2_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                       M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
+                                       MX_APLLS_CLIKIN_13
+
+#define M2_DPLL_MULT_19                        (17 << 12)
+#define M2_DPLL_DIV_19                 (0 << 8)
+#define M2_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                       M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
+                                       MX_APLLS_CLIKIN_19_2
+
 /* boot (boot) */
 #define MB_DPLL_MULT                   (1 << 12)
 #define MB_DPLL_DIV                    (0 << 8)
@@ -370,15 +414,21 @@ struct prcm_config {
 #define S100M  100000000
 #define S133M  133000000
 #define S150M  150000000
+#define S164M  164000000
 #define S165M  165000000
+#define S199M  199000000
 #define S200M  200000000
 #define S266M  266000000
 #define S300M  300000000
+#define S329M  329000000
 #define S330M  330000000
+#define S399M  399000000
 #define S400M  400000000
 #define S532M  532000000
 #define S600M  600000000
+#define S658M  658000000
 #define S660M  660000000
+#define S798M  798000000
 
 /*-------------------------------------------------------------------------
  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
@@ -472,12 +522,20 @@ static struct prcm_config rate_table[] = {
                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
                RATE_IN_242X},
 
-       /* PRCM #3 - ratio2 (ES2) - FAST */
-       {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+       /* PRCM #4 - ratio2 (ES2.1) - FAST */
+       {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-               R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
+               R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
-               SDRC_RFR_CTRL_110MHz,
+               SDRC_RFR_CTRL_133MHz,
+               RATE_IN_243X},
+
+       /* PRCM #2 - ratio1 (ES2) - FAST */
+       {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+               R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+               R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+               MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+               SDRC_RFR_CTRL_165MHz,
                RATE_IN_243X},
 
        /* PRCM #5a - ratio1 - FAST */
@@ -496,12 +554,20 @@ static struct prcm_config rate_table[] = {
                SDRC_RFR_CTRL_100MHz,
                RATE_IN_243X},
 
-       /* PRCM #3 - ratio2 (ES2) - SLOW */
-       {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
+       /* PRCM #4 - ratio1 (ES2.1) - SLOW */
+       {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-               R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
+               R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
-               SDRC_RFR_CTRL_110MHz,
+               SDRC_RFR_CTRL_133MHz,
+               RATE_IN_243X},
+
+       /* PRCM #2 - ratio1 (ES2) - SLOW */
+       {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
+               R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+               R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+               MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+               SDRC_RFR_CTRL_165MHz,
                RATE_IN_243X},
 
        /* PRCM #5a - ratio1 - SLOW */
@@ -608,8 +674,6 @@ static const struct dpll_data dpll_dd = {
        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
-       .auto_idle_mask         = OMAP24XX_AUTO_DPLL_MASK,
-       .auto_idle_val          = 0x3, /* stop DPLL upon idle */
 };
 
 static struct clk dpll_ck = {
@@ -965,7 +1029,7 @@ static struct clk iva2_1_fck = {
        .parent         = &core_ck,
        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES |
                                CONFIG_PARTICIPANT,
-       .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
@@ -1027,7 +1091,7 @@ static struct clk dsp_fck = {
        .parent         = &core_ck,
        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP |
                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
-       .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
@@ -1082,7 +1146,7 @@ static struct clk iva1_ifck = {
        .parent         = &core_ck,
        .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
                                RATE_PROPAGATES | DELAYED_APP,
-       .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
@@ -1097,7 +1161,7 @@ static struct clk iva1_mpu_int_ifck = {
        .name           = "iva1_mpu_int_ifck",
        .parent         = &iva1_ifck,
        .flags          = CLOCK_IN_OMAP242X,
-       .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
        .fixed_div      = 2,
        .recalc         = &omap2_fixed_divisor_recalc,
@@ -1232,20 +1296,9 @@ static struct clk ssi_ssr_sst_fck = {
  */
 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
 
-/*
- * These clksel_rate/clksel structs are shared between gfx_3d_fck and
- * gfx_2d_fck
- */
-static const struct clksel_rate gfx_fck_core_l3_rates[] = {
-       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-       { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
-       { .div = 3, .val = 3, .flags = RATE_IN_243X },
-       { .div = 4, .val = 4, .flags = RATE_IN_243X },
-       { .div = 0 }
-};
-
+/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
 static const struct clksel gfx_fck_clksel[] = {
-       { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates },
+       { .parent = &core_l3_ck, .rates = gfx_l3_rates },
        { .parent = NULL },
 };
 
@@ -1253,7 +1306,7 @@ static struct clk gfx_3d_fck = {
        .name           = "gfx_3d_fck",
        .parent         = &core_l3_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
@@ -1267,7 +1320,7 @@ static struct clk gfx_2d_fck = {
        .name           = "gfx_2d_fck",
        .parent         = &core_l3_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
@@ -1324,7 +1377,7 @@ static struct clk mdm_osc_ck = {
        .name           = "mdm_osc_ck",
        .parent         = &osc_ck,
        .flags          = CLOCK_IN_OMAP243X,
-       .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1474,22 +1527,12 @@ static struct clk dss_54m_fck = {       /* Alt clk used in power management */
  * here will likely have an L4 interface parent, and may have multiple
  * functional clock parents.
  */
-static const struct clksel_rate gpt_32k_rates[] = {
-       { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
-       { .div = 0 }
-};
-
-static const struct clksel_rate gpt_sys_rates[] = {
-       { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
-       { .div = 0 }
-};
-
 static const struct clksel_rate gpt_alt_rates[] = {
        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
        { .div = 0 }
 };
 
-static const struct clksel gpt_clksel[] = {
+static const struct clksel omap24xx_gpt_clksel[] = {
        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
        { .parent = &sys_ck,      .rates = gpt_sys_rates },
        { .parent = &alt_ck,      .rates = gpt_alt_rates },
@@ -1509,12 +1552,12 @@ static struct clk gpt1_fck = {
        .name           = "gpt1_fck",
        .parent         = &func_32k_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
        .round_rate     = &omap2_clksel_round_rate,
        .set_rate       = &omap2_clksel_set_rate
@@ -1538,7 +1581,7 @@ static struct clk gpt2_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1560,7 +1603,7 @@ static struct clk gpt3_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1582,7 +1625,7 @@ static struct clk gpt4_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1604,7 +1647,7 @@ static struct clk gpt5_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1626,7 +1669,7 @@ static struct clk gpt6_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1648,7 +1691,7 @@ static struct clk gpt7_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1670,7 +1713,7 @@ static struct clk gpt8_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1692,7 +1735,7 @@ static struct clk gpt9_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1714,7 +1757,7 @@ static struct clk gpt10_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1736,7 +1779,7 @@ static struct clk gpt11_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1758,7 +1801,7 @@ static struct clk gpt12_fck = {
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
        .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
-       .clksel         = gpt_clksel,
+       .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1979,7 +2022,7 @@ static struct clk gpios_fck = {
        .name           = "gpios_fck",
        .parent         = &func_32k_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1997,7 +2040,7 @@ static struct clk mpu_wdt_fck = {
        .name           = "mpu_wdt_fck",
        .parent         = &func_32k_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2495,7 +2538,7 @@ static struct clk virt_prcm_set = {
        .round_rate     = &omap2_round_to_table_rate,
 };
 
-static struct clk *onchip_clks[] __initdata = {
+static struct clk *onchip_24xx_clks[] __initdata = {
        /* external root sources */
        &func_32k_ck,
        &osc_ck,
Unnamed repository; edit this file 'description' to name the repository.