static void omap2_osc_clk_recalc(struct clk *clk);
static void omap2_sys_clk_recalc(struct clk *clk);
static void omap2_dpllcore_recalc(struct clk *clk);
-static int omap2_clk_fixed_enable(struct clk *clk);
-static void omap2_clk_fixed_disable(struct clk *clk);
-static int omap2_enable_osc_ck(struct clk *clk);
-static void omap2_disable_osc_ck(struct clk *clk);
static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
/* Base external input clocks */
static struct clk func_32k_ck = {
.name = "func_32k_ck",
+ .ops = &clkops_null,
.rate = 32000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+ RATE_FIXED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &propagate_rate,
};
/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
.name = "osc_ck",
+ .ops = &clkops_oscck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
- .enable = &omap2_enable_osc_ck,
- .disable = &omap2_disable_osc_ck,
.recalc = &omap2_osc_clk_recalc,
};
/* Without modem likely 12MHz, with modem likely 13MHz */
static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
.name = "sys_ck", /* ~ ref_clk also */
+ .ops = &clkops_null,
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- ALWAYS_ENABLED | RATE_PROPAGATES,
+ RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_sys_clk_recalc,
};
static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
.name = "alt_ck",
+ .ops = &clkops_null,
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+ RATE_FIXED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &propagate_rate,
};
*/
static struct clk dpll_ck = {
.name = "dpll_ck",
+ .ops = &clkops_null,
.parent = &sys_ck, /* Can be func_32k also */
.dpll_data = &dpll_dd,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_PROPAGATES | ALWAYS_ENABLED,
+ RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_dpllcore_recalc,
.set_rate = &omap2_reprogram_dpllcore,
static struct clk apll96_ck = {
.name = "apll96_ck",
+ .ops = &clkops_fixed,
.parent = &sys_ck,
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
- .enable = &omap2_clk_fixed_enable,
- .disable = &omap2_clk_fixed_disable,
.recalc = &propagate_rate,
};
static struct clk apll54_ck = {
.name = "apll54_ck",
+ .ops = &clkops_fixed,
.parent = &sys_ck,
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
- .enable = &omap2_clk_fixed_enable,
- .disable = &omap2_clk_fixed_disable,
.recalc = &propagate_rate,
};
static struct clk func_54m_ck = {
.name = "func_54m_ck",
+ .ops = &clkops_null,
.parent = &apll54_ck, /* can also be alt_clk */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+ RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
static struct clk core_ck = {
.name = "core_ck",
+ .ops = &clkops_null,
.parent = &dpll_ck, /* can also be 32k */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- ALWAYS_ENABLED | RATE_PROPAGATES,
+ RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
/* The parent of this clock is not selectable on 2420. */
static struct clk func_96m_ck = {
.name = "func_96m_ck",
+ .ops = &clkops_null,
.parent = &apll96_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+ RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
static struct clk func_48m_ck = {
.name = "func_48m_ck",
+ .ops = &clkops_null,
.parent = &apll96_ck, /* 96M or Alt */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+ RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
static struct clk func_12m_ck = {
.name = "func_12m_ck",
+ .ops = &clkops_null,
.parent = &func_48m_ck,
.fixed_div = 4,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+ RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_fixed_divisor_recalc,
};
/* Secure timer, only available in secure mode */
static struct clk wdt1_osc_ck = {
.name = "ck_wdt1_osc",
+ .ops = &clkops_null, /* RMK: missing? */
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.recalc = &followparent_recalc,
static struct clk sys_clkout_src = {
.name = "sys_clkout_src",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES,
static struct clk sys_clkout = {
.name = "sys_clkout",
+ .ops = &clkops_null,
.parent = &sys_clkout_src,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- PARENT_CONTROLS_CLOCK,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "wkup_clkdm",
.clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
/* In 2430, new in 2420 ES2 */
static struct clk sys_clkout2_src = {
.name = "sys_clkout2_src",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
/* In 2430, new in 2420 ES2 */
static struct clk sys_clkout2 = {
.name = "sys_clkout2",
+ .ops = &clkops_null,
.parent = &sys_clkout2_src,
- .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
+ .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "wkup_clkdm",
.clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
static struct clk emul_ck = {
.name = "emul_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X,
.clkdm_name = "wkup_clkdm",
static struct clk mpu_ck = { /* Control cpu */
.name = "mpu_ck",
+ .ops = &clkops_null,
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- ALWAYS_ENABLED | DELAYED_APP |
+ DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm_name = "mpu_clkdm",
.init = &omap2_init_clksel_parent,
static struct clk dsp_fck = {
.name = "dsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
/* This clock does not exist as such in the TRM. */
static struct clk dsp_irate_ick = {
.name = "dsp_irate_ick",
+ .ops = &clkops_null,
.parent = &dsp_fck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
- CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
+ CONFIG_PARTICIPANT,
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
.clksel = dsp_irate_ick_clksel,
/* 2420 only */
static struct clk dsp_ick = {
.name = "dsp_ick", /* apparently ipi and isp */
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dsp_irate_ick,
.flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
static struct clk iva2_1_ick = {
.name = "iva2_1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dsp_irate_ick,
.flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
*/
static struct clk iva1_ifck = {
.name = "iva1_ifck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
RATE_PROPAGATES | DELAYED_APP,
/* IVA1 mpu/int/i/f clocks are /2 of parent */
static struct clk iva1_mpu_int_ifck = {
.name = "iva1_mpu_int_ifck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &iva1_ifck,
.flags = CLOCK_IN_OMAP242X,
.clkdm_name = "iva1_clkdm",
static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
.name = "core_l3_ck",
+ .ops = &clkops_null,
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- ALWAYS_ENABLED | DELAYED_APP |
+ DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm_name = "core_l3_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
static struct clk usb_l4_ick = { /* FS-USB interface clock */
.name = "usb_l4_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP | CONFIG_PARTICIPANT,
static struct clk l4_ck = { /* used both as an ick and fck */
.name = "l4_ck",
+ .ops = &clkops_null,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
+ DELAYED_APP | RATE_PROPAGATES,
.clkdm_name = "core_l4_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
static struct clk ssi_ssr_sst_fck = {
.name = "ssi_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
static struct clk gfx_3d_fck = {
.name = "gfx_3d_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "gfx_clkdm",
static struct clk gfx_2d_fck = {
.name = "gfx_2d_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "gfx_clkdm",
static struct clk gfx_ick = {
.name = "gfx_ick", /* From l3 */
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "gfx_clkdm",
static struct clk mdm_ick = { /* used both as a ick and fck */
.name = "mdm_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_ck,
.flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "mdm_clkdm",
static struct clk mdm_osc_ck = {
.name = "mdm_osc_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP243X,
.clkdm_name = "mdm_clkdm",
static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.name = "dss_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck, /* really both l3 and l4 */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "dss_clkdm",
static struct clk dss1_fck = {
.name = "dss1_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_ck, /* Core or sys */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
static struct clk dss2_fck = { /* Alt clk used in power management */
.name = "dss2_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
static struct clk dss_54m_fck = { /* Alt clk used in power management */
.name = "dss_54m_fck", /* 54m tv clk */
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "dss_clkdm",
static struct clk gpt1_ick = {
.name = "gpt1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt1_fck = {
.name = "gpt1_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt2_ick = {
.name = "gpt2_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt2_fck = {
.name = "gpt2_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt3_ick = {
.name = "gpt3_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt3_fck = {
.name = "gpt3_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt4_ick = {
.name = "gpt4_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt4_fck = {
.name = "gpt4_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt5_ick = {
.name = "gpt5_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt5_fck = {
.name = "gpt5_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt6_ick = {
.name = "gpt6_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt6_fck = {
.name = "gpt6_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt7_ick = {
.name = "gpt7_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
static struct clk gpt7_fck = {
.name = "gpt7_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt8_ick = {
.name = "gpt8_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt8_fck = {
.name = "gpt8_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt9_ick = {
.name = "gpt9_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt9_fck = {
.name = "gpt9_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt10_ick = {
.name = "gpt10_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt10_fck = {
.name = "gpt10_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt11_ick = {
.name = "gpt11_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt11_fck = {
.name = "gpt11_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt12_ick = {
.name = "gpt12_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpt12_fck = {
.name = "gpt12_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk mcbsp1_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
static struct clk mcbsp1_fck = {
.name = "mcbsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
static struct clk mcbsp2_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
static struct clk mcbsp2_fck = {
.name = "mcbsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
static struct clk mcbsp3_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk mcbsp3_fck = {
.name = "mcbsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk mcbsp4_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 4,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk mcbsp4_fck = {
.name = "mcbsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 4,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk mcbsp5_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 5,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk mcbsp5_fck = {
.name = "mcbsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 5,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk mcspi1_ick = {
.name = "mcspi_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
static struct clk mcspi1_fck = {
.name = "mcspi_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
static struct clk mcspi2_ick = {
.name = "mcspi_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
static struct clk mcspi2_fck = {
.name = "mcspi_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
static struct clk mcspi3_ick = {
.name = "mcspi_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk mcspi3_fck = {
.name = "mcspi_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk uart1_ick = {
.name = "uart1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk uart1_fck = {
.name = "uart1_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk uart2_ick = {
.name = "uart2_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk uart2_fck = {
.name = "uart2_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk uart3_ick = {
.name = "uart3_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk uart3_fck = {
.name = "uart3_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpios_ick = {
.name = "gpios_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpios_fck = {
.name = "gpios_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "wkup_clkdm",
static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk mpu_wdt_fck = {
.name = "mpu_wdt_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "wkup_clkdm",
static struct clk sync_32k_ick = {
.name = "sync_32k_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
static struct clk wdt1_ick = {
.name = "wdt1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
static struct clk icr_ick = {
.name = "icr_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk cam_ick = {
.name = "cam_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
*/
static struct clk cam_fck = {
.name = "cam_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk wdt4_ick = {
.name = "wdt4_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk wdt4_fck = {
.name = "wdt4_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk wdt3_ick = {
.name = "wdt3_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk wdt3_fck = {
.name = "wdt3_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk mspro_ick = {
.name = "mspro_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk mspro_fck = {
.name = "mspro_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk mmc_ick = {
.name = "mmc_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk mmc_fck = {
.name = "mmc_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk fac_ick = {
.name = "fac_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk fac_fck = {
.name = "fac_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk eac_ick = {
.name = "eac_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk eac_fck = {
.name = "eac_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk hdq_ick = {
.name = "hdq_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk hdq_fck = {
.name = "hdq_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk i2c2_ick = {
.name = "i2c_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
static struct clk i2c2_fck = {
.name = "i2c_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X,
};
static struct clk i2chs2_fck = {
- .name = "i2chs_fck",
+ .name = "i2c_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk i2c1_ick = {
.name = "i2c_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
static struct clk i2c1_fck = {
.name = "i2c_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X,
};
static struct clk i2chs1_fck = {
- .name = "i2chs_fck",
+ .name = "i2c_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk gpmc_fck = {
.name = "gpmc_fck",
+ .ops = &clkops_null, /* RMK: missing? */
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
static struct clk sdma_fck = {
.name = "sdma_fck",
+ .ops = &clkops_null, /* RMK: missing? */
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
static struct clk sdma_ick = {
.name = "sdma_ick",
+ .ops = &clkops_null, /* RMK: missing? */
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
static struct clk vlynq_ick = {
.name = "vlynq_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l3_clkdm",
static struct clk vlynq_fck = {
.name = "vlynq_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | DELAYED_APP,
.clkdm_name = "core_l3_clkdm",
static struct clk sdrc_ick = {
.name = "sdrc_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
static struct clk des_ick = {
.name = "des_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk sha_ick = {
.name = "sha_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk rng_ick = {
.name = "rng_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk aes_ick = {
.name = "aes_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk pka_ick = {
.name = "pka_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
static struct clk usb_fck = {
.name = "usb_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l3_clkdm",
static struct clk usbhs_ick = {
.name = "usbhs_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
static struct clk mmchs1_ick = {
.name = "mmchs_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk mmchs1_fck = {
.name = "mmchs_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
static struct clk mmchs2_ick = {
.name = "mmchs_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk mmchs2_fck = {
.name = "mmchs_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
static struct clk gpio5_ick = {
.name = "gpio5_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk gpio5_fck = {
.name = "gpio5_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk mdm_intc_ick = {
.name = "mdm_intc_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk mmchsdb1_fck = {
.name = "mmchsdb_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
static struct clk mmchsdb2_fck = {
.name = "mmchsdb_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
*/
static struct clk virt_prcm_set = {
.name = "virt_prcm_set",
+ .ops = &clkops_null,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
+ DELAYED_APP,
.parent = &mpu_ck, /* Indexed by mpu speed, no parent */
.recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
.set_rate = &omap2_select_table_rate,
projects / linux-2.6-omap-h63xx.git / blobdiff