ARM: OMAP: Remove OMAP_PRM_REGADDR

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock24xx.c

diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index efe443691eb6b7719ac3b30ffba5687fa11414e5..84a0d10185c5478d754ce470f4bd2d9acdea11ce 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/cpufreq.h>
 
+#include <asm/arch/common.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
 #include <asm/div64.h>
@@ -77,16 +78,16 @@ static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
 static int omap2_enable_osc_ck(struct clk *clk)
 {
 
-       prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0,
-                        OMAP24XX_PRCM_CLKSRC_CTRL);
+       prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0,
+                       OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
 
        return 0;
 }
 
 static void omap2_disable_osc_ck(struct clk *clk)
 {
-       prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
-                        OMAP24XX_PRCM_CLKSRC_CTRL);
+       prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
+                       OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
 }
 
 /* Enable an APLL if off */
@@ -443,7 +444,8 @@ static u32 omap2_get_sysclkdiv(void)
 {
        u32 div;
 
-       div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+       div = prm_read_mod_reg(OMAP24XX_GR_MOD,
+                               OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
        div &= OMAP_SYSCLKDIV_MASK;
        div >>= OMAP_SYSCLKDIV_SHIFT;
 
@@ -499,6 +501,37 @@ static int __init omap2_clk_arch_init(void)
 }
 arch_initcall(omap2_clk_arch_init);
 
+static u32 prm_base;
+static u32 cm_base;
+
+/*
+ * Since we share clock data for 242x and 243x, we need to rewrite some
+ * some register base offsets. Assume offset is at prm_base if flagged,
+ * else assume it's cm_base.
+ */
+static inline void omap2_clk_check_reg(u32 flags, void __iomem **reg)
+{
+       u32 tmp = (__force u32)*reg;
+
+       if ((tmp >> 24) != 0)
+               return;
+
+       if (flags & OFFSET_GR_MOD)
+               tmp += prm_base;
+       else
+               tmp += cm_base;
+
+       *reg = (__force void __iomem *)tmp;
+}
+
+void __init omap2_clk_rewrite_base(struct clk *clk)
+{
+       omap2_clk_check_reg(clk->flags, &clk->clksel_reg);
+       omap2_clk_check_reg(clk->flags, &clk->enable_reg);
+       if (clk->dpll_data)
+               omap2_clk_check_reg(0, &clk->dpll_data->mult_div1_reg);
+}
+
 int __init omap2_clk_init(void)
 {
        struct prcm_config *prcm;
@@ -510,6 +543,12 @@ int __init omap2_clk_init(void)
        else if (cpu_is_omap2430())
                cpu_mask = RATE_IN_243X;
 
+       for (clkp = onchip_24xx_clks;
+            clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
+            clkp++) {
+                       omap2_clk_rewrite_base(*clkp);
+       }
+
        clk_init(&omap2_clk_functions);
 
        omap2_osc_clk_recalc(&osc_ck);
@@ -561,3 +600,9 @@ int __init omap2_clk_init(void)
 
        return 0;
 }
+
+void __init omap2_set_globals_clock24xx(struct omap_globals *omap2_globals)
+{
+       prm_base = (__force u32)omap2_globals->prm;
+       cm_base = (__force u32)omap2_globals->cm;
+}