[ARM] OMAP2 SDRC: move mach-omap2/memory.h into mach/sdrc.h

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock24xx.c

diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 1e9ac83dca5e5449448ca749519faa62804397a6..83911ad48733bfc3e1293b64854b4c242dfbd95a 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -33,7 +33,7 @@
 #include <asm/div64.h>
 #include <asm/clkdev.h>
 
-#include "memory.h"
+#include <mach/sdrc.h>
 #include "clock.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
@@ -112,6 +112,7 @@ static struct omap_clk omap24xx_clks[] = {
        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
        /* L4 domain clocks */
        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
+       CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
        /* virtual meta-group clock */
        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
        /* general l4 interface ck, multi-parent functional clk */
@@ -169,8 +170,8 @@ static struct omap_clk omap24xx_clks[] = {
        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X | CK_242X),
        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X | CK_242X),
        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
-       CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X | CK_242X),
-       CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X | CK_242X),
+       CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X | CK_242X),
+       CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X | CK_242X),
        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X | CK_242X),
        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X | CK_242X),
        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X | CK_242X),
@@ -205,10 +206,10 @@ static struct omap_clk omap24xx_clks[] = {
        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
-       CLK("mmci-omap-hs.0", "mmchs_ick",      &mmchs1_ick,    CK_243X),
-       CLK("mmci-omap-hs.0", "mmchs_fck",      &mmchs1_fck,    CK_243X),
-       CLK("mmci-omap-hs.1", "mmchs_ick",      &mmchs2_ick,    CK_243X),
-       CLK("mmci-omap-hs.1", "mmchs_fck",      &mmchs2_fck,    CK_243X),
+       CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
+       CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
+       CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
+       CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
@@ -339,7 +340,7 @@ static const struct clkops clkops_fixed = {
  * Uses the current prcm set to tell if a rate is valid.
  * You can go slower, but not faster within a given rate set.
  */
-long omap2_dpllcore_round_rate(unsigned long target_rate)
+static long omap2_dpllcore_round_rate(unsigned long target_rate)
 {
        u32 high, low, core_clk_src;
 
@@ -550,7 +551,9 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 
                /* Major subsystem dividers */
                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-               cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
+               cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+                                CM_CLKSEL1);
+
                if (cpu_is_omap2430())
                        cm_write_mod_reg(prcm->cm_clksel_mdm,
                                         OMAP2430_MDM_MOD, CM_CLKSEL);
@@ -571,6 +574,45 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
        return 0;
 }
 
+#ifdef CONFIG_CPU_FREQ
+/*
+ * Walk PRCM rate table and fillout cpufreq freq_table
+ */
+static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
+
+void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+       struct prcm_config *prcm;
+       int i = 0;
+
+       for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+               if (!(prcm->flags & cpu_mask))
+                       continue;
+               if (prcm->xtal_speed != sys_ck.rate)
+                       continue;
+
+               /* don't put bypass rates in table */
+               if (prcm->dpll_speed == prcm->xtal_speed)
+                       continue;
+
+               freq_table[i].index = i;
+               freq_table[i].frequency = prcm->mpu_speed / 1000;
+               i++;
+       }
+
+       if (i == 0) {
+               printk(KERN_WARNING "%s: failed to initialize frequency "
+                      "table\n", __func__);
+               return;
+       }
+
+       freq_table[i].index = i;
+       freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+       *table = &freq_table[0];
+}
+#endif
+
 static struct clk_functions omap2_clk_functions = {
        .clk_enable             = omap2_clk_enable,
        .clk_disable            = omap2_clk_disable,
@@ -578,24 +620,27 @@ static struct clk_functions omap2_clk_functions = {
        .clk_set_rate           = omap2_clk_set_rate,
        .clk_set_parent         = omap2_clk_set_parent,
        .clk_disable_unused     = omap2_clk_disable_unused,
+#ifdef CONFIG_CPU_FREQ
+       .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
+#endif
 };
 
 static u32 omap2_get_apll_clkin(void)
 {
-       u32 aplls, sclk = 0;
+       u32 aplls, srate = 0;
 
        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 
        if (aplls == APLLS_CLKIN_19_2MHZ)
-               sclk = 19200000;
+               srate = 19200000;
        else if (aplls == APLLS_CLKIN_13MHZ)
-               sclk = 13000000;
+               srate = 13000000;
        else if (aplls == APLLS_CLKIN_12MHZ)
-               sclk = 12000000;
+               srate = 12000000;
 
-       return sclk;
+       return srate;
 }
 
 static u32 omap2_get_sysclkdiv(void)