#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
-
+#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/cpufreq.h>
+#include <asm/arch/common.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
#include <asm/div64.h>
-#include <asm/bitops.h>
#include "memory.h"
#include "clock.h"
static int omap2_enable_osc_ck(struct clk *clk)
{
-
- prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, ~OMAP_AUTOEXTCLKMODE_MASK,
- OMAP24XX_PRCM_CLKSRC_CTRL);
+ prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0,
+ OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
return 0;
}
static void omap2_disable_osc_ck(struct clk *clk)
{
- prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
- OMAP24XX_PRCM_CLKSRC_CTRL);
+ prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
+ OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
}
/* Enable an APLL if off */
static int omap2_clk_fixed_enable(struct clk *clk)
{
u32 cval, apll_mask;
+ void __iomem *idlest;
apll_mask = EN_APLL_LOCKED << clk->enable_bit;
else if (clk == &apll54_ck)
cval = OMAP24XX_ST_54M_APLL;
- omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
- clk->name);
+ if (cpu_is_omap242x())
+ idlest = (__force void __iomem *)OMAP2420_CM_REGADDR(PLL_MOD,
+ CM_IDLEST);
+ else
+ idlest = (__force void __iomem *)OMAP2430_CM_REGADDR(PLL_MOD,
+ CM_IDLEST);
+
+ omap2_wait_clock_ready(idlest, cval, clk->name);
/*
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
* Uses the current prcm set to tell if a rate is valid.
* You can go slower, but not faster within a given rate set.
*/
-long omap2_dpllcore_round_rate(unsigned long target_rate)
+static long omap2_dpllcore_round_rate(unsigned long target_rate)
{
u32 high, low, core_clk_src;
/* Major subsystem dividers */
tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
- cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
+ cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+ CM_CLKSEL1);
+
if (cpu_is_omap2430())
cm_write_mod_reg(prcm->cm_clksel_mdm,
OMAP2430_MDM_MOD, CM_CLKSEL);
}
if (i == 0) {
- printk(KERN_WARNING "%s: failed to initialize frequency table\n",
- __FUNCTION__);
+ printk(KERN_WARNING "%s: failed to initialize frequency "
+ "table\n", __func__);
return;
}
static u32 omap2_get_apll_clkin(void)
{
- u32 aplls, sclk = 0;
+ u32 aplls, srate = 0;
aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
aplls &= OMAP24XX_APLLS_CLKIN_MASK;
aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
if (aplls == APLLS_CLKIN_19_2MHZ)
- sclk = 19200000;
+ srate = 19200000;
else if (aplls == APLLS_CLKIN_13MHZ)
- sclk = 13000000;
+ srate = 13000000;
else if (aplls == APLLS_CLKIN_12MHZ)
- sclk = 12000000;
+ srate = 12000000;
- return sclk;
+ return srate;
}
static u32 omap2_get_sysclkdiv(void)
{
u32 div;
- div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+ div = prm_read_mod_reg(OMAP24XX_GR_MOD,
+ OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
div &= OMAP_SYSCLKDIV_MASK;
div >>= OMAP_SYSCLKDIV_SHIFT;
}
arch_initcall(omap2_clk_arch_init);
+static u32 prm_base;
+static u32 cm_base;
+
+/*
+ * Since we share clock data for 242x and 243x, we need to rewrite some
+ * some register base offsets. Assume offset is at prm_base if flagged,
+ * else assume it's cm_base.
+ */
+static inline void omap2_clk_check_reg(u32 flags, void __iomem **reg)
+{
+ u32 tmp = (__force u32)*reg;
+
+ if ((tmp >> 24) != 0)
+ return;
+
+ if (flags & OFFSET_GR_MOD)
+ tmp += prm_base;
+ else
+ tmp += cm_base;
+
+ *reg = (__force void __iomem *)tmp;
+}
+
+static void __init omap2_clk_rewrite_base(struct clk *clk)
+{
+ omap2_clk_check_reg(clk->flags, &clk->clksel_reg);
+ omap2_clk_check_reg(clk->flags, &clk->enable_reg);
+ if (clk->dpll_data)
+ omap2_clk_check_reg(0, &clk->dpll_data->mult_div1_reg);
+}
+
int __init omap2_clk_init(void)
{
struct prcm_config *prcm;
else if (cpu_is_omap2430())
cpu_mask = RATE_IN_243X;
+ for (clkp = onchip_24xx_clks;
+ clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
+ clkp++) {
+ omap2_clk_rewrite_base(*clkp);
+ }
+
clk_init(&omap2_clk_functions);
omap2_osc_clk_recalc(&osc_ck);
return 0;
}
+
+void __init omap2_set_globals_clock24xx(struct omap_globals *omap2_globals)
+{
+ prm_base = (__force u32)omap2_globals->prm;
+ cm_base = (__force u32)omap2_globals->cm;
+}