OMAP clock: add OMAP chip family-specific clk_register() option

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock.c

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 31b5c9dc06631f6969e710ef490ed5d4e3c72458..5f54e7eabe270a2ecf7bddd4178cb088dbdf29c1 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -120,6 +120,28 @@ static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
                cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
 }
 
+/**
+ * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
+ * @clk: struct clk *
+ *
+ * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
+ * don't take effect until the VALID_CONFIG bit is written, write the
+ * VALID_CONFIG bit and wait for the write to complete.  No return value.
+ */
+static void _omap2xxx_clk_commit(struct clk *clk)
+{
+       if (!cpu_is_omap24xx())
+               return;
+
+       if (!(clk->flags & DELAYED_APP))
+               return;
+
+       prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
+                         OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+       /* OCP barrier */
+       prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+}
+
 /*
  * _dpll_test_fint - test whether an Fint value is valid for the DPLL
  * @clk: DPLL struct clk to test
@@ -424,7 +446,7 @@ static int _omap2_clk_enable(struct clk *clk)
        else
                v |= (1 << clk->enable_bit);
        _omap2_clk_write_reg(v, clk->enable_reg, clk);
-       wmb();
+       v = _omap2_clk_read_reg(clk->enable_reg, clk); /* OCP barrier */
 
        omap2_clk_wait_ready(clk);
 
@@ -450,7 +472,7 @@ static void _omap2_clk_disable(struct clk *clk)
        else
                v &= ~(1 << clk->enable_bit);
        _omap2_clk_write_reg(v, clk->enable_reg, clk);
-       wmb();
+       /* No OCP barrier needed here since it is a disable operation */
 }
 
 void omap2_clk_disable(struct clk *clk)
@@ -563,8 +585,6 @@ static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
  *
  * Finds 'best' divider value in an array based on the source and target
  * rates.  The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
  *
  * Returns the rounded clock rate or returns 0xffffffff on error.
  */
@@ -625,8 +645,6 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
  * Compatibility wrapper for OMAP clock framework
  * Finds best target rate based on the source clock and possible dividers.
  * rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
  *
  * Returns the rounded clock rate or returns 0xffffffff on error.
  */
@@ -756,16 +774,11 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
        v &= ~clk->clksel_mask;
        v |= field_val << __ffs(clk->clksel_mask);
        _omap2_clk_write_reg(v, clk->clksel_reg, clk);
-
-       wmb();
+       v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
 
        clk->rate = clk->parent->rate / new_div;
 
-       if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
-               prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
-                       OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
-               wmb();
-       }
+       _omap2xxx_clk_commit(clk);
 
        return 0;
 }
@@ -778,12 +791,6 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 
        pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
 
-       /* CONFIG_PARTICIPANT clocks are changed only in sets via the
-          rate table mechanism, driven by mpu_speed  */
-       if (clk->flags & CONFIG_PARTICIPANT)
-               return -EINVAL;
-
-       /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
        if (clk->set_rate != NULL)
                ret = clk->set_rate(clk, rate);
 
@@ -828,9 +835,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
        u32 field_val, v, parent_div;
 
-       if (clk->flags & CONFIG_PARTICIPANT)
-               return -EINVAL;
-
        if (!clk->clksel)
                return -EINVAL;
 
@@ -846,13 +850,9 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
        v &= ~clk->clksel_mask;
        v |= field_val << __ffs(clk->clksel_mask);
        _omap2_clk_write_reg(v, clk->clksel_reg, clk);
-       wmb();
+       v = _omap2_clk_read_reg(clk->clksel_reg, clk);    /* OCP barrier */
 
-       if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
-               prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
-                       OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
-               wmb();
-       }
+       _omap2xxx_clk_commit(clk);
 
        if (clk->usecount > 0)
                _omap2_clk_enable(clk);
@@ -1085,3 +1085,9 @@ void omap2_clk_disable_unused(struct clk *clk)
        _omap2_clk_disable(clk);
 }
 #endif
+
+int omap2_clk_register(struct clk *clk)
+{
+       omap2_init_clk_clkdm(clk);
+       return 0;
+}