cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
}
+/**
+ * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
+ * @clk: struct clk *
+ *
+ * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
+ * don't take effect until the VALID_CONFIG bit is written, write the
+ * VALID_CONFIG bit and wait for the write to complete. No return value.
+ */
+static void _omap2xxx_clk_commit(struct clk *clk)
+{
+ if (!cpu_is_omap24xx())
+ return;
+
+ if (!(clk->flags & DELAYED_APP))
+ return;
+
+ prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
+ OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+ /* OCP barrier */
+ prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+}
+
/*
* _dpll_test_fint - test whether an Fint value is valid for the DPLL
* @clk: DPLL struct clk to test
{
struct clockdomain *clkdm;
- if (!clk->clkdm.name) {
- pr_err("clock: %s: missing clockdomain", clk->name);
- return;
- }
-
clkdm = clkdm_lookup(clk->clkdm.name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
clk->name, clks->parent->name,
((clk->parent) ?
clk->parent->name : "NULL"));
+ if (clk->parent)
+ omap_clk_del_child(clk->parent,
+ clk);
clk->parent = clks->parent;
+ omap_clk_add_child(clk->parent, clk);
};
found = 1;
}
else
v |= (1 << clk->enable_bit);
_omap2_clk_write_reg(v, clk->enable_reg, clk);
- wmb();
+ v = _omap2_clk_read_reg(clk->enable_reg, clk); /* OCP barrier */
omap2_clk_wait_ready(clk);
else
v &= ~(1 << clk->enable_bit);
_omap2_clk_write_reg(v, clk->enable_reg, clk);
- wmb();
+ /* No OCP barrier needed here since it is a disable operation */
}
void omap2_clk_disable(struct clk *clk)
_omap2_clk_disable(clk);
if (clk->parent)
omap2_clk_disable(clk->parent);
- if (clk->clkdm.ptr)
- omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
+ omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
}
}
int omap2_clk_enable(struct clk *clk)
{
- int ret = 0;
-
- if (clk->usecount++ == 0) {
- if (clk->parent)
- ret = omap2_clk_enable(clk->parent);
+ int ret;
- if (ret != 0) {
- clk->usecount--;
- return ret;
- }
+ if (++clk->usecount > 1)
+ return 0;
- if (clk->clkdm.ptr)
- omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
+ omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
- ret = _omap2_clk_enable(clk);
+ if (clk->parent) {
+ int parent_ret;
- if (ret != 0) {
- if (clk->clkdm.ptr)
- omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
+ parent_ret = omap2_clk_enable(clk->parent);
- if (clk->parent) {
- omap2_clk_disable(clk->parent);
- clk->usecount--;
- }
+ if (parent_ret != 0) {
+ clk->usecount--;
+ omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
+ return parent_ret;
}
}
+ ret = _omap2_clk_enable(clk);
+
+ if (ret != 0) {
+ clk->usecount--;
+ omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
+ if (clk->parent)
+ omap2_clk_disable(clk->parent);
+ }
+
return ret;
}
*
* Finds 'best' divider value in an array based on the source and target
* rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
*
* Returns the rounded clock rate or returns 0xffffffff on error.
*/
* Compatibility wrapper for OMAP clock framework
* Finds best target rate based on the source clock and possible dividers.
* rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
*
* Returns the rounded clock rate or returns 0xffffffff on error.
*/
if (clk->round_rate != NULL)
return clk->round_rate(clk, rate);
- if (clk->flags & RATE_FIXED)
- printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
- "on fixed-rate clock %s\n", clk->name);
-
return clk->rate;
}
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
_omap2_clk_write_reg(v, clk->clksel_reg, clk);
-
- wmb();
+ v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
clk->rate = clk->parent->rate / new_div;
- if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
- prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
- OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
- wmb();
- }
+ _omap2xxx_clk_commit(clk);
return 0;
}
pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
- /* CONFIG_PARTICIPANT clocks are changed only in sets via the
- rate table mechanism, driven by mpu_speed */
- if (clk->flags & CONFIG_PARTICIPANT)
- return -EINVAL;
-
- /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
if (clk->set_rate != NULL)
ret = clk->set_rate(clk, rate);
{
u32 field_val, v, parent_div;
- if (clk->flags & CONFIG_PARTICIPANT)
- return -EINVAL;
-
if (!clk->clksel)
return -EINVAL;
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
_omap2_clk_write_reg(v, clk->clksel_reg, clk);
- wmb();
+ v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
- if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
- prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
- OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
- wmb();
- }
+ _omap2xxx_clk_commit(clk);
if (clk->usecount > 0)
_omap2_clk_enable(clk);
return;
printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
- _omap2_clk_disable(clk);
+ if (cpu_is_omap34xx()) {
+ omap2_clk_enable(clk);
+ omap2_clk_disable(clk);
+ } else
+ _omap2_clk_disable(clk);
}
#endif
+
+int omap2_clk_register(struct clk *clk)
+{
+ if (!clk->clkdm.name) {
+ pr_debug("clock: %s: missing clockdomain", clk->name);
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ omap2_init_clk_clkdm(clk);
+ return 0;
+}
projects / linux-2.6-omap-h63xx.git / blobdiff