cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
}
+/**
+ * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
+ * @clk: struct clk *
+ *
+ * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
+ * don't take effect until the VALID_CONFIG bit is written, write the
+ * VALID_CONFIG bit and wait for the write to complete. No return value.
+ */
+static void _omap2xxx_clk_commit(struct clk *clk)
+{
+ if (!cpu_is_omap24xx())
+ return;
+
+ if (!(clk->flags & DELAYED_APP))
+ return;
+
+ prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
+ OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+ /* OCP barrier */
+ prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+}
+
/*
* _dpll_test_fint - test whether an Fint value is valid for the DPLL
* @clk: DPLL struct clk to test
{
struct clockdomain *clkdm;
- if (!clk->clkdm.name) {
- pr_err("clock: %s: missing clockdomain", clk->name);
- return;
- }
-
clkdm = clkdm_lookup(clk->clkdm.name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
else
v |= (1 << clk->enable_bit);
_omap2_clk_write_reg(v, clk->enable_reg, clk);
- wmb();
+ v = _omap2_clk_read_reg(clk->enable_reg, clk); /* OCP barrier */
omap2_clk_wait_ready(clk);
_omap2_clk_disable(clk);
if (clk->parent)
omap2_clk_disable(clk->parent);
- if (clk->clkdm.ptr)
- omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
+ omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
}
}
return ret;
}
- if (clk->clkdm.ptr)
- omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
+ omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
ret = _omap2_clk_enable(clk);
if (ret != 0) {
- if (clk->clkdm.ptr)
- omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
+ omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
if (clk->parent) {
omap2_clk_disable(clk->parent);
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
_omap2_clk_write_reg(v, clk->clksel_reg, clk);
-
- wmb();
+ v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
clk->rate = clk->parent->rate / new_div;
- if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
- prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
- OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
- wmb();
- }
+ _omap2xxx_clk_commit(clk);
return 0;
}
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
_omap2_clk_write_reg(v, clk->clksel_reg, clk);
- wmb();
+ v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
- if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
- prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
- OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
- wmb();
- }
+ _omap2xxx_clk_commit(clk);
if (clk->usecount > 0)
_omap2_clk_enable(clk);
_omap2_clk_disable(clk);
}
#endif
+
+int omap2_clk_register(struct clk *clk)
+{
+ if (!clk->clkdm.name) {
+ pr_debug("clock: %s: missing clockdomain", clk->name);
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ omap2_init_clk_clkdm(clk);
+ return 0;
+}