[PATCH] ARM: OMAP: Use gpmc_cs_get_base_addr for H4 smc91x

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / board-h4.c

diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 05eba929332078dae7db62b506918aa70be0de39..20a5733e96279e32a8fe4b95ed8f35cef63268c7 100644 (file)
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -19,6 +19,8 @@
 #include <linux/delay.h>
 #include <linux/workqueue.h>
 #include <linux/input.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
@@ -270,16 +272,78 @@ static struct platform_device *h4_devices[] __initdata = {
        &h4_lcd_device,
 };
 
+/* 2420 Sysboot setup (2430 is different) */
+static u32 get_sysboot_value(void)
+{
+       return (omap_readl(OMAP242X_CONTROL_STATUS) & 0xFFF);
+}
+
+/* FIXME: This function should be moved to some other file, gpmc.c? */
+
+/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
+ *
+ * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
+ *  correctly.  The macro needs to look at production_id not just hawkeye.
+ */
+static u32 is_gpmc_muxed(void)
+{
+       u32 mux;
+       mux = get_sysboot_value();
+       if ((mux & 0xF) == 0xd)
+               return 1;       /* NAND config (could be either) */
+       if (mux & 0x2)          /* if mux'ed */
+               return 1;
+       else
+               return 0;
+}
+
+#define SMC91X_CS      1
+
 static inline void __init h4_init_smc91x(void)
 {
+       int eth_cs;
+       unsigned int muxed, rate;
+       struct clk *l3ck;
+
+       eth_cs  = SMC91X_CS;
+
+       l3ck = clk_get(NULL, "core_l3_ck");
+       if (IS_ERR(l3ck))
+               rate = 100000000;
+       else
+               rate = clk_get_rate(l3ck);
+
+       if (is_gpmc_muxed())
+               muxed = 0x200;
+       else
+               muxed = 0;
+
        /* Make sure CS1 timings are correct */
-       GPMC_CONFIG1_1 = 0x00011200;
-       GPMC_CONFIG2_1 = 0x001f1f01;
-       GPMC_CONFIG3_1 = 0x00080803;
-       GPMC_CONFIG4_1 = 0x1c091c09;
-       GPMC_CONFIG5_1 = 0x041f1f1f;
-       GPMC_CONFIG6_1 = 0x000004c4;
-       GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24);
+       gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
+                         0x00011000 | muxed);
+
+       if (rate >= 160000000) {
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+       } else if (rate >= 130000000) {
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+       } else {/* rate = 100000000 */
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
+               gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
+       }
+
+       gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG7,
+                         0x00000f40 | (0x08000000 >> 24));
        udelay(100);
 
        omap_cfg_reg(M15_24XX_GPIO92);