ARM: OMAP: Partial revert for EAC IO address changes

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / board-3430sdp-flash.c

diff --git a/arch/arm/mach-omap2/board-3430sdp-flash.c b/arch/arm/mach-omap2/board-3430sdp-flash.c
index 1fddcd67b57750feab6e889efb93c811a2e59cc4..f0e25a464172b3b7c6faf049e313aab704cbce94 100644 (file)
--- a/arch/arm/mach-omap2/board-3430sdp-flash.c
+++ b/arch/arm/mach-omap2/board-3430sdp-flash.c
@@ -21,9 +21,33 @@
 #include <linux/io.h>
 
 #include <asm/mach/flash.h>
-#include <asm/arch/onenand.h>
-#include <asm/arch/board.h>
-#include <asm/arch/gpmc.h>
+#include <mach/onenand.h>
+#include <mach/board.h>
+#include <mach/gpmc.h>
+#include <mach/nand.h>
+
+#define NAND_BLOCK_SIZE                SZ_128K
+
+/* NAND */
+/* IMPORTANT NOTE ON MAPPING
+ * 3430SDP - 34XX
+ * ----------
+ * NOR always on 0x04000000 for SDPV1
+ * NOR always on 0x10000000 for SDPV2
+ * MPDB always on 0x08000000
+ * NAND always on 0x0C000000
+ * OneNand Mapped to 0x20000000
+ * Boot Mode(NAND/NOR). The other on CS1
+ */
+#define FLASH_BASE_SDPV1       0x04000000 /* NOR flash (64 Meg aligned) */
+#define FLASH_BASE_SDPV2       0x10000000 /* NOR flash (256 Meg aligned) */
+#define DEBUG_BASE             0x08000000 /* debug board */
+#define NAND_BASE              0x0C000000 /* NAND flash */
+#define ONENAND_MAP            0x20000000 /* OneNand flash */
+
+/* various memory sizes */
+#define FLASH_SIZE_SDPV1       SZ_64M
+#define FLASH_SIZE_SDPV2       SZ_128M
 
 static struct mtd_partition sdp_nor_partitions[] = {
        /* bootloader (U-Boot, etc) in first sector */
@@ -137,6 +161,61 @@ static int sdp_onenand_setup(void __iomem *onenand_base, int freq)
        /* Onenand setup does nothing at present */
        return 0;
 }
+
+static struct mtd_partition sdp_nand_partitions[] = {
+       /* All the partition sizes are listed in terms of NAND block size */
+       {
+               .name           = "X-Loader-NAND",
+               .offset         = 0,
+               .size           = 4 * NAND_BLOCK_SIZE,
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "U-Boot-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+               .size           = 4 * NAND_BLOCK_SIZE,
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "Boot Env-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x100000 */
+               .size           = 2 * NAND_BLOCK_SIZE,
+       },
+       {
+               .name           = "Kernel-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x140000 */
+               .size           = 32 * NAND_BLOCK_SIZE,
+       },
+       {
+               .name           = "File System - NAND",
+               .size           = MTDPART_SIZ_FULL,
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x540000 */
+       },
+};
+
+static struct omap_nand_platform_data sdp_nand_data = {
+       .parts          = sdp_nand_partitions,
+       .nr_parts       = ARRAY_SIZE(sdp_nand_partitions),
+       .nand_setup     = NULL,
+       .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
+       .dev_ready      = NULL,
+};
+
+static struct resource sdp_nand_resource = {
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device sdp_nand_device = {
+       .name           = "omap2-nand",
+       .id             = 0,
+       .dev            = {
+       .platform_data  = &sdp_nand_data,
+       },
+       .num_resources  = 1,
+       .resource       = &sdp_nand_resource,
+};
+
+
 /**
  * sdp3430_flash_init - Identify devices connected to GPMC and register.
  *
@@ -145,10 +224,14 @@ static int sdp_onenand_setup(void __iomem *onenand_base, int freq)
 void __init sdp3430_flash_init(void)
 {
        u8              cs = 0;
+       u8              nandcs = GPMC_CS_NUM + 1;
        u8              onenandcs = GPMC_CS_NUM + 1;
+       unsigned long   gpmc_base_add;
+
+       gpmc_base_add   = OMAP34XX_GPMC_VIRT;
 
        /* Configure start address and size of NOR device */
-       if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+       if (omap_rev() > OMAP3430_REV_ES1_0) {
                sdp_nor_resource.start  = FLASH_BASE_SDPV2;
                sdp_nor_resource.end    = FLASH_BASE_SDPV2
                                                + FLASH_SIZE_SDPV2 - 1;
@@ -163,25 +246,42 @@ void __init sdp3430_flash_init(void)
 
        while (cs < GPMC_CS_NUM) {
                u32 ret = 0;
-               ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+               ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 
                /*
-               * xloader/Uboot would have programmed the oneNAND
+               * xloader/Uboot would have programmed the NAND/oneNAND
                * base address for us This is a ugly hack. The proper
                * way of doing this is to pass the setup of u-boot up
                * to kernel using kernel params - something on the
                * lines of machineID. Check if oneNAND is configured
                */
-               if ((ret & 0x3F) == (ONENAND_MAP >> 24))
+               if ((ret & 0xC00) == 0x800) {
+                       /* Found it!! */
+                       if (nandcs > GPMC_CS_NUM)
+                               nandcs = cs;
+               } else {
+                       ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+                       if ((ret & 0x3F) == (ONENAND_MAP >> 24))
                        onenandcs = cs;
+               }
                cs++;
        }
-       if (onenandcs > GPMC_CS_NUM) {
-               printk(KERN_INFO "OneNAND: Unable to find configuration "
+       if ((nandcs > GPMC_CS_NUM) && (onenandcs > GPMC_CS_NUM)) {
+               printk(KERN_INFO "NAND/OneNAND: Unable to find configuration "
                                " in GPMC\n ");
                return;
        }
 
+       if (nandcs < GPMC_CS_NUM) {
+               sdp_nand_data.cs        = nandcs;
+               sdp_nand_data.gpmc_cs_baseaddr   = (void *)(gpmc_base_add +
+                                       GPMC_CS0_BASE + nandcs*GPMC_CS_SIZE);
+               sdp_nand_data.gpmc_baseaddr     = (void *) (gpmc_base_add);
+
+               if (platform_device_register(&sdp_nand_device) < 0)
+                       printk(KERN_ERR "Unable to register NAND device\n");
+       }
+
        if (onenandcs < GPMC_CS_NUM) {
                sdp_onenand_data.cs = onenandcs;
                if (platform_device_register(&sdp_onenand_device) < 0)