[ARM] 3430/1: ARM: OMAP: 5/8 Update PM

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap1 / sleep.S

diff --git a/arch/arm/plat-omap/sleep.S b/arch/arm/mach-omap1/sleep.S
similarity index 93%
rename from arch/arm/plat-omap/sleep.S
rename to arch/arm/mach-omap1/sleep.S
index 4cd7d292f854be9c5b743829081ac0dcdbce2279..e58295e2d3b244e7410d7dbec5d666afa66d400e 100644 (file)
--- a/arch/arm/plat-omap/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/plat-omap/sleep.S
+ * linux/arch/arm/mach-omap1/sleep.S
  *
  * Low-level OMAP730/1510/1610 sleep/wakeUp support
  *
@@ -383,60 +383,133 @@ ENTRY(omap1610_cpu_suspend)
        mcr     p15, 0, r0, c7, c10, 4
        nop
 
-       @ load base address of Traffic Controller
+       @ Load base address of Traffic Controller
        mov     r6, #TCMIF_ASM_BASE & 0xff000000
        orr     r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
        orr     r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
 
-       @ prepare to put SDRAM into self-refresh manually
+       @ Prepare to put SDRAM into self-refresh manually
        ldr     r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
        orr     r9, r7, #SELF_REFRESH_MODE & 0xff000000
        orr     r9, r9, #SELF_REFRESH_MODE & 0x000000ff
        str     r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
 
-       @ prepare to put EMIFS to Sleep
+       @ Prepare to put EMIFS to Sleep
        ldr     r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
        orr     r9, r8, #IDLE_EMIFS_REQUEST & 0xff
        str     r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
 
-       @ load base address of ARM_IDLECT1 and ARM_IDLECT2
+       @ Load base address of ARM_IDLECT1 and ARM_IDLECT2
        mov     r4, #CLKGEN_REG_ASM_BASE & 0xff000000
        orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
        orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
 
-       @ turn off clock domains
-       @ do not disable PERCK (0x04)
+       @ Turn off clock domains
+       @ Do not disable PERCK (0x04)
        mov     r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
        orr     r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
        strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
 
-       @ request ARM idle
+       @ Request ARM idle
        mov     r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff
        orr     r3, r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff00
        strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
 
-       @ disable instruction cache
-       mrc     p15, 0, r9, c1, c0, 0
-       bic     r2, r9, #0x1000
-       mcr     p15, 0, r2, c1, c0, 0
-       nop
-
 /*
  * Let's wait for the next wake up event to wake us up. r0 can't be
  * used here because r0 holds ARM_IDLECT1
  */
        mov     r2, #0
        mcr     p15, 0, r2, c7, c0, 4           @ wait for interrupt
+
+       @ Errata (HEL3SU467, section 1.4.4) specifies nop-instructions
+       @ according to this formula:
+       @ 2 + (4*DPLL_MULT)/DPLL_DIV/ARMDIV
+       @ Max DPLL_MULT = 18
+       @ DPLL_DIV = 1
+       @ ARMDIV = 1
+       @ => 74 nop-instructions
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop     @10
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop     @20
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop     @30
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop     @40
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop     @50
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop     @60
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop     @70
+       nop
+       nop
+       nop
+       nop     @74
 /*
  * omap1610_cpu_suspend()'s resume point.
  *
  * It will just start executing here, so we'll restore stuff from the
  * stack.
  */
-       @ re-enable Icache
-       mcr     p15, 0, r9, c1, c0, 0
-
-       @ reset the ARM_IDLECT1 and ARM_IDLECT2.
+       @ Restore the ARM_IDLECT1 and ARM_IDLECT2.
        strh    r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
        strh    r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
 
@@ -444,7 +517,7 @@ ENTRY(omap1610_cpu_suspend)
        str     r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
        str     r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
 
-       @ restore regs and return
+       @ Restore regs and return
        ldmfd   sp!, {r0 - r12, pc}
 
 ENTRY(omap1610_cpu_suspend_sz)