#define MMU_LOCK_BASE_MASK (0x3f << 10)
#define MMU_LOCK_VICTIM_MASK (0x3f << 4)
-#define OMAP_MMU_BASE (0xfffed200)
-#define OMAP_MMU_PREFETCH (OMAP_MMU_BASE + 0x00)
-#define OMAP_MMU_WALKING_ST (OMAP_MMU_BASE + 0x04)
-#define OMAP_MMU_CNTL (OMAP_MMU_BASE + 0x08)
-#define OMAP_MMU_FAULT_AD_H (OMAP_MMU_BASE + 0x0c)
-#define OMAP_MMU_FAULT_AD_L (OMAP_MMU_BASE + 0x10)
-#define OMAP_MMU_FAULT_ST (OMAP_MMU_BASE + 0x14)
-#define OMAP_MMU_IT_ACK (OMAP_MMU_BASE + 0x18)
-#define OMAP_MMU_TTB_H (OMAP_MMU_BASE + 0x1c)
-#define OMAP_MMU_TTB_L (OMAP_MMU_BASE + 0x20)
-#define OMAP_MMU_LOCK (OMAP_MMU_BASE + 0x24)
-#define OMAP_MMU_LD_TLB (OMAP_MMU_BASE + 0x28)
-#define OMAP_MMU_CAM_H (OMAP_MMU_BASE + 0x2c)
-#define OMAP_MMU_CAM_L (OMAP_MMU_BASE + 0x30)
-#define OMAP_MMU_RAM_H (OMAP_MMU_BASE + 0x34)
-#define OMAP_MMU_RAM_L (OMAP_MMU_BASE + 0x38)
-#define OMAP_MMU_GFLUSH (OMAP_MMU_BASE + 0x3c)
-#define OMAP_MMU_FLUSH_ENTRY (OMAP_MMU_BASE + 0x40)
-#define OMAP_MMU_READ_CAM_H (OMAP_MMU_BASE + 0x44)
-#define OMAP_MMU_READ_CAM_L (OMAP_MMU_BASE + 0x48)
-#define OMAP_MMU_READ_RAM_H (OMAP_MMU_BASE + 0x4c)
-#define OMAP_MMU_READ_RAM_L (OMAP_MMU_BASE + 0x50)
+#define OMAP_MMU_PREFETCH 0x00
+#define OMAP_MMU_WALKING_ST 0x04
+#define OMAP_MMU_CNTL 0x08
+#define OMAP_MMU_FAULT_AD_H 0x0c
+#define OMAP_MMU_FAULT_AD_L 0x10
+#define OMAP_MMU_FAULT_ST 0x14
+#define OMAP_MMU_IT_ACK 0x18
+#define OMAP_MMU_TTB_H 0x1c
+#define OMAP_MMU_TTB_L 0x20
+#define OMAP_MMU_LOCK 0x24
+#define OMAP_MMU_LD_TLB 0x28
+#define OMAP_MMU_CAM_H 0x2c
+#define OMAP_MMU_CAM_L 0x30
+#define OMAP_MMU_RAM_H 0x34
+#define OMAP_MMU_RAM_L 0x38
+#define OMAP_MMU_GFLUSH 0x3c
+#define OMAP_MMU_FLUSH_ENTRY 0x40
+#define OMAP_MMU_READ_CAM_H 0x44
+#define OMAP_MMU_READ_CAM_L 0x48
+#define OMAP_MMU_READ_RAM_H 0x4c
+#define OMAP_MMU_READ_RAM_L 0x50
#define OMAP_MMU_CNTL_BURST_16MNGT_EN 0x0020
#define OMAP_MMU_CNTL_WTL_EN 0x0004