ARM: Add support for FA526 v2

[linux-2.6-omap-h63xx.git] / arch / arm / boot / compressed / head.S

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 77d614232d815fd592e6798383e7eb4aa8be48ae..def02483286ad00d40a11e74712192f8e2d174ad 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -459,6 +459,20 @@ __armv7_mmu_cache_on:
                mcr     p15, 0, r0, c7, c5, 4   @ ISB
                mov     pc, r12
 
+__fa526_cache_on:
+               mov     r12, lr
+               bl      __setup_mmu
+               mov     r0, #0
+               mcr     p15, 0, r0, c7, c7, 0   @ Invalidate whole cache
+               mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
+               mcr     p15, 0, r0, c8, c7, 0   @ flush UTLB
+               mrc     p15, 0, r0, c1, c0, 0   @ read control reg
+               orr     r0, r0, #0x1000         @ I-cache enable
+               bl      __common_mmu_cache_on
+               mov     r0, #0
+               mcr     p15, 0, r0, c8, c7, 0   @ flush UTLB
+               mov     pc, r12
+
 __arm6_mmu_cache_on:
                mov     r12, lr
                bl      __setup_mmu
@@ -636,6 +650,12 @@ proc_types:
                b       __armv4_mmu_cache_off
                b       __armv5tej_mmu_cache_flush
 
+               .word   0x66015261              @ FA526
+               .word   0xff01fff1
+               b       __fa526_cache_on
+               b       __armv4_mmu_cache_off
+               b       __fa526_cache_flush
+
                @ These match on the architecture ID
 
                .word   0x00020000              @ ARMv4T
@@ -775,6 +795,12 @@ __armv4_mpu_cache_flush:
                mcr     p15, 0, ip, c7, c10, 4  @ drain WB
                mov     pc, lr
                
+__fa526_cache_flush:
+               mov     r1, #0
+               mcr     p15, 0, r1, c7, c14, 0  @ clean and invalidate D cache
+               mcr     p15, 0, r1, c7, c5, 0   @ flush I cache
+               mcr     p15, 0, r1, c7, c10, 4  @ drain WB
+               mov     pc, lr
 
 __armv6_mmu_cache_flush:
                mov     r1, #0