2 * pxa2xx-i2s.c -- ALSA Soc Audio Layer
4 * Copyright 2005 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/platform_device.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/initval.h>
23 #include <sound/soc.h>
24 #include <sound/pxa2xx-lib.h>
26 #include <mach/hardware.h>
27 #include <mach/pxa-regs.h>
28 #include <mach/pxa2xx-gpio.h>
29 #include <mach/audio.h>
31 #include "pxa2xx-pcm.h"
32 #include "pxa2xx-i2s.h"
43 * I2S Controller Register and Bit Definitions
45 #define SACR0 __REG(0x40400000) /* Global Control Register */
46 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
47 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
48 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
49 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
50 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
51 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
53 #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
54 #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
55 #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
56 #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
57 #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
58 #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
59 #define SACR0_ENB (1 << 0) /* Enable I2S Link */
60 #define SACR1_ENLBF (1 << 5) /* Enable Loopback */
61 #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
62 #define SACR1_DREC (1 << 3) /* Disable Recording Function */
63 #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
65 #define SASR0_I2SOFF (1 << 7) /* Controller Status */
66 #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
67 #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
68 #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
69 #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
70 #define SASR0_BSY (1 << 2) /* I2S Busy */
71 #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
72 #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
74 #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
75 #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
77 #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
78 #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
79 #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
80 #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
90 static struct pxa_i2s_port pxa_i2s;
91 static struct clk *clk_i2s;
93 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
94 .name = "I2S PCM Stereo out",
95 .dev_addr = __PREG(SADR),
97 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
98 DCMD_BURST32 | DCMD_WIDTH4,
101 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
102 .name = "I2S PCM Stereo in",
103 .dev_addr = __PREG(SADR),
105 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
106 DCMD_BURST32 | DCMD_WIDTH4,
109 static struct pxa2xx_gpio gpio_bus[] = {
110 { /* I2S SoC Slave */
111 .rx = GPIO29_SDATA_IN_I2S_MD,
112 .tx = GPIO30_SDATA_OUT_I2S_MD,
113 .clk = GPIO28_BITCLK_IN_I2S_MD,
114 .frm = GPIO31_SYNC_I2S_MD,
116 { /* I2S SoC Master */
117 .rx = GPIO29_SDATA_IN_I2S_MD,
118 .tx = GPIO30_SDATA_OUT_I2S_MD,
119 .clk = GPIO28_BITCLK_OUT_I2S_MD,
120 .frm = GPIO31_SYNC_I2S_MD,
124 static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
125 struct snd_soc_dai *dai)
127 struct snd_soc_pcm_runtime *rtd = substream->private_data;
128 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
131 return PTR_ERR(clk_i2s);
133 if (!cpu_dai->active) {
141 /* wait for I2S controller to be ready */
142 static int pxa_i2s_wait(void)
146 /* flush the Rx FIFO */
147 for(i = 0; i < 16; i++)
152 static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
155 /* interface format */
156 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
157 case SND_SOC_DAIFMT_I2S:
160 case SND_SOC_DAIFMT_LEFT_J:
161 pxa_i2s.fmt = SACR1_AMSL;
165 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
166 case SND_SOC_DAIFMT_CBS_CFS:
169 case SND_SOC_DAIFMT_CBM_CFS:
178 static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
179 int clk_id, unsigned int freq, int dir)
181 if (clk_id != PXA2XX_I2S_SYSCLK)
184 if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
185 pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
190 static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
191 struct snd_pcm_hw_params *params,
192 struct snd_soc_dai *dai)
194 struct snd_soc_pcm_runtime *rtd = substream->private_data;
195 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
197 pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
198 pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
199 pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
200 pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
201 BUG_ON(IS_ERR(clk_i2s));
205 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
206 cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
208 cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
210 /* is port used by another stream */
211 if (!(SACR0 & SACR0_ENB)) {
218 SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
219 SACR1 |= pxa_i2s.fmt;
221 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
226 switch (params_rate(params)) {
245 case 96000: /* not in manual and possibly slightly inaccurate */
253 static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
254 struct snd_soc_dai *dai)
259 case SNDRV_PCM_TRIGGER_START:
262 case SNDRV_PCM_TRIGGER_RESUME:
263 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
264 case SNDRV_PCM_TRIGGER_STOP:
265 case SNDRV_PCM_TRIGGER_SUSPEND:
266 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
275 static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
276 struct snd_soc_dai *dai)
278 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
286 if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
289 clk_disable(clk_i2s);
296 static int pxa2xx_i2s_suspend(struct snd_soc_dai *dai)
301 /* store registers */
302 pxa_i2s.sacr0 = SACR0;
303 pxa_i2s.sacr1 = SACR1;
304 pxa_i2s.saimr = SAIMR;
305 pxa_i2s.sadiv = SADIV;
307 /* deactivate link */
313 static int pxa2xx_i2s_resume(struct snd_soc_dai *dai)
320 SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
321 SACR1 = pxa_i2s.sacr1;
322 SAIMR = pxa_i2s.saimr;
323 SADIV = pxa_i2s.sadiv;
330 #define pxa2xx_i2s_suspend NULL
331 #define pxa2xx_i2s_resume NULL
334 #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
335 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
336 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
338 struct snd_soc_dai pxa_i2s_dai = {
339 .name = "pxa2xx-i2s",
341 .suspend = pxa2xx_i2s_suspend,
342 .resume = pxa2xx_i2s_resume,
346 .rates = PXA2XX_I2S_RATES,
347 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
351 .rates = PXA2XX_I2S_RATES,
352 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
354 .startup = pxa2xx_i2s_startup,
355 .shutdown = pxa2xx_i2s_shutdown,
356 .trigger = pxa2xx_i2s_trigger,
357 .hw_params = pxa2xx_i2s_hw_params,
358 .set_fmt = pxa2xx_i2s_set_dai_fmt,
359 .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
363 EXPORT_SYMBOL_GPL(pxa_i2s_dai);
365 static int pxa2xx_i2s_probe(struct platform_device *dev)
369 clk_i2s = clk_get(&dev->dev, "I2SCLK");
371 return PTR_ERR(clk_i2s);
373 pxa_i2s_dai.dev = &dev->dev;
374 ret = snd_soc_register_dai(&pxa_i2s_dai);
381 static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
383 snd_soc_unregister_dai(&pxa_i2s_dai);
385 clk_i2s = ERR_PTR(-ENOENT);
389 static struct platform_driver pxa2xx_i2s_driver = {
390 .probe = pxa2xx_i2s_probe,
391 .remove = __devexit_p(pxa2xx_i2s_remove),
394 .name = "pxa2xx-i2s",
395 .owner = THIS_MODULE,
399 static int __init pxa2xx_i2s_init(void)
402 gpio_bus[1].sys = GPIO113_I2S_SYSCLK_MD;
404 gpio_bus[1].sys = GPIO32_SYSCLK_I2S_MD;
406 clk_i2s = ERR_PTR(-ENOENT);
407 return platform_driver_register(&pxa2xx_i2s_driver);
410 static void __exit pxa2xx_i2s_exit(void)
412 platform_driver_unregister(&pxa2xx_i2s_driver);
415 module_init(pxa2xx_i2s_init);
416 module_exit(pxa2xx_i2s_exit);
418 /* Module information */
419 MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
420 MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
421 MODULE_LICENSE("GPL");