2 * ALSA driver for Intel ICH (i8x0) chipsets
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <sound/driver.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/moduleparam.h>
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/ac97_codec.h>
40 #include <sound/info.h>
41 #include <sound/initval.h>
42 /* for 440MX workaround */
43 #include <asm/pgtable.h>
44 #include <asm/cacheflush.h>
46 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48 MODULE_LICENSE("GPL");
49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
67 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
68 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
69 static int ac97_clock;
70 static char *ac97_quirk;
71 static int buggy_semaphore;
72 static int buggy_irq = -1; /* auto-check */
74 static int spdif_aclink = -1;
76 module_param(index, int, 0444);
77 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
78 module_param(id, charp, 0444);
79 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
80 module_param(ac97_clock, int, 0444);
81 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
82 module_param(ac97_quirk, charp, 0444);
83 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
84 module_param(buggy_semaphore, bool, 0444);
85 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
86 module_param(buggy_irq, bool, 0444);
87 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
88 module_param(xbox, bool, 0444);
89 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
90 module_param(spdif_aclink, int, 0444);
91 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
93 /* just for backward compatibility */
95 module_param(enable, bool, 0444);
97 module_param(joystick, int, 0444);
102 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
104 #define ICHREG(x) ICH_REG_##x
106 #define DEFINE_REGSET(name,base) \
108 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
109 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
110 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
111 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
112 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
113 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
114 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
117 /* busmaster blocks */
118 DEFINE_REGSET(OFF, 0); /* offset */
119 DEFINE_REGSET(PI, 0x00); /* PCM in */
120 DEFINE_REGSET(PO, 0x10); /* PCM out */
121 DEFINE_REGSET(MC, 0x20); /* Mic in */
123 /* ICH4 busmaster blocks */
124 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
125 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
126 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
128 /* values for each busmaster block */
131 #define ICH_REG_LVI_MASK 0x1f
134 #define ICH_FIFOE 0x10 /* FIFO error */
135 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
136 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
137 #define ICH_CELV 0x02 /* current equals last valid */
138 #define ICH_DCH 0x01 /* DMA controller halted */
141 #define ICH_REG_PIV_MASK 0x1f /* mask */
144 #define ICH_IOCE 0x10 /* interrupt on completion enable */
145 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
146 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
147 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
148 #define ICH_STARTBM 0x01 /* start busmaster operation */
152 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
153 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
154 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
155 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
156 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
157 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
158 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
159 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
160 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
161 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
162 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
163 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
164 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
165 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
166 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
167 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
168 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
169 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
170 #define ICH_ACLINK 0x00000008 /* AClink shut off */
171 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
172 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
173 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
174 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
175 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
176 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
177 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
178 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
179 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
180 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
181 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
182 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
183 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
184 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
185 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
186 #define ICH_MD3 0x00020000 /* modem power down semaphore */
187 #define ICH_AD3 0x00010000 /* audio power down semaphore */
188 #define ICH_RCS 0x00008000 /* read completion status */
189 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
190 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
191 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
192 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
193 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
194 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
195 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
196 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
197 #define ICH_POINT 0x00000040 /* playback interrupt */
198 #define ICH_PIINT 0x00000020 /* capture interrupt */
199 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
200 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
201 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
202 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
203 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
204 #define ICH_CAS 0x01 /* codec access semaphore */
205 #define ICH_REG_SDM 0x80
206 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
207 #define ICH_DI2L_SHIFT 6
208 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
209 #define ICH_DI1L_SHIFT 4
210 #define ICH_SE 0x00000008 /* steer enable */
211 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
213 #define ICH_MAX_FRAGS 32 /* max hw frags */
217 * registers for Ali5455
220 /* ALi 5455 busmaster blocks */
221 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
222 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
223 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
224 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
225 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
226 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
227 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
228 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
229 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
230 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
231 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
234 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
235 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
236 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
237 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
238 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
239 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
240 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
241 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
242 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
243 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
244 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
245 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
246 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
247 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
248 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
249 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
250 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
251 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
252 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
253 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
254 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
257 #define ALI_CAS_SEM_BUSY 0x80000000
258 #define ALI_CPR_ADDR_SECONDARY 0x100
259 #define ALI_CPR_ADDR_READ 0x80
260 #define ALI_CSPSR_CODEC_READY 0x08
261 #define ALI_CSPSR_READ_OK 0x02
262 #define ALI_CSPSR_WRITE_OK 0x01
264 /* interrupts for the whole chip by interrupt status register finish */
266 #define ALI_INT_MICIN2 (1<<26)
267 #define ALI_INT_PCMIN2 (1<<25)
268 #define ALI_INT_I2SIN (1<<24)
269 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
270 #define ALI_INT_SPDIFIN (1<<22)
271 #define ALI_INT_LFEOUT (1<<21)
272 #define ALI_INT_CENTEROUT (1<<20)
273 #define ALI_INT_CODECSPDIFOUT (1<<19)
274 #define ALI_INT_MICIN (1<<18)
275 #define ALI_INT_PCMOUT (1<<17)
276 #define ALI_INT_PCMIN (1<<16)
277 #define ALI_INT_CPRAIS (1<<7) /* command port available */
278 #define ALI_INT_SPRAIS (1<<5) /* status port available */
279 #define ALI_INT_GPIO (1<<1)
280 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
281 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
283 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
284 #define ICH_ALI_SC_AC97_DBL (1<<30)
285 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
286 #define ICH_ALI_SC_IN_BITS (3<<18)
287 #define ICH_ALI_SC_OUT_BITS (3<<16)
288 #define ICH_ALI_SC_6CH_CFG (3<<14)
289 #define ICH_ALI_SC_PCM_4 (1<<8)
290 #define ICH_ALI_SC_PCM_6 (2<<8)
291 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
293 #define ICH_ALI_SS_SEC_ID (3<<5)
294 #define ICH_ALI_SS_PRI_ID (3<<3)
296 #define ICH_ALI_IF_AC97SP (1<<21)
297 #define ICH_ALI_IF_MC (1<<20)
298 #define ICH_ALI_IF_PI (1<<19)
299 #define ICH_ALI_IF_MC2 (1<<18)
300 #define ICH_ALI_IF_PI2 (1<<17)
301 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
302 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
303 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
304 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
305 #define ICH_ALI_IF_PO_SPDF (1<<3)
306 #define ICH_ALI_IF_PO (1<<1)
319 ICHD_LAST = ICHD_SPBAR
335 ALID_LAST = ALID_SPDIFOUT
338 #define get_ichdev(substream) (substream->runtime->private_data)
341 unsigned int ichd; /* ich device number */
342 unsigned long reg_offset; /* offset to bmaddr */
343 u32 *bdbar; /* CPU address (32bit) */
344 unsigned int bdbar_addr; /* PCI bus address (32bit) */
345 struct snd_pcm_substream *substream;
346 unsigned int physbuf; /* physical address (32bit) */
348 unsigned int fragsize;
349 unsigned int fragsize1;
350 unsigned int position;
351 unsigned int pos_shift;
358 unsigned int ack_bit;
359 unsigned int roff_sr;
360 unsigned int roff_picb;
361 unsigned int int_sta_mask; /* interrupt status mask */
362 unsigned int ali_slot; /* ALI DMA slot */
363 struct ac97_pcm *pcm;
365 unsigned int page_attr_changed: 1;
366 unsigned int suspended: 1;
370 unsigned int device_type;
375 void __iomem *bmaddr;
378 struct snd_card *card;
381 struct snd_pcm *pcm[6];
382 struct ichdev ichd[6];
388 unsigned in_ac97_init: 1,
390 unsigned in_measurement: 1; /* during ac97 clock measurement */
391 unsigned fix_nocache: 1; /* workaround for 440MX */
392 unsigned buggy_irq: 1; /* workaround for buggy mobos */
393 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
394 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
396 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
397 unsigned int sdm_saved; /* SDM reg value */
399 struct snd_ac97_bus *ac97_bus;
400 struct snd_ac97 *ac97[3];
401 unsigned int ac97_sdin[3];
402 unsigned int max_codecs, ncodecs;
403 unsigned int *codec_bit;
404 unsigned int codec_isr_bits;
405 unsigned int codec_ready_bits;
410 struct snd_dma_buffer bdbars;
411 u32 int_sta_reg; /* interrupt status register */
412 u32 int_sta_mask; /* interrupt status mask */
415 static struct pci_device_id snd_intel8x0_ids[] = {
416 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
417 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
418 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
419 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
420 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
421 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
422 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
423 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
424 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
425 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
426 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
427 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
428 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
429 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
430 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
431 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
432 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
433 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
434 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
435 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */
436 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
437 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
438 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
442 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
445 * Lowlevel I/O - busmaster
448 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
450 return ioread8(chip->bmaddr + offset);
453 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
455 return ioread16(chip->bmaddr + offset);
458 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
460 return ioread32(chip->bmaddr + offset);
463 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
465 iowrite8(val, chip->bmaddr + offset);
468 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
470 iowrite16(val, chip->bmaddr + offset);
473 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
475 iowrite32(val, chip->bmaddr + offset);
479 * Lowlevel I/O - AC'97 registers
482 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
484 return ioread16(chip->addr + offset);
487 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
489 iowrite16(val, chip->addr + offset);
497 * access to AC97 codec via normal i/o (for ICH and SIS7012)
500 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
506 if (chip->in_sdin_init) {
507 /* we don't know the ready bit assignment at the moment */
508 /* so we check any */
509 codec = chip->codec_isr_bits;
511 codec = chip->codec_bit[chip->ac97_sdin[codec]];
515 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
518 if (chip->buggy_semaphore)
519 return 0; /* just ignore ... */
521 /* Anyone holding a semaphore for 1 msec should be shot... */
524 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
529 /* access to some forbidden (non existant) ac97 registers will not
530 * reset the semaphore. So even if you don't get the semaphore, still
531 * continue the access. We don't need the semaphore anyway. */
532 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
533 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
534 iagetword(chip, 0); /* clear semaphore flag */
535 /* I don't care about the semaphore */
539 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
543 struct intel8x0 *chip = ac97->private_data;
545 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
546 if (! chip->in_ac97_init)
547 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
549 iaputword(chip, reg + ac97->num * 0x80, val);
552 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
555 struct intel8x0 *chip = ac97->private_data;
559 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
560 if (! chip->in_ac97_init)
561 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
564 res = iagetword(chip, reg + ac97->num * 0x80);
565 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
566 /* reset RCS and preserve other R/WC bits */
567 iputdword(chip, ICHREG(GLOB_STA), tmp &
568 ~(chip->codec_ready_bits | ICH_GSCI));
569 if (! chip->in_ac97_init)
570 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
577 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
582 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
583 iagetword(chip, codec * 0x80);
584 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
585 /* reset RCS and preserve other R/WC bits */
586 iputdword(chip, ICHREG(GLOB_STA), tmp &
587 ~(chip->codec_ready_bits | ICH_GSCI));
593 * access to AC97 for Ali5455
595 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
598 for (count = 0; count < 0x7f; count++) {
599 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
603 if (! chip->in_ac97_init)
604 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
608 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
611 if (chip->buggy_semaphore)
612 return 0; /* just ignore ... */
613 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
615 if (! time && ! chip->in_ac97_init)
616 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
617 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
620 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
622 struct intel8x0 *chip = ac97->private_data;
623 unsigned short data = 0xffff;
625 if (snd_intel8x0_ali_codec_semaphore(chip))
627 reg |= ALI_CPR_ADDR_READ;
629 reg |= ALI_CPR_ADDR_SECONDARY;
630 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
631 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
633 data = igetword(chip, ICHREG(ALI_SPR));
638 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
641 struct intel8x0 *chip = ac97->private_data;
643 if (snd_intel8x0_ali_codec_semaphore(chip))
645 iputword(chip, ICHREG(ALI_CPR), val);
647 reg |= ALI_CPR_ADDR_SECONDARY;
648 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
649 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
656 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
659 u32 *bdbar = ichdev->bdbar;
660 unsigned long port = ichdev->reg_offset;
662 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
663 if (ichdev->size == ichdev->fragsize) {
664 ichdev->ack_reload = ichdev->ack = 2;
665 ichdev->fragsize1 = ichdev->fragsize >> 1;
666 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
667 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
668 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
669 ichdev->fragsize1 >> ichdev->pos_shift);
670 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
671 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
672 ichdev->fragsize1 >> ichdev->pos_shift);
676 ichdev->ack_reload = ichdev->ack = 1;
677 ichdev->fragsize1 = ichdev->fragsize;
678 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
679 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
680 (((idx >> 1) * ichdev->fragsize) %
682 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
683 ichdev->fragsize >> ichdev->pos_shift);
685 printk("bdbar[%i] = 0x%x [0x%x]\n",
686 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
689 ichdev->frags = ichdev->size / ichdev->fragsize;
691 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
693 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
694 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
695 ichdev->position = 0;
697 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
698 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
700 /* clear interrupts */
701 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
706 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
707 * which aborts PCI busmaster for audio transfer. A workaround is to set
708 * the pages as non-cached. For details, see the errata in
709 * http://www.intel.com/design/chipsets/specupdt/245051.htm
711 static void fill_nocache(void *buf, int size, int nocache)
713 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
715 set_pages_uc(virt_to_page(buf), size);
717 set_pages_wb(virt_to_page(buf), size);
721 #define fill_nocache(buf, size, nocache) do { ; } while (0)
728 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
730 unsigned long port = ichdev->reg_offset;
732 int status, civ, i, step;
735 spin_lock_irqsave(&chip->reg_lock, flags);
736 status = igetbyte(chip, port + ichdev->roff_sr);
737 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
738 if (!(status & ICH_BCIS)) {
740 } else if (civ == ichdev->civ) {
741 // snd_printd("civ same %d\n", civ);
744 ichdev->civ &= ICH_REG_LVI_MASK;
746 step = civ - ichdev->civ;
748 step += ICH_REG_LVI_MASK + 1;
750 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
754 ichdev->position += step * ichdev->fragsize1;
755 if (! chip->in_measurement)
756 ichdev->position %= ichdev->size;
758 ichdev->lvi &= ICH_REG_LVI_MASK;
759 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
760 for (i = 0; i < step; i++) {
762 ichdev->lvi_frag %= ichdev->frags;
763 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
765 printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
766 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
767 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
768 inl(port + 4), inb(port + ICH_REG_OFF_CR));
770 if (--ichdev->ack == 0) {
771 ichdev->ack = ichdev->ack_reload;
775 spin_unlock_irqrestore(&chip->reg_lock, flags);
776 if (ack && ichdev->substream) {
777 snd_pcm_period_elapsed(ichdev->substream);
779 iputbyte(chip, port + ichdev->roff_sr,
780 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
783 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
785 struct intel8x0 *chip = dev_id;
786 struct ichdev *ichdev;
790 status = igetdword(chip, chip->int_sta_reg);
791 if (status == 0xffffffff) /* we are not yet resumed */
794 if ((status & chip->int_sta_mask) == 0) {
797 iputdword(chip, chip->int_sta_reg, status);
798 if (! chip->buggy_irq)
801 return IRQ_RETVAL(status);
804 for (i = 0; i < chip->bdbars_count; i++) {
805 ichdev = &chip->ichd[i];
806 if (status & ichdev->int_sta_mask)
807 snd_intel8x0_update(chip, ichdev);
811 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
820 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
822 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
823 struct ichdev *ichdev = get_ichdev(substream);
824 unsigned char val = 0;
825 unsigned long port = ichdev->reg_offset;
828 case SNDRV_PCM_TRIGGER_RESUME:
829 ichdev->suspended = 0;
831 case SNDRV_PCM_TRIGGER_START:
832 val = ICH_IOCE | ICH_STARTBM;
834 case SNDRV_PCM_TRIGGER_SUSPEND:
835 ichdev->suspended = 1;
837 case SNDRV_PCM_TRIGGER_STOP:
840 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
843 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
844 val = ICH_IOCE | ICH_STARTBM;
849 iputbyte(chip, port + ICH_REG_OFF_CR, val);
850 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
851 /* wait until DMA stopped */
852 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
853 /* reset whole DMA things */
854 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
859 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
861 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
862 struct ichdev *ichdev = get_ichdev(substream);
863 unsigned long port = ichdev->reg_offset;
864 static int fiforeg[] = {
865 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
867 unsigned int val, fifo;
869 val = igetdword(chip, ICHREG(ALI_DMACR));
871 case SNDRV_PCM_TRIGGER_RESUME:
872 ichdev->suspended = 0;
874 case SNDRV_PCM_TRIGGER_START:
875 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
876 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
877 /* clear FIFO for synchronization of channels */
878 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
879 fifo &= ~(0xff << (ichdev->ali_slot % 4));
880 fifo |= 0x83 << (ichdev->ali_slot % 4);
881 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
883 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
884 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
886 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
888 case SNDRV_PCM_TRIGGER_SUSPEND:
889 ichdev->suspended = 1;
891 case SNDRV_PCM_TRIGGER_STOP:
892 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
894 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
895 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
896 while (igetbyte(chip, port + ICH_REG_OFF_CR))
898 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
900 /* reset whole DMA things */
901 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
902 /* clear interrupts */
903 iputbyte(chip, port + ICH_REG_OFF_SR,
904 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
905 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
906 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
914 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
915 struct snd_pcm_hw_params *hw_params)
917 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
918 struct ichdev *ichdev = get_ichdev(substream);
919 struct snd_pcm_runtime *runtime = substream->runtime;
920 int dbl = params_rate(hw_params) > 48000;
923 if (chip->fix_nocache && ichdev->page_attr_changed) {
924 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
925 ichdev->page_attr_changed = 0;
927 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
930 if (chip->fix_nocache) {
931 if (runtime->dma_area && ! ichdev->page_attr_changed) {
932 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
933 ichdev->page_attr_changed = 1;
936 if (ichdev->pcm_open_flag) {
937 snd_ac97_pcm_close(ichdev->pcm);
938 ichdev->pcm_open_flag = 0;
940 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
941 params_channels(hw_params),
942 ichdev->pcm->r[dbl].slots);
944 ichdev->pcm_open_flag = 1;
945 /* Force SPDIF setting */
946 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
947 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
948 params_rate(hw_params));
953 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
955 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
956 struct ichdev *ichdev = get_ichdev(substream);
958 if (ichdev->pcm_open_flag) {
959 snd_ac97_pcm_close(ichdev->pcm);
960 ichdev->pcm_open_flag = 0;
962 if (chip->fix_nocache && ichdev->page_attr_changed) {
963 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
964 ichdev->page_attr_changed = 0;
966 return snd_pcm_lib_free_pages(substream);
969 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
970 struct snd_pcm_runtime *runtime)
973 int dbl = runtime->rate > 48000;
975 spin_lock_irq(&chip->reg_lock);
976 switch (chip->device_type) {
978 cnt = igetdword(chip, ICHREG(ALI_SCR));
979 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
980 if (runtime->channels == 4 || dbl)
981 cnt |= ICH_ALI_SC_PCM_4;
982 else if (runtime->channels == 6)
983 cnt |= ICH_ALI_SC_PCM_6;
984 iputdword(chip, ICHREG(ALI_SCR), cnt);
987 cnt = igetdword(chip, ICHREG(GLOB_CNT));
988 cnt &= ~ICH_SIS_PCM_246_MASK;
989 if (runtime->channels == 4 || dbl)
990 cnt |= ICH_SIS_PCM_4;
991 else if (runtime->channels == 6)
992 cnt |= ICH_SIS_PCM_6;
993 iputdword(chip, ICHREG(GLOB_CNT), cnt);
996 cnt = igetdword(chip, ICHREG(GLOB_CNT));
997 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
998 if (runtime->channels == 4 || dbl)
1000 else if (runtime->channels == 6)
1002 if (chip->device_type == DEVICE_NFORCE) {
1003 /* reset to 2ch once to keep the 6 channel data in alignment,
1004 * to start from Front Left always
1006 if (cnt & ICH_PCM_246_MASK) {
1007 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1008 spin_unlock_irq(&chip->reg_lock);
1009 msleep(50); /* grrr... */
1010 spin_lock_irq(&chip->reg_lock);
1012 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1013 if (runtime->sample_bits > 16)
1014 cnt |= ICH_PCM_20BIT;
1016 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1019 spin_unlock_irq(&chip->reg_lock);
1022 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1024 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1025 struct snd_pcm_runtime *runtime = substream->runtime;
1026 struct ichdev *ichdev = get_ichdev(substream);
1028 ichdev->physbuf = runtime->dma_addr;
1029 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1030 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1031 if (ichdev->ichd == ICHD_PCMOUT) {
1032 snd_intel8x0_setup_pcm_out(chip, runtime);
1033 if (chip->device_type == DEVICE_INTEL_ICH4)
1034 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1036 snd_intel8x0_setup_periods(chip, ichdev);
1040 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1042 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1043 struct ichdev *ichdev = get_ichdev(substream);
1045 int civ, timeout = 100;
1046 unsigned int position;
1048 spin_lock(&chip->reg_lock);
1050 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1051 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1052 position = ichdev->position;
1057 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1058 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1060 } while (timeout--);
1061 ptr1 <<= ichdev->pos_shift;
1062 ptr = ichdev->fragsize1 - ptr1;
1064 spin_unlock(&chip->reg_lock);
1065 if (ptr >= ichdev->size)
1067 return bytes_to_frames(substream->runtime, ptr);
1070 static struct snd_pcm_hardware snd_intel8x0_stream =
1072 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1073 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1074 SNDRV_PCM_INFO_MMAP_VALID |
1075 SNDRV_PCM_INFO_PAUSE |
1076 SNDRV_PCM_INFO_RESUME),
1077 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1078 .rates = SNDRV_PCM_RATE_48000,
1083 .buffer_bytes_max = 128 * 1024,
1084 .period_bytes_min = 32,
1085 .period_bytes_max = 128 * 1024,
1087 .periods_max = 1024,
1091 static unsigned int channels4[] = {
1095 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1096 .count = ARRAY_SIZE(channels4),
1101 static unsigned int channels6[] = {
1105 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1106 .count = ARRAY_SIZE(channels6),
1111 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1113 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1114 struct snd_pcm_runtime *runtime = substream->runtime;
1117 ichdev->substream = substream;
1118 runtime->hw = snd_intel8x0_stream;
1119 runtime->hw.rates = ichdev->pcm->rates;
1120 snd_pcm_limit_hw_rates(runtime);
1121 if (chip->device_type == DEVICE_SIS) {
1122 runtime->hw.buffer_bytes_max = 64*1024;
1123 runtime->hw.period_bytes_max = 64*1024;
1125 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1127 runtime->private_data = ichdev;
1131 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1133 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1134 struct snd_pcm_runtime *runtime = substream->runtime;
1137 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1142 runtime->hw.channels_max = 6;
1143 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1144 &hw_constraints_channels6);
1145 } else if (chip->multi4) {
1146 runtime->hw.channels_max = 4;
1147 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1148 &hw_constraints_channels4);
1151 snd_ac97_pcm_double_rate_rules(runtime);
1153 if (chip->smp20bit) {
1154 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1155 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1160 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1162 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1164 chip->ichd[ICHD_PCMOUT].substream = NULL;
1168 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1170 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1172 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1175 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1177 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1179 chip->ichd[ICHD_PCMIN].substream = NULL;
1183 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1185 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1187 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1190 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1192 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1194 chip->ichd[ICHD_MIC].substream = NULL;
1198 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1200 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1202 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1205 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1207 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1209 chip->ichd[ICHD_MIC2].substream = NULL;
1213 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1215 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1217 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1220 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1222 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1224 chip->ichd[ICHD_PCM2IN].substream = NULL;
1228 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1230 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1231 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1233 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1236 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1238 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1239 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1241 chip->ichd[idx].substream = NULL;
1245 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1247 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1250 spin_lock_irq(&chip->reg_lock);
1251 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1252 val |= ICH_ALI_IF_AC97SP;
1253 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1254 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1255 spin_unlock_irq(&chip->reg_lock);
1257 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1260 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1262 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1265 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1266 spin_lock_irq(&chip->reg_lock);
1267 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1268 val &= ~ICH_ALI_IF_AC97SP;
1269 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1270 spin_unlock_irq(&chip->reg_lock);
1276 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1278 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1280 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1283 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1285 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1287 chip->ichd[ALID_SPDIFIN].substream = NULL;
1291 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1293 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1295 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1298 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1300 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1302 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1307 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1308 .open = snd_intel8x0_playback_open,
1309 .close = snd_intel8x0_playback_close,
1310 .ioctl = snd_pcm_lib_ioctl,
1311 .hw_params = snd_intel8x0_hw_params,
1312 .hw_free = snd_intel8x0_hw_free,
1313 .prepare = snd_intel8x0_pcm_prepare,
1314 .trigger = snd_intel8x0_pcm_trigger,
1315 .pointer = snd_intel8x0_pcm_pointer,
1318 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1319 .open = snd_intel8x0_capture_open,
1320 .close = snd_intel8x0_capture_close,
1321 .ioctl = snd_pcm_lib_ioctl,
1322 .hw_params = snd_intel8x0_hw_params,
1323 .hw_free = snd_intel8x0_hw_free,
1324 .prepare = snd_intel8x0_pcm_prepare,
1325 .trigger = snd_intel8x0_pcm_trigger,
1326 .pointer = snd_intel8x0_pcm_pointer,
1329 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1330 .open = snd_intel8x0_mic_open,
1331 .close = snd_intel8x0_mic_close,
1332 .ioctl = snd_pcm_lib_ioctl,
1333 .hw_params = snd_intel8x0_hw_params,
1334 .hw_free = snd_intel8x0_hw_free,
1335 .prepare = snd_intel8x0_pcm_prepare,
1336 .trigger = snd_intel8x0_pcm_trigger,
1337 .pointer = snd_intel8x0_pcm_pointer,
1340 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1341 .open = snd_intel8x0_mic2_open,
1342 .close = snd_intel8x0_mic2_close,
1343 .ioctl = snd_pcm_lib_ioctl,
1344 .hw_params = snd_intel8x0_hw_params,
1345 .hw_free = snd_intel8x0_hw_free,
1346 .prepare = snd_intel8x0_pcm_prepare,
1347 .trigger = snd_intel8x0_pcm_trigger,
1348 .pointer = snd_intel8x0_pcm_pointer,
1351 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1352 .open = snd_intel8x0_capture2_open,
1353 .close = snd_intel8x0_capture2_close,
1354 .ioctl = snd_pcm_lib_ioctl,
1355 .hw_params = snd_intel8x0_hw_params,
1356 .hw_free = snd_intel8x0_hw_free,
1357 .prepare = snd_intel8x0_pcm_prepare,
1358 .trigger = snd_intel8x0_pcm_trigger,
1359 .pointer = snd_intel8x0_pcm_pointer,
1362 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1363 .open = snd_intel8x0_spdif_open,
1364 .close = snd_intel8x0_spdif_close,
1365 .ioctl = snd_pcm_lib_ioctl,
1366 .hw_params = snd_intel8x0_hw_params,
1367 .hw_free = snd_intel8x0_hw_free,
1368 .prepare = snd_intel8x0_pcm_prepare,
1369 .trigger = snd_intel8x0_pcm_trigger,
1370 .pointer = snd_intel8x0_pcm_pointer,
1373 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1374 .open = snd_intel8x0_playback_open,
1375 .close = snd_intel8x0_playback_close,
1376 .ioctl = snd_pcm_lib_ioctl,
1377 .hw_params = snd_intel8x0_hw_params,
1378 .hw_free = snd_intel8x0_hw_free,
1379 .prepare = snd_intel8x0_pcm_prepare,
1380 .trigger = snd_intel8x0_ali_trigger,
1381 .pointer = snd_intel8x0_pcm_pointer,
1384 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1385 .open = snd_intel8x0_capture_open,
1386 .close = snd_intel8x0_capture_close,
1387 .ioctl = snd_pcm_lib_ioctl,
1388 .hw_params = snd_intel8x0_hw_params,
1389 .hw_free = snd_intel8x0_hw_free,
1390 .prepare = snd_intel8x0_pcm_prepare,
1391 .trigger = snd_intel8x0_ali_trigger,
1392 .pointer = snd_intel8x0_pcm_pointer,
1395 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1396 .open = snd_intel8x0_mic_open,
1397 .close = snd_intel8x0_mic_close,
1398 .ioctl = snd_pcm_lib_ioctl,
1399 .hw_params = snd_intel8x0_hw_params,
1400 .hw_free = snd_intel8x0_hw_free,
1401 .prepare = snd_intel8x0_pcm_prepare,
1402 .trigger = snd_intel8x0_ali_trigger,
1403 .pointer = snd_intel8x0_pcm_pointer,
1406 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1407 .open = snd_intel8x0_ali_ac97spdifout_open,
1408 .close = snd_intel8x0_ali_ac97spdifout_close,
1409 .ioctl = snd_pcm_lib_ioctl,
1410 .hw_params = snd_intel8x0_hw_params,
1411 .hw_free = snd_intel8x0_hw_free,
1412 .prepare = snd_intel8x0_pcm_prepare,
1413 .trigger = snd_intel8x0_ali_trigger,
1414 .pointer = snd_intel8x0_pcm_pointer,
1418 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1419 .open = snd_intel8x0_ali_spdifin_open,
1420 .close = snd_intel8x0_ali_spdifin_close,
1421 .ioctl = snd_pcm_lib_ioctl,
1422 .hw_params = snd_intel8x0_hw_params,
1423 .hw_free = snd_intel8x0_hw_free,
1424 .prepare = snd_intel8x0_pcm_prepare,
1425 .trigger = snd_intel8x0_pcm_trigger,
1426 .pointer = snd_intel8x0_pcm_pointer,
1429 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1430 .open = snd_intel8x0_ali_spdifout_open,
1431 .close = snd_intel8x0_ali_spdifout_close,
1432 .ioctl = snd_pcm_lib_ioctl,
1433 .hw_params = snd_intel8x0_hw_params,
1434 .hw_free = snd_intel8x0_hw_free,
1435 .prepare = snd_intel8x0_pcm_prepare,
1436 .trigger = snd_intel8x0_pcm_trigger,
1437 .pointer = snd_intel8x0_pcm_pointer,
1441 struct ich_pcm_table {
1443 struct snd_pcm_ops *playback_ops;
1444 struct snd_pcm_ops *capture_ops;
1445 size_t prealloc_size;
1446 size_t prealloc_max_size;
1450 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1451 struct ich_pcm_table *rec)
1453 struct snd_pcm *pcm;
1458 sprintf(name, "Intel ICH - %s", rec->suffix);
1460 strcpy(name, "Intel ICH");
1461 err = snd_pcm_new(chip->card, name, device,
1462 rec->playback_ops ? 1 : 0,
1463 rec->capture_ops ? 1 : 0, &pcm);
1467 if (rec->playback_ops)
1468 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1469 if (rec->capture_ops)
1470 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1472 pcm->private_data = chip;
1473 pcm->info_flags = 0;
1475 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1477 strcpy(pcm->name, chip->card->shortname);
1478 chip->pcm[device] = pcm;
1480 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1481 snd_dma_pci_data(chip->pci),
1482 rec->prealloc_size, rec->prealloc_max_size);
1487 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1489 .playback_ops = &snd_intel8x0_playback_ops,
1490 .capture_ops = &snd_intel8x0_capture_ops,
1491 .prealloc_size = 64 * 1024,
1492 .prealloc_max_size = 128 * 1024,
1495 .suffix = "MIC ADC",
1496 .capture_ops = &snd_intel8x0_capture_mic_ops,
1498 .prealloc_max_size = 128 * 1024,
1499 .ac97_idx = ICHD_MIC,
1502 .suffix = "MIC2 ADC",
1503 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1505 .prealloc_max_size = 128 * 1024,
1506 .ac97_idx = ICHD_MIC2,
1510 .capture_ops = &snd_intel8x0_capture2_ops,
1512 .prealloc_max_size = 128 * 1024,
1513 .ac97_idx = ICHD_PCM2IN,
1517 .playback_ops = &snd_intel8x0_spdif_ops,
1518 .prealloc_size = 64 * 1024,
1519 .prealloc_max_size = 128 * 1024,
1520 .ac97_idx = ICHD_SPBAR,
1524 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1526 .playback_ops = &snd_intel8x0_playback_ops,
1527 .capture_ops = &snd_intel8x0_capture_ops,
1528 .prealloc_size = 64 * 1024,
1529 .prealloc_max_size = 128 * 1024,
1532 .suffix = "MIC ADC",
1533 .capture_ops = &snd_intel8x0_capture_mic_ops,
1535 .prealloc_max_size = 128 * 1024,
1536 .ac97_idx = NVD_MIC,
1540 .playback_ops = &snd_intel8x0_spdif_ops,
1541 .prealloc_size = 64 * 1024,
1542 .prealloc_max_size = 128 * 1024,
1543 .ac97_idx = NVD_SPBAR,
1547 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1549 .playback_ops = &snd_intel8x0_ali_playback_ops,
1550 .capture_ops = &snd_intel8x0_ali_capture_ops,
1551 .prealloc_size = 64 * 1024,
1552 .prealloc_max_size = 128 * 1024,
1555 .suffix = "MIC ADC",
1556 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1558 .prealloc_max_size = 128 * 1024,
1559 .ac97_idx = ALID_MIC,
1563 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1564 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1565 .prealloc_size = 64 * 1024,
1566 .prealloc_max_size = 128 * 1024,
1567 .ac97_idx = ALID_AC97SPDIFOUT,
1571 .suffix = "HW IEC958",
1572 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1573 .prealloc_size = 64 * 1024,
1574 .prealloc_max_size = 128 * 1024,
1579 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1581 int i, tblsize, device, err;
1582 struct ich_pcm_table *tbl, *rec;
1584 switch (chip->device_type) {
1585 case DEVICE_INTEL_ICH4:
1587 tblsize = ARRAY_SIZE(intel_pcms);
1593 tblsize = ARRAY_SIZE(nforce_pcms);
1599 tblsize = ARRAY_SIZE(ali_pcms);
1608 for (i = 0; i < tblsize; i++) {
1610 if (i > 0 && rec->ac97_idx) {
1611 /* activate PCM only when associated AC'97 codec */
1612 if (! chip->ichd[rec->ac97_idx].pcm)
1615 err = snd_intel8x0_pcm1(chip, device, rec);
1621 chip->pcm_devs = device;
1630 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1632 struct intel8x0 *chip = bus->private_data;
1633 chip->ac97_bus = NULL;
1636 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1638 struct intel8x0 *chip = ac97->private_data;
1639 chip->ac97[ac97->num] = NULL;
1642 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1647 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1648 (1 << AC97_SLOT_PCM_RIGHT) |
1649 (1 << AC97_SLOT_PCM_CENTER) |
1650 (1 << AC97_SLOT_PCM_SLEFT) |
1651 (1 << AC97_SLOT_PCM_SRIGHT) |
1652 (1 << AC97_SLOT_LFE)
1655 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1656 (1 << AC97_SLOT_PCM_RIGHT) |
1657 (1 << AC97_SLOT_PCM_LEFT_0) |
1658 (1 << AC97_SLOT_PCM_RIGHT_0)
1667 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1668 (1 << AC97_SLOT_PCM_RIGHT)
1677 .slots = (1 << AC97_SLOT_MIC)
1686 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1687 (1 << AC97_SLOT_SPDIF_RIGHT2)
1696 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1697 (1 << AC97_SLOT_PCM_RIGHT)
1706 .slots = (1 << AC97_SLOT_MIC)
1712 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1714 .subvendor = 0x0e11,
1715 .subdevice = 0x008a,
1716 .name = "Compaq Evo W4000", /* AD1885 */
1717 .type = AC97_TUNE_HP_ONLY
1720 .subvendor = 0x0e11,
1721 .subdevice = 0x00b8,
1722 .name = "Compaq Evo D510C",
1723 .type = AC97_TUNE_HP_ONLY
1726 .subvendor = 0x0e11,
1727 .subdevice = 0x0860,
1728 .name = "HP/Compaq nx7010",
1729 .type = AC97_TUNE_MUTE_LED
1732 .subvendor = 0x1014,
1733 .subdevice = 0x1f00,
1735 .type = AC97_TUNE_ALC_JACK
1738 .subvendor = 0x1014,
1739 .subdevice = 0x0267,
1740 .name = "IBM NetVista A30p", /* AD1981B */
1741 .type = AC97_TUNE_HP_ONLY
1744 .subvendor = 0x1025,
1745 .subdevice = 0x0083,
1746 .name = "Acer Aspire 3003LCi",
1747 .type = AC97_TUNE_HP_ONLY
1750 .subvendor = 0x1028,
1751 .subdevice = 0x00d8,
1752 .name = "Dell Precision 530", /* AD1885 */
1753 .type = AC97_TUNE_HP_ONLY
1756 .subvendor = 0x1028,
1757 .subdevice = 0x010d,
1758 .name = "Dell", /* which model? AD1885 */
1759 .type = AC97_TUNE_HP_ONLY
1762 .subvendor = 0x1028,
1763 .subdevice = 0x0126,
1764 .name = "Dell Optiplex GX260", /* AD1981A */
1765 .type = AC97_TUNE_HP_ONLY
1768 .subvendor = 0x1028,
1769 .subdevice = 0x012c,
1770 .name = "Dell Precision 650", /* AD1981A */
1771 .type = AC97_TUNE_HP_ONLY
1774 .subvendor = 0x1028,
1775 .subdevice = 0x012d,
1776 .name = "Dell Precision 450", /* AD1981B*/
1777 .type = AC97_TUNE_HP_ONLY
1780 .subvendor = 0x1028,
1781 .subdevice = 0x0147,
1782 .name = "Dell", /* which model? AD1981B*/
1783 .type = AC97_TUNE_HP_ONLY
1786 .subvendor = 0x1028,
1787 .subdevice = 0x0151,
1788 .name = "Dell Optiplex GX270", /* AD1981B */
1789 .type = AC97_TUNE_HP_ONLY
1792 .subvendor = 0x1028,
1793 .subdevice = 0x014e,
1794 .name = "Dell D800", /* STAC9750/51 */
1795 .type = AC97_TUNE_HP_ONLY
1798 .subvendor = 0x1028,
1799 .subdevice = 0x0163,
1800 .name = "Dell Unknown", /* STAC9750/51 */
1801 .type = AC97_TUNE_HP_ONLY
1804 .subvendor = 0x1028,
1805 .subdevice = 0x0186,
1806 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1807 .type = AC97_TUNE_HP_MUTE_LED
1810 .subvendor = 0x1028,
1811 .subdevice = 0x0188,
1812 .name = "Dell Inspiron 6000",
1813 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1816 .subvendor = 0x1028,
1817 .subdevice = 0x0191,
1818 .name = "Dell Inspiron 8600",
1819 .type = AC97_TUNE_HP_ONLY
1822 .subvendor = 0x103c,
1823 .subdevice = 0x006d,
1824 .name = "HP zv5000",
1825 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1827 { /* FIXME: which codec? */
1828 .subvendor = 0x103c,
1829 .subdevice = 0x00c3,
1830 .name = "HP xw6000",
1831 .type = AC97_TUNE_HP_ONLY
1834 .subvendor = 0x103c,
1835 .subdevice = 0x088c,
1836 .name = "HP nc8000",
1837 .type = AC97_TUNE_HP_MUTE_LED
1840 .subvendor = 0x103c,
1841 .subdevice = 0x0890,
1842 .name = "HP nc6000",
1843 .type = AC97_TUNE_MUTE_LED
1846 .subvendor = 0x103c,
1847 .subdevice = 0x0934,
1848 .name = "HP nx8220",
1849 .type = AC97_TUNE_MUTE_LED
1852 .subvendor = 0x103c,
1853 .subdevice = 0x129d,
1854 .name = "HP xw8000",
1855 .type = AC97_TUNE_HP_ONLY
1858 .subvendor = 0x103c,
1859 .subdevice = 0x0938,
1860 .name = "HP nc4200",
1861 .type = AC97_TUNE_HP_MUTE_LED
1864 .subvendor = 0x103c,
1865 .subdevice = 0x099c,
1866 .name = "HP nx6110/nc6120",
1867 .type = AC97_TUNE_HP_MUTE_LED
1870 .subvendor = 0x103c,
1871 .subdevice = 0x0944,
1872 .name = "HP nc6220",
1873 .type = AC97_TUNE_HP_MUTE_LED
1876 .subvendor = 0x103c,
1877 .subdevice = 0x0934,
1878 .name = "HP nc8220",
1879 .type = AC97_TUNE_HP_MUTE_LED
1882 .subvendor = 0x103c,
1883 .subdevice = 0x12f1,
1884 .name = "HP xw8200", /* AD1981B*/
1885 .type = AC97_TUNE_HP_ONLY
1888 .subvendor = 0x103c,
1889 .subdevice = 0x12f2,
1890 .name = "HP xw6200",
1891 .type = AC97_TUNE_HP_ONLY
1894 .subvendor = 0x103c,
1895 .subdevice = 0x3008,
1896 .name = "HP xw4200", /* AD1981B*/
1897 .type = AC97_TUNE_HP_ONLY
1900 .subvendor = 0x104d,
1901 .subdevice = 0x8197,
1902 .name = "Sony S1XP",
1903 .type = AC97_TUNE_INV_EAPD
1906 .subvendor = 0x1043,
1907 .subdevice = 0x80f3,
1908 .name = "ASUS ICH5/AD1985",
1909 .type = AC97_TUNE_AD_SHARING
1912 .subvendor = 0x10cf,
1913 .subdevice = 0x11c3,
1914 .name = "Fujitsu-Siemens E4010",
1915 .type = AC97_TUNE_HP_ONLY
1918 .subvendor = 0x10cf,
1919 .subdevice = 0x1225,
1920 .name = "Fujitsu-Siemens T3010",
1921 .type = AC97_TUNE_HP_ONLY
1924 .subvendor = 0x10cf,
1925 .subdevice = 0x1253,
1926 .name = "Fujitsu S6210", /* STAC9750/51 */
1927 .type = AC97_TUNE_HP_ONLY
1930 .subvendor = 0x10cf,
1931 .subdevice = 0x127e,
1932 .name = "Fujitsu Lifebook C1211D",
1933 .type = AC97_TUNE_HP_ONLY
1936 .subvendor = 0x10cf,
1937 .subdevice = 0x12ec,
1938 .name = "Fujitsu-Siemens 4010",
1939 .type = AC97_TUNE_HP_ONLY
1942 .subvendor = 0x10cf,
1943 .subdevice = 0x12f2,
1944 .name = "Fujitsu-Siemens Celsius H320",
1945 .type = AC97_TUNE_SWAP_HP
1948 .subvendor = 0x10f1,
1949 .subdevice = 0x2665,
1950 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1951 .type = AC97_TUNE_HP_ONLY
1954 .subvendor = 0x10f1,
1955 .subdevice = 0x2885,
1956 .name = "AMD64 Mobo", /* ALC650 */
1957 .type = AC97_TUNE_HP_ONLY
1960 .subvendor = 0x10f1,
1961 .subdevice = 0x2895,
1962 .name = "Tyan Thunder K8WE",
1963 .type = AC97_TUNE_HP_ONLY
1966 .subvendor = 0x10f7,
1967 .subdevice = 0x834c,
1968 .name = "Panasonic CF-R4",
1969 .type = AC97_TUNE_HP_ONLY,
1972 .subvendor = 0x110a,
1973 .subdevice = 0x0056,
1974 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1975 .type = AC97_TUNE_HP_ONLY
1978 .subvendor = 0x11d4,
1979 .subdevice = 0x5375,
1980 .name = "ADI AD1985 (discrete)",
1981 .type = AC97_TUNE_HP_ONLY
1984 .subvendor = 0x1462,
1985 .subdevice = 0x5470,
1986 .name = "MSI P4 ATX 645 Ultra",
1987 .type = AC97_TUNE_HP_ONLY
1990 .subvendor = 0x1734,
1991 .subdevice = 0x0088,
1992 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1993 .type = AC97_TUNE_HP_ONLY
1996 .subvendor = 0x8086,
1997 .subdevice = 0x2000,
1999 .name = "Intel ICH5/AD1985",
2000 .type = AC97_TUNE_AD_SHARING
2003 .subvendor = 0x8086,
2004 .subdevice = 0x4000,
2006 .name = "Intel ICH5/AD1985",
2007 .type = AC97_TUNE_AD_SHARING
2010 .subvendor = 0x8086,
2011 .subdevice = 0x4856,
2012 .name = "Intel D845WN (82801BA)",
2013 .type = AC97_TUNE_SWAP_HP
2016 .subvendor = 0x8086,
2017 .subdevice = 0x4d44,
2018 .name = "Intel D850EMV2", /* AD1885 */
2019 .type = AC97_TUNE_HP_ONLY
2022 .subvendor = 0x8086,
2023 .subdevice = 0x4d56,
2024 .name = "Intel ICH/AD1885",
2025 .type = AC97_TUNE_HP_ONLY
2028 .subvendor = 0x8086,
2029 .subdevice = 0x6000,
2031 .name = "Intel ICH5/AD1985",
2032 .type = AC97_TUNE_AD_SHARING
2035 .subvendor = 0x8086,
2036 .subdevice = 0xe000,
2038 .name = "Intel ICH5/AD1985",
2039 .type = AC97_TUNE_AD_SHARING
2041 #if 0 /* FIXME: this seems wrong on most boards */
2043 .subvendor = 0x8086,
2044 .subdevice = 0xa000,
2046 .name = "Intel ICH5/AD1985",
2047 .type = AC97_TUNE_HP_ONLY
2050 { } /* terminator */
2053 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2054 const char *quirk_override)
2056 struct snd_ac97_bus *pbus;
2057 struct snd_ac97_template ac97;
2059 unsigned int i, codecs;
2060 unsigned int glob_sta = 0;
2061 struct snd_ac97_bus_ops *ops;
2062 static struct snd_ac97_bus_ops standard_bus_ops = {
2063 .write = snd_intel8x0_codec_write,
2064 .read = snd_intel8x0_codec_read,
2066 static struct snd_ac97_bus_ops ali_bus_ops = {
2067 .write = snd_intel8x0_ali_codec_write,
2068 .read = snd_intel8x0_ali_codec_read,
2071 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2072 if (!spdif_aclink) {
2073 switch (chip->device_type) {
2075 chip->spdif_idx = NVD_SPBAR;
2078 chip->spdif_idx = ALID_AC97SPDIFOUT;
2080 case DEVICE_INTEL_ICH4:
2081 chip->spdif_idx = ICHD_SPBAR;
2086 chip->in_ac97_init = 1;
2088 memset(&ac97, 0, sizeof(ac97));
2089 ac97.private_data = chip;
2090 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2091 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2093 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2094 if (chip->device_type != DEVICE_ALI) {
2095 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2096 ops = &standard_bus_ops;
2097 chip->in_sdin_init = 1;
2099 for (i = 0; i < chip->max_codecs; i++) {
2100 if (! (glob_sta & chip->codec_bit[i]))
2102 if (chip->device_type == DEVICE_INTEL_ICH4) {
2103 snd_intel8x0_codec_read_test(chip, codecs);
2104 chip->ac97_sdin[codecs] =
2105 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2106 snd_assert(chip->ac97_sdin[codecs] < 3,
2107 chip->ac97_sdin[codecs] = 0);
2109 chip->ac97_sdin[codecs] = i;
2112 chip->in_sdin_init = 0;
2118 /* detect the secondary codec */
2119 for (i = 0; i < 100; i++) {
2120 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2125 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2129 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2131 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2132 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2133 pbus->clock = ac97_clock;
2134 /* FIXME: my test board doesn't work well with VRA... */
2135 if (chip->device_type == DEVICE_ALI)
2139 chip->ac97_bus = pbus;
2140 chip->ncodecs = codecs;
2142 ac97.pci = chip->pci;
2143 for (i = 0; i < codecs; i++) {
2145 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2147 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2153 /* tune up the primary codec */
2154 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2155 /* enable separate SDINs for ICH4 */
2156 if (chip->device_type == DEVICE_INTEL_ICH4)
2158 /* find the available PCM streams */
2159 i = ARRAY_SIZE(ac97_pcm_defs);
2160 if (chip->device_type != DEVICE_INTEL_ICH4)
2161 i -= 2; /* do not allocate PCM2IN and MIC2 */
2162 if (chip->spdif_idx < 0)
2163 i--; /* do not allocate S/PDIF */
2164 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2167 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2168 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2169 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2170 if (chip->spdif_idx >= 0)
2171 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2172 if (chip->device_type == DEVICE_INTEL_ICH4) {
2173 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2174 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2176 /* enable separate SDINs for ICH4 */
2177 if (chip->device_type == DEVICE_INTEL_ICH4) {
2178 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2179 u8 tmp = igetbyte(chip, ICHREG(SDM));
2180 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2182 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2183 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2184 for (i = 1; i < 4; i++) {
2185 if (pcm->r[0].codec[i]) {
2186 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2191 tmp &= ~ICH_SE; /* steer disable */
2193 iputbyte(chip, ICHREG(SDM), tmp);
2195 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2197 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2200 if (pbus->pcms[0].r[1].rslots[0]) {
2203 if (chip->device_type == DEVICE_INTEL_ICH4) {
2204 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2207 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2209 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2211 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2212 /* use slot 10/11 for SPDIF */
2214 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2215 val |= ICH_PCM_SPDIF_1011;
2216 iputdword(chip, ICHREG(GLOB_CNT), val);
2217 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2219 chip->in_ac97_init = 0;
2223 /* clear the cold-reset bit for the next chance */
2224 if (chip->device_type != DEVICE_ALI)
2225 iputdword(chip, ICHREG(GLOB_CNT),
2226 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2235 static void do_ali_reset(struct intel8x0 *chip)
2237 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2238 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2239 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2240 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2241 iputdword(chip, ICHREG(ALI_INTERFACECR),
2242 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2243 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2244 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2247 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2249 unsigned long end_time;
2250 unsigned int cnt, status, nstatus;
2252 /* put logic to right state */
2253 /* first clear status bits */
2254 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2255 if (chip->device_type == DEVICE_NFORCE)
2256 status |= ICH_NVSPINT;
2257 cnt = igetdword(chip, ICHREG(GLOB_STA));
2258 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2260 /* ACLink on, 2 channels */
2261 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2262 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2263 #ifdef CONFIG_SND_AC97_POWER_SAVE
2264 /* do cold reset - the full ac97 powerdown may leave the controller
2265 * in a warm state but actually it cannot communicate with the codec.
2267 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2268 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2270 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2273 /* finish cold or do warm reset */
2274 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2275 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2276 end_time = (jiffies + (HZ / 4)) + 1;
2278 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2280 schedule_timeout_uninterruptible(1);
2281 } while (time_after_eq(end_time, jiffies));
2282 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2283 igetdword(chip, ICHREG(GLOB_CNT)));
2289 /* wait for any codec ready status.
2290 * Once it becomes ready it should remain ready
2291 * as long as we do not disable the ac97 link.
2293 end_time = jiffies + HZ;
2295 status = igetdword(chip, ICHREG(GLOB_STA)) &
2296 chip->codec_isr_bits;
2299 schedule_timeout_uninterruptible(1);
2300 } while (time_after_eq(end_time, jiffies));
2302 /* no codec is found */
2303 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2304 igetdword(chip, ICHREG(GLOB_STA)));
2308 /* wait for other codecs ready status. */
2309 end_time = jiffies + HZ / 4;
2310 while (status != chip->codec_isr_bits &&
2311 time_after_eq(end_time, jiffies)) {
2312 schedule_timeout_uninterruptible(1);
2313 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2314 chip->codec_isr_bits;
2321 for (i = 0; i < chip->ncodecs; i++)
2323 status |= chip->codec_bit[chip->ac97_sdin[i]];
2324 /* wait until all the probed codecs are ready */
2325 end_time = jiffies + HZ;
2327 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2328 chip->codec_isr_bits;
2329 if (status == nstatus)
2331 schedule_timeout_uninterruptible(1);
2332 } while (time_after_eq(end_time, jiffies));
2335 if (chip->device_type == DEVICE_SIS) {
2336 /* unmute the output on SIS7012 */
2337 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2339 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2340 /* enable SPDIF interrupt */
2342 pci_read_config_dword(chip->pci, 0x4c, &val);
2344 pci_write_config_dword(chip->pci, 0x4c, val);
2349 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2354 reg = igetdword(chip, ICHREG(ALI_SCR));
2355 if ((reg & 2) == 0) /* Cold required */
2358 reg |= 1; /* Warm */
2359 reg &= ~0x80000000; /* ACLink on */
2360 iputdword(chip, ICHREG(ALI_SCR), reg);
2362 for (i = 0; i < HZ / 2; i++) {
2363 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2365 schedule_timeout_uninterruptible(1);
2367 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2372 for (i = 0; i < HZ / 2; i++) {
2373 reg = igetdword(chip, ICHREG(ALI_RTSR));
2374 if (reg & 0x80) /* primary codec */
2376 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2377 schedule_timeout_uninterruptible(1);
2384 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2386 unsigned int i, timeout;
2389 if (chip->device_type != DEVICE_ALI) {
2390 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2392 iagetword(chip, 0); /* clear semaphore flag */
2394 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2398 /* disable interrupts */
2399 for (i = 0; i < chip->bdbars_count; i++)
2400 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2401 /* reset channels */
2402 for (i = 0; i < chip->bdbars_count; i++)
2403 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2404 for (i = 0; i < chip->bdbars_count; i++) {
2406 while (--timeout != 0) {
2407 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2411 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2413 /* initialize Buffer Descriptor Lists */
2414 for (i = 0; i < chip->bdbars_count; i++)
2415 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2416 chip->ichd[i].bdbar_addr);
2420 static int snd_intel8x0_free(struct intel8x0 *chip)
2426 /* disable interrupts */
2427 for (i = 0; i < chip->bdbars_count; i++)
2428 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2429 /* reset channels */
2430 for (i = 0; i < chip->bdbars_count; i++)
2431 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2432 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2433 /* stop the spdif interrupt */
2435 pci_read_config_dword(chip->pci, 0x4c, &val);
2437 pci_write_config_dword(chip->pci, 0x4c, val);
2440 synchronize_irq(chip->irq);
2443 free_irq(chip->irq, chip);
2444 if (chip->bdbars.area) {
2445 if (chip->fix_nocache)
2446 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2447 snd_dma_free_pages(&chip->bdbars);
2450 pci_iounmap(chip->pci, chip->addr);
2452 pci_iounmap(chip->pci, chip->bmaddr);
2453 pci_release_regions(chip->pci);
2454 pci_disable_device(chip->pci);
2463 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2465 struct snd_card *card = pci_get_drvdata(pci);
2466 struct intel8x0 *chip = card->private_data;
2469 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2470 for (i = 0; i < chip->pcm_devs; i++)
2471 snd_pcm_suspend_all(chip->pcm[i]);
2473 if (chip->fix_nocache) {
2474 for (i = 0; i < chip->bdbars_count; i++) {
2475 struct ichdev *ichdev = &chip->ichd[i];
2476 if (ichdev->substream && ichdev->page_attr_changed) {
2477 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2478 if (runtime->dma_area)
2479 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2483 for (i = 0; i < chip->ncodecs; i++)
2484 snd_ac97_suspend(chip->ac97[i]);
2485 if (chip->device_type == DEVICE_INTEL_ICH4)
2486 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2488 if (chip->irq >= 0) {
2489 synchronize_irq(chip->irq);
2490 free_irq(chip->irq, chip);
2493 pci_disable_device(pci);
2494 pci_save_state(pci);
2495 /* The call below may disable built-in speaker on some laptops
2496 * after S2RAM. So, don't touch it.
2498 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2502 static int intel8x0_resume(struct pci_dev *pci)
2504 struct snd_card *card = pci_get_drvdata(pci);
2505 struct intel8x0 *chip = card->private_data;
2508 pci_set_power_state(pci, PCI_D0);
2509 pci_restore_state(pci);
2510 if (pci_enable_device(pci) < 0) {
2511 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2512 "disabling device\n");
2513 snd_card_disconnect(card);
2516 pci_set_master(pci);
2517 snd_intel8x0_chip_init(chip, 0);
2518 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2519 IRQF_SHARED, card->shortname, chip)) {
2520 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2521 "disabling device\n", pci->irq);
2522 snd_card_disconnect(card);
2525 chip->irq = pci->irq;
2526 synchronize_irq(chip->irq);
2528 /* re-initialize mixer stuff */
2529 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2530 /* enable separate SDINs for ICH4 */
2531 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2532 /* use slot 10/11 for SPDIF */
2533 iputdword(chip, ICHREG(GLOB_CNT),
2534 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2535 ICH_PCM_SPDIF_1011);
2538 /* refill nocache */
2539 if (chip->fix_nocache)
2540 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2542 for (i = 0; i < chip->ncodecs; i++)
2543 snd_ac97_resume(chip->ac97[i]);
2545 /* refill nocache */
2546 if (chip->fix_nocache) {
2547 for (i = 0; i < chip->bdbars_count; i++) {
2548 struct ichdev *ichdev = &chip->ichd[i];
2549 if (ichdev->substream && ichdev->page_attr_changed) {
2550 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2551 if (runtime->dma_area)
2552 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2558 for (i = 0; i < chip->bdbars_count; i++) {
2559 struct ichdev *ichdev = &chip->ichd[i];
2560 unsigned long port = ichdev->reg_offset;
2561 if (! ichdev->substream || ! ichdev->suspended)
2563 if (ichdev->ichd == ICHD_PCMOUT)
2564 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2565 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2566 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2567 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2568 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2571 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2574 #endif /* CONFIG_PM */
2576 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2578 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2580 struct snd_pcm_substream *subs;
2581 struct ichdev *ichdev;
2583 unsigned long pos, t;
2584 struct timeval start_time, stop_time;
2586 if (chip->ac97_bus->clock != 48000)
2587 return; /* specified in module option */
2589 subs = chip->pcm[0]->streams[0].substream;
2590 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2591 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2594 ichdev = &chip->ichd[ICHD_PCMOUT];
2595 ichdev->physbuf = subs->dma_buffer.addr;
2596 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2597 ichdev->substream = NULL; /* don't process interrupts */
2600 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2601 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2604 snd_intel8x0_setup_periods(chip, ichdev);
2605 port = ichdev->reg_offset;
2606 spin_lock_irq(&chip->reg_lock);
2607 chip->in_measurement = 1;
2609 if (chip->device_type != DEVICE_ALI)
2610 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2612 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2613 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2615 do_gettimeofday(&start_time);
2616 spin_unlock_irq(&chip->reg_lock);
2618 spin_lock_irq(&chip->reg_lock);
2619 /* check the position */
2620 pos = ichdev->fragsize1;
2621 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2622 pos += ichdev->position;
2623 chip->in_measurement = 0;
2624 do_gettimeofday(&stop_time);
2626 if (chip->device_type == DEVICE_ALI) {
2627 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2628 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2629 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2632 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2633 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2636 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2637 spin_unlock_irq(&chip->reg_lock);
2639 t = stop_time.tv_sec - start_time.tv_sec;
2641 t += stop_time.tv_usec - start_time.tv_usec;
2642 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2644 snd_printk(KERN_ERR "?? calculation error..\n");
2647 pos = (pos / 4) * 1000;
2648 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2649 if (pos < 40000 || pos >= 60000)
2650 /* abnormal value. hw problem? */
2651 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2652 else if (pos < 47500 || pos > 48500)
2653 /* not 48000Hz, tuning the clock.. */
2654 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2655 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2656 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2659 #ifdef CONFIG_PROC_FS
2660 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2661 struct snd_info_buffer *buffer)
2663 struct intel8x0 *chip = entry->private_data;
2666 snd_iprintf(buffer, "Intel8x0\n\n");
2667 if (chip->device_type == DEVICE_ALI)
2669 tmp = igetdword(chip, ICHREG(GLOB_STA));
2670 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2671 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2672 if (chip->device_type == DEVICE_INTEL_ICH4)
2673 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2674 snd_iprintf(buffer, "AC'97 codecs ready :");
2675 if (tmp & chip->codec_isr_bits) {
2677 static const char *codecs[3] = {
2678 "primary", "secondary", "tertiary"
2680 for (i = 0; i < chip->max_codecs; i++)
2681 if (tmp & chip->codec_bit[i])
2682 snd_iprintf(buffer, " %s", codecs[i]);
2684 snd_iprintf(buffer, " none");
2685 snd_iprintf(buffer, "\n");
2686 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2687 chip->device_type == DEVICE_SIS)
2688 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2691 chip->ac97_sdin[2]);
2694 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2696 struct snd_info_entry *entry;
2698 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2699 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2702 #define snd_intel8x0_proc_init(x)
2705 static int snd_intel8x0_dev_free(struct snd_device *device)
2707 struct intel8x0 *chip = device->device_data;
2708 return snd_intel8x0_free(chip);
2711 struct ich_reg_info {
2712 unsigned int int_sta_mask;
2713 unsigned int offset;
2716 static unsigned int ich_codec_bits[3] = {
2717 ICH_PCR, ICH_SCR, ICH_TCR
2719 static unsigned int sis_codec_bits[3] = {
2720 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2723 static int __devinit snd_intel8x0_create(struct snd_card *card,
2724 struct pci_dev *pci,
2725 unsigned long device_type,
2726 struct intel8x0 ** r_intel8x0)
2728 struct intel8x0 *chip;
2731 unsigned int int_sta_masks;
2732 struct ichdev *ichdev;
2733 static struct snd_device_ops ops = {
2734 .dev_free = snd_intel8x0_dev_free,
2737 static unsigned int bdbars[] = {
2738 3, /* DEVICE_INTEL */
2739 6, /* DEVICE_INTEL_ICH4 */
2742 4, /* DEVICE_NFORCE */
2744 static struct ich_reg_info intel_regs[6] = {
2746 { ICH_POINT, 0x10 },
2747 { ICH_MCINT, 0x20 },
2748 { ICH_M2INT, 0x40 },
2749 { ICH_P2INT, 0x50 },
2750 { ICH_SPINT, 0x60 },
2752 static struct ich_reg_info nforce_regs[4] = {
2754 { ICH_POINT, 0x10 },
2755 { ICH_MCINT, 0x20 },
2756 { ICH_NVSPINT, 0x70 },
2758 static struct ich_reg_info ali_regs[6] = {
2759 { ALI_INT_PCMIN, 0x40 },
2760 { ALI_INT_PCMOUT, 0x50 },
2761 { ALI_INT_MICIN, 0x60 },
2762 { ALI_INT_CODECSPDIFOUT, 0x70 },
2763 { ALI_INT_SPDIFIN, 0xa0 },
2764 { ALI_INT_SPDIFOUT, 0xb0 },
2766 struct ich_reg_info *tbl;
2770 if ((err = pci_enable_device(pci)) < 0)
2773 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2775 pci_disable_device(pci);
2778 spin_lock_init(&chip->reg_lock);
2779 chip->device_type = device_type;
2784 /* module parameters */
2785 chip->buggy_irq = buggy_irq;
2786 chip->buggy_semaphore = buggy_semaphore;
2790 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2791 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2792 chip->fix_nocache = 1; /* enable workaround */
2794 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2796 pci_disable_device(pci);
2800 if (device_type == DEVICE_ALI) {
2801 /* ALI5455 has no ac97 region */
2802 chip->bmaddr = pci_iomap(pci, 0, 0);
2806 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2807 chip->addr = pci_iomap(pci, 2, 0);
2809 chip->addr = pci_iomap(pci, 0, 0);
2811 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2812 snd_intel8x0_free(chip);
2815 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2816 chip->bmaddr = pci_iomap(pci, 3, 0);
2818 chip->bmaddr = pci_iomap(pci, 1, 0);
2819 if (!chip->bmaddr) {
2820 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2821 snd_intel8x0_free(chip);
2826 chip->bdbars_count = bdbars[device_type];
2828 /* initialize offsets */
2829 switch (device_type) {
2840 for (i = 0; i < chip->bdbars_count; i++) {
2841 ichdev = &chip->ichd[i];
2843 ichdev->reg_offset = tbl[i].offset;
2844 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2845 if (device_type == DEVICE_SIS) {
2846 /* SiS 7012 swaps the registers */
2847 ichdev->roff_sr = ICH_REG_OFF_PICB;
2848 ichdev->roff_picb = ICH_REG_OFF_SR;
2850 ichdev->roff_sr = ICH_REG_OFF_SR;
2851 ichdev->roff_picb = ICH_REG_OFF_PICB;
2853 if (device_type == DEVICE_ALI)
2854 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2855 /* SIS7012 handles the pcm data in bytes, others are in samples */
2856 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2859 /* allocate buffer descriptor lists */
2860 /* the start of each lists must be aligned to 8 bytes */
2861 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2862 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2863 &chip->bdbars) < 0) {
2864 snd_intel8x0_free(chip);
2865 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2868 /* tables must be aligned to 8 bytes here, but the kernel pages
2869 are much bigger, so we don't care (on i386) */
2870 /* workaround for 440MX */
2871 if (chip->fix_nocache)
2872 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2874 for (i = 0; i < chip->bdbars_count; i++) {
2875 ichdev = &chip->ichd[i];
2876 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2877 (i * ICH_MAX_FRAGS * 2);
2878 ichdev->bdbar_addr = chip->bdbars.addr +
2879 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2880 int_sta_masks |= ichdev->int_sta_mask;
2882 chip->int_sta_reg = device_type == DEVICE_ALI ?
2883 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2884 chip->int_sta_mask = int_sta_masks;
2886 pci_set_master(pci);
2888 switch(chip->device_type) {
2889 case DEVICE_INTEL_ICH4:
2890 /* ICH4 can have three codecs */
2891 chip->max_codecs = 3;
2892 chip->codec_bit = ich_codec_bits;
2893 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2896 /* recent SIS7012 can have three codecs */
2897 chip->max_codecs = 3;
2898 chip->codec_bit = sis_codec_bits;
2899 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
2902 /* others up to two codecs */
2903 chip->max_codecs = 2;
2904 chip->codec_bit = ich_codec_bits;
2905 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
2908 for (i = 0; i < chip->max_codecs; i++)
2909 chip->codec_isr_bits |= chip->codec_bit[i];
2911 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2912 snd_intel8x0_free(chip);
2916 /* request irq after initializaing int_sta_mask, etc */
2917 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2918 IRQF_SHARED, card->shortname, chip)) {
2919 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2920 snd_intel8x0_free(chip);
2923 chip->irq = pci->irq;
2925 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2926 snd_intel8x0_free(chip);
2930 snd_card_set_dev(card, &pci->dev);
2936 static struct shortname_table {
2939 } shortnames[] __devinitdata = {
2940 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2941 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2942 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
2943 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2944 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2945 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2946 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
2947 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2948 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2949 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2950 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2951 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2952 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
2953 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2954 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2955 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2956 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2957 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2958 { 0x003a, "NVidia MCP04" },
2959 { 0x746d, "AMD AMD8111" },
2960 { 0x7445, "AMD AMD768" },
2961 { 0x5455, "ALi M5455" },
2965 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
2966 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
2970 /* look up white/black list for SPDIF over ac-link */
2971 static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
2973 const struct snd_pci_quirk *w;
2975 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
2978 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
2979 "AC-Link for %s\n", w->name);
2981 snd_printdd(KERN_INFO "intel8x0: Using integrated "
2982 "SPDIF DMA for %s\n", w->name);
2988 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2989 const struct pci_device_id *pci_id)
2991 struct snd_card *card;
2992 struct intel8x0 *chip;
2994 struct shortname_table *name;
2996 card = snd_card_new(index, id, THIS_MODULE, 0);
3000 if (spdif_aclink < 0)
3001 spdif_aclink = check_default_spdif_aclink(pci);
3003 strcpy(card->driver, "ICH");
3004 if (!spdif_aclink) {
3005 switch (pci_id->driver_data) {
3007 strcpy(card->driver, "NFORCE");
3009 case DEVICE_INTEL_ICH4:
3010 strcpy(card->driver, "ICH4");
3014 strcpy(card->shortname, "Intel ICH");
3015 for (name = shortnames; name->id; name++) {
3016 if (pci->device == name->id) {
3017 strcpy(card->shortname, name->s);
3022 if (buggy_irq < 0) {
3023 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3024 * Needs to return IRQ_HANDLED for unknown irqs.
3026 if (pci_id->driver_data == DEVICE_NFORCE)
3032 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3034 snd_card_free(card);
3037 card->private_data = chip;
3039 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3040 snd_card_free(card);
3043 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3044 snd_card_free(card);
3048 snd_intel8x0_proc_init(chip);
3050 snprintf(card->longname, sizeof(card->longname),
3051 "%s with %s at irq %i", card->shortname,
3052 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3055 intel8x0_measure_ac97_clock(chip);
3057 if ((err = snd_card_register(card)) < 0) {
3058 snd_card_free(card);
3061 pci_set_drvdata(pci, card);
3065 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3067 snd_card_free(pci_get_drvdata(pci));
3068 pci_set_drvdata(pci, NULL);
3071 static struct pci_driver driver = {
3072 .name = "Intel ICH",
3073 .id_table = snd_intel8x0_ids,
3074 .probe = snd_intel8x0_probe,
3075 .remove = __devexit_p(snd_intel8x0_remove),
3077 .suspend = intel8x0_suspend,
3078 .resume = intel8x0_resume,
3083 static int __init alsa_card_intel8x0_init(void)
3085 return pci_register_driver(&driver);
3088 static void __exit alsa_card_intel8x0_exit(void)
3090 pci_unregister_driver(&driver);
3093 module_init(alsa_card_intel8x0_init)
3094 module_exit(alsa_card_intel8x0_exit)