2 * ALSA driver for ICEnsemble ICE1724 (Envy24)
4 * Lowlevel functions for Terratec PHASE 22
6 * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * Audio controller: VIA Envy24HT-S (slightly trimmed down version of Envy24HT)
26 * Analog chip: AK4524 (partially via Philip's 74HCT125)
27 * Digital receiver: CS8414-CS (not supported in this release)
29 * Envy connects to AK4524
30 * - CS directly from GPIO 10
31 * - CCLK via 74HCT125's gate #4 from GPIO 4
32 * - CDTI via 74HCT125's gate #2 from GPIO 5
33 * CDTI may be completely blocked by 74HCT125's gate #1 controlled by GPIO 3
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/init.h>
40 #include <linux/slab.h>
41 #include <linux/mutex.h>
43 #include <sound/core.h>
48 #include <sound/tlv.h>
50 /* WM8770 registers */
51 #define WM_DAC_ATTEN 0x00 /* DAC1-8 analog attenuation */
52 #define WM_DAC_MASTER_ATTEN 0x08 /* DAC master analog attenuation */
53 #define WM_DAC_DIG_ATTEN 0x09 /* DAC1-8 digital attenuation */
54 #define WM_DAC_DIG_MASTER_ATTEN 0x11 /* DAC master digital attenuation */
55 #define WM_PHASE_SWAP 0x12 /* DAC phase */
56 #define WM_DAC_CTRL1 0x13 /* DAC control bits */
57 #define WM_MUTE 0x14 /* mute controls */
58 #define WM_DAC_CTRL2 0x15 /* de-emphasis and zefo-flag */
59 #define WM_INT_CTRL 0x16 /* interface control */
60 #define WM_MASTER 0x17 /* master clock and mode */
61 #define WM_POWERDOWN 0x18 /* power-down controls */
62 #define WM_ADC_GAIN 0x19 /* ADC gain L(19)/R(1a) */
63 #define WM_ADC_MUX 0x1b /* input MUX */
64 #define WM_OUT_MUX1 0x1c /* output MUX */
65 #define WM_OUT_MUX2 0x1e /* output MUX */
66 #define WM_RESET 0x1f /* software reset */
70 * Logarithmic volume values for WM8770
71 * Computed as 20 * Log10(255 / x)
73 static const unsigned char wm_vol[256] = {
74 127, 48, 42, 39, 36, 34, 33, 31, 30, 29, 28, 27, 27, 26, 25, 25, 24, 24, 23,
75 23, 22, 22, 21, 21, 21, 20, 20, 20, 19, 19, 19, 18, 18, 18, 18, 17, 17, 17,
76 17, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 13, 13, 13,
77 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11,
78 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8,
79 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6,
80 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
81 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3,
82 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
83 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
84 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
88 #define WM_VOL_MAX (sizeof(wm_vol) - 1)
89 #define WM_VOL_MUTE 0x8000
91 static struct snd_akm4xxx akm_phase22 __devinitdata = {
97 static struct snd_ak4xxx_private akm_phase22_priv __devinitdata = {
109 static int __devinit phase22_init(struct snd_ice1712 *ice)
111 struct snd_akm4xxx *ak;
114 // Configure DAC/ADC description for generic part of ice1724
115 switch (ice->eeprom.subvendor) {
116 case VT1724_SUBDEVICE_PHASE22:
117 ice->num_total_dacs = 2;
118 ice->num_total_adcs = 2;
119 ice->vt1720 = 1; // Envy24HT-S have 16 bit wide GPIO
126 // Initialize analog chips
127 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
131 switch (ice->eeprom.subvendor) {
132 case VT1724_SUBDEVICE_PHASE22:
133 if ((err = snd_ice1712_akm4xxx_init(ak, &akm_phase22, &akm_phase22_priv, ice)) < 0)
141 static int __devinit phase22_add_controls(struct snd_ice1712 *ice)
145 switch (ice->eeprom.subvendor) {
146 case VT1724_SUBDEVICE_PHASE22:
147 err = snd_ice1712_akm4xxx_build_controls(ice);
154 static unsigned char phase22_eeprom[] __devinitdata = {
155 [ICE_EEP2_SYSCONF] = 0x00, /* 1xADC, 1xDACs */
156 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
157 [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit */
158 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
159 [ICE_EEP2_GPIO_DIR] = 0xff,
160 [ICE_EEP2_GPIO_DIR1] = 0xff,
161 [ICE_EEP2_GPIO_DIR2] = 0xff,
162 [ICE_EEP2_GPIO_MASK] = 0x00,
163 [ICE_EEP2_GPIO_MASK1] = 0x00,
164 [ICE_EEP2_GPIO_MASK2] = 0x00,
165 [ICE_EEP2_GPIO_STATE] = 0x00,
166 [ICE_EEP2_GPIO_STATE1] = 0x00,
167 [ICE_EEP2_GPIO_STATE2] = 0x00,
170 static unsigned char phase28_eeprom[] __devinitdata = {
171 [ICE_EEP2_SYSCONF] = 0x0b, /* clock 512, spdif-in/ADC, 4DACs */
172 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
173 [ICE_EEP2_I2S] = 0xfc, /* vol, 96k, 24bit, 192k */
174 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
175 [ICE_EEP2_GPIO_DIR] = 0xff,
176 [ICE_EEP2_GPIO_DIR1] = 0xff,
177 [ICE_EEP2_GPIO_DIR2] = 0x5f,
178 [ICE_EEP2_GPIO_MASK] = 0x00,
179 [ICE_EEP2_GPIO_MASK1] = 0x00,
180 [ICE_EEP2_GPIO_MASK2] = 0x00,
181 [ICE_EEP2_GPIO_STATE] = 0x00,
182 [ICE_EEP2_GPIO_STATE1] = 0x00,
183 [ICE_EEP2_GPIO_STATE2] = 0x00,
187 * write data in the SPI mode
189 static void phase28_spi_write(struct snd_ice1712 *ice, unsigned int cs, unsigned int data, int bits)
194 tmp = snd_ice1712_gpio_read(ice);
196 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RW|PHASE28_SPI_MOSI|PHASE28_SPI_CLK|
198 tmp |= PHASE28_WM_RW;
200 snd_ice1712_gpio_write(ice, tmp);
203 for (i = bits - 1; i >= 0; i--) {
204 tmp &= ~PHASE28_SPI_CLK;
205 snd_ice1712_gpio_write(ice, tmp);
208 tmp |= PHASE28_SPI_MOSI;
210 tmp &= ~PHASE28_SPI_MOSI;
211 snd_ice1712_gpio_write(ice, tmp);
213 tmp |= PHASE28_SPI_CLK;
214 snd_ice1712_gpio_write(ice, tmp);
218 tmp &= ~PHASE28_SPI_CLK;
220 snd_ice1712_gpio_write(ice, tmp);
222 tmp |= PHASE28_SPI_CLK;
223 snd_ice1712_gpio_write(ice, tmp);
228 * get the current register value of WM codec
230 static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
233 return ((unsigned short)ice->akm[0].images[reg] << 8) |
234 ice->akm[0].images[reg + 1];
238 * set the register value of WM codec
240 static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
242 phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16);
246 * set the register value of WM codec and remember it
248 static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
250 wm_put_nocache(ice, reg, val);
252 ice->akm[0].images[reg] = val >> 8;
253 ice->akm[0].images[reg + 1] = val;
256 static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index, unsigned short vol, unsigned short master)
260 if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
263 nvol = 127 - wm_vol[(((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 127) & WM_VOL_MAX];
265 wm_put(ice, index, nvol);
266 wm_put_nocache(ice, index, 0x180 | nvol);
272 #define wm_pcm_mute_info snd_ctl_boolean_mono_info
274 static int wm_pcm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
276 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
278 mutex_lock(&ice->gpio_mutex);
279 ucontrol->value.integer.value[0] = (wm_get(ice, WM_MUTE) & 0x10) ? 0 : 1;
280 mutex_unlock(&ice->gpio_mutex);
284 static int wm_pcm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
286 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
287 unsigned short nval, oval;
290 snd_ice1712_save_gpio_status(ice);
291 oval = wm_get(ice, WM_MUTE);
292 nval = (oval & ~0x10) | (ucontrol->value.integer.value[0] ? 0 : 0x10);
293 if ((change = (nval != oval)))
294 wm_put(ice, WM_MUTE, nval);
295 snd_ice1712_restore_gpio_status(ice);
301 * Master volume attenuation mixer control
303 static int wm_master_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
305 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
307 uinfo->value.integer.min = 0;
308 uinfo->value.integer.max = WM_VOL_MAX;
312 static int wm_master_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
314 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
317 ucontrol->value.integer.value[i] = ice->spec.phase28.master[i] & ~WM_VOL_MUTE;
321 static int wm_master_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
323 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
326 snd_ice1712_save_gpio_status(ice);
327 for (ch = 0; ch < 2; ch++) {
328 unsigned int vol = ucontrol->value.integer.value[ch];
329 if (vol > WM_VOL_MAX)
331 vol |= ice->spec.phase28.master[ch] & WM_VOL_MUTE;
332 if (vol != ice->spec.phase28.master[ch]) {
334 ice->spec.phase28.master[ch] = vol;
335 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
336 wm_set_vol(ice, WM_DAC_ATTEN + dac + ch,
337 ice->spec.phase28.vol[dac + ch],
338 ice->spec.phase28.master[ch]);
342 snd_ice1712_restore_gpio_status(ice);
346 static int __devinit phase28_init(struct snd_ice1712 *ice)
348 static const unsigned short wm_inits_phase28[] = {
349 /* These come first to reduce init pop noise */
350 0x1b, 0x044, /* ADC Mux (AC'97 source) */
351 0x1c, 0x00B, /* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
352 0x1d, 0x009, /* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
354 0x18, 0x000, /* All power-up */
356 0x16, 0x122, /* I2S, normal polarity, 24bit */
357 0x17, 0x022, /* 256fs, slave mode */
358 0x00, 0, /* DAC1 analog mute */
359 0x01, 0, /* DAC2 analog mute */
360 0x02, 0, /* DAC3 analog mute */
361 0x03, 0, /* DAC4 analog mute */
362 0x04, 0, /* DAC5 analog mute */
363 0x05, 0, /* DAC6 analog mute */
364 0x06, 0, /* DAC7 analog mute */
365 0x07, 0, /* DAC8 analog mute */
366 0x08, 0x100, /* master analog mute */
367 0x09, 0xff, /* DAC1 digital full */
368 0x0a, 0xff, /* DAC2 digital full */
369 0x0b, 0xff, /* DAC3 digital full */
370 0x0c, 0xff, /* DAC4 digital full */
371 0x0d, 0xff, /* DAC5 digital full */
372 0x0e, 0xff, /* DAC6 digital full */
373 0x0f, 0xff, /* DAC7 digital full */
374 0x10, 0xff, /* DAC8 digital full */
375 0x11, 0x1ff, /* master digital full */
376 0x12, 0x000, /* phase normal */
377 0x13, 0x090, /* unmute DAC L/R */
378 0x14, 0x000, /* all unmute */
379 0x15, 0x000, /* no deemphasis, no ZFLG */
380 0x19, 0x000, /* -12dB ADC/L */
381 0x1a, 0x000, /* -12dB ADC/R */
386 struct snd_akm4xxx *ak;
387 const unsigned short *p;
390 ice->num_total_dacs = 8;
391 ice->num_total_adcs = 2;
393 // Initialize analog chips
394 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
399 snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for the time being */
401 /* reset the wm codec as the SPI mode */
402 snd_ice1712_save_gpio_status(ice);
403 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|PHASE28_HP_SEL));
405 tmp = snd_ice1712_gpio_read(ice);
406 tmp &= ~PHASE28_WM_RESET;
407 snd_ice1712_gpio_write(ice, tmp);
409 tmp |= PHASE28_WM_CS;
410 snd_ice1712_gpio_write(ice, tmp);
412 tmp |= PHASE28_WM_RESET;
413 snd_ice1712_gpio_write(ice, tmp);
416 p = wm_inits_phase28;
417 for (; *p != (unsigned short)-1; p += 2)
418 wm_put(ice, p[0], p[1]);
420 snd_ice1712_restore_gpio_status(ice);
422 ice->spec.phase28.master[0] = WM_VOL_MUTE;
423 ice->spec.phase28.master[1] = WM_VOL_MUTE;
424 for (i = 0; i < ice->num_total_dacs; i++) {
425 ice->spec.phase28.vol[i] = WM_VOL_MUTE;
426 wm_set_vol(ice, i, ice->spec.phase28.vol[i], ice->spec.phase28.master[i % 2]);
433 * DAC volume attenuation mixer control
435 static int wm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
437 int voices = kcontrol->private_value >> 8;
438 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
439 uinfo->count = voices;
440 uinfo->value.integer.min = 0; /* mute (-101dB) */
441 uinfo->value.integer.max = 0x7F; /* 0dB */
445 static int wm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
447 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
450 voices = kcontrol->private_value >> 8;
451 ofs = kcontrol->private_value & 0xff;
452 for (i = 0; i < voices; i++)
453 ucontrol->value.integer.value[i] = ice->spec.phase28.vol[ofs+i] & ~WM_VOL_MUTE;
457 static int wm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
459 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
460 int i, idx, ofs, voices;
463 voices = kcontrol->private_value >> 8;
464 ofs = kcontrol->private_value & 0xff;
465 snd_ice1712_save_gpio_status(ice);
466 for (i = 0; i < voices; i++) {
468 vol = ucontrol->value.integer.value[i];
471 vol |= ice->spec.phase28.vol[ofs+i] & WM_VOL_MUTE;
472 if (vol != ice->spec.phase28.vol[ofs+i]) {
473 ice->spec.phase28.vol[ofs+i] = vol;
474 idx = WM_DAC_ATTEN + ofs + i;
475 wm_set_vol(ice, idx, ice->spec.phase28.vol[ofs+i],
476 ice->spec.phase28.master[i]);
480 snd_ice1712_restore_gpio_status(ice);
485 * WM8770 mute control
487 static int wm_mute_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) {
488 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
489 uinfo->count = kcontrol->private_value >> 8;
490 uinfo->value.integer.min = 0;
491 uinfo->value.integer.max = 1;
495 static int wm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
497 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
500 voices = kcontrol->private_value >> 8;
501 ofs = kcontrol->private_value & 0xFF;
503 for (i = 0; i < voices; i++)
504 ucontrol->value.integer.value[i] = (ice->spec.phase28.vol[ofs+i] & WM_VOL_MUTE) ? 0 : 1;
508 static int wm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
510 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
511 int change = 0, voices, ofs, i;
513 voices = kcontrol->private_value >> 8;
514 ofs = kcontrol->private_value & 0xFF;
516 snd_ice1712_save_gpio_status(ice);
517 for (i = 0; i < voices; i++) {
518 int val = (ice->spec.phase28.vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
519 if (ucontrol->value.integer.value[i] != val) {
520 ice->spec.phase28.vol[ofs + i] &= ~WM_VOL_MUTE;
521 ice->spec.phase28.vol[ofs + i] |=
522 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
523 wm_set_vol(ice, ofs + i, ice->spec.phase28.vol[ofs + i],
524 ice->spec.phase28.master[i]);
528 snd_ice1712_restore_gpio_status(ice);
534 * WM8770 master mute control
536 #define wm_master_mute_info snd_ctl_boolean_stereo_info
538 static int wm_master_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
540 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
542 ucontrol->value.integer.value[0] = (ice->spec.phase28.master[0] & WM_VOL_MUTE) ? 0 : 1;
543 ucontrol->value.integer.value[1] = (ice->spec.phase28.master[1] & WM_VOL_MUTE) ? 0 : 1;
547 static int wm_master_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
549 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
552 snd_ice1712_save_gpio_status(ice);
553 for (i = 0; i < 2; i++) {
554 int val = (ice->spec.phase28.master[i] & WM_VOL_MUTE) ? 0 : 1;
555 if (ucontrol->value.integer.value[i] != val) {
557 ice->spec.phase28.master[i] &= ~WM_VOL_MUTE;
558 ice->spec.phase28.master[i] |=
559 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
560 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
561 wm_set_vol(ice, WM_DAC_ATTEN + dac + i,
562 ice->spec.phase28.vol[dac + i],
563 ice->spec.phase28.master[i]);
567 snd_ice1712_restore_gpio_status(ice);
572 /* digital master volume */
574 #define PCM_RES 128 /* -64dB */
575 #define PCM_MIN (PCM_0dB - PCM_RES)
576 static int wm_pcm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
578 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
580 uinfo->value.integer.min = 0; /* mute (-64dB) */
581 uinfo->value.integer.max = PCM_RES; /* 0dB */
585 static int wm_pcm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
587 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
590 mutex_lock(&ice->gpio_mutex);
591 val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
592 val = val > PCM_MIN ? (val - PCM_MIN) : 0;
593 ucontrol->value.integer.value[0] = val;
594 mutex_unlock(&ice->gpio_mutex);
598 static int wm_pcm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
600 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
601 unsigned short ovol, nvol;
604 nvol = ucontrol->value.integer.value[0];
607 snd_ice1712_save_gpio_status(ice);
608 nvol = (nvol ? (nvol + PCM_MIN) : 0) & 0xff;
609 ovol = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
611 wm_put(ice, WM_DAC_DIG_MASTER_ATTEN, nvol); /* prelatch */
612 wm_put_nocache(ice, WM_DAC_DIG_MASTER_ATTEN, nvol | 0x100); /* update */
615 snd_ice1712_restore_gpio_status(ice);
622 #define phase28_deemp_info snd_ctl_boolean_mono_info
624 static int phase28_deemp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
626 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
627 ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) == 0xf;
631 static int phase28_deemp_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
633 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
635 temp2 = temp = wm_get(ice, WM_DAC_CTRL2);
636 if (ucontrol->value.integer.value[0])
641 wm_put(ice, WM_DAC_CTRL2, temp);
650 static int phase28_oversampling_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo)
652 static char *texts[2] = { "128x", "64x" };
654 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
656 uinfo->value.enumerated.items = 2;
658 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
659 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
660 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
665 static int phase28_oversampling_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
667 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
668 ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) == 0x8;
672 static int phase28_oversampling_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
675 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
677 temp2 = temp = wm_get(ice, WM_MASTER);
679 if (ucontrol->value.enumerated.item[0])
685 wm_put(ice, WM_MASTER, temp);
691 static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
692 static const DECLARE_TLV_DB_SCALE(db_scale_wm_pcm, -6400, 50, 1);
694 static struct snd_kcontrol_new phase28_dac_controls[] __devinitdata = {
696 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
697 .name = "Master Playback Switch",
698 .info = wm_master_mute_info,
699 .get = wm_master_mute_get,
700 .put = wm_master_mute_put
703 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
704 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
705 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
706 .name = "Master Playback Volume",
707 .info = wm_master_vol_info,
708 .get = wm_master_vol_get,
709 .put = wm_master_vol_put,
710 .tlv = { .p = db_scale_wm_dac }
713 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
714 .name = "Front Playback Switch",
715 .info = wm_mute_info,
718 .private_value = (2 << 8) | 0
721 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
722 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
723 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
724 .name = "Front Playback Volume",
728 .private_value = (2 << 8) | 0,
729 .tlv = { .p = db_scale_wm_dac }
732 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
733 .name = "Rear Playback Switch",
734 .info = wm_mute_info,
737 .private_value = (2 << 8) | 2
740 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
741 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
742 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
743 .name = "Rear Playback Volume",
747 .private_value = (2 << 8) | 2,
748 .tlv = { .p = db_scale_wm_dac }
751 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
752 .name = "Center Playback Switch",
753 .info = wm_mute_info,
756 .private_value = (1 << 8) | 4
759 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
760 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
761 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
762 .name = "Center Playback Volume",
766 .private_value = (1 << 8) | 4,
767 .tlv = { .p = db_scale_wm_dac }
770 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
771 .name = "LFE Playback Switch",
772 .info = wm_mute_info,
775 .private_value = (1 << 8) | 5
778 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
779 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
780 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
781 .name = "LFE Playback Volume",
785 .private_value = (1 << 8) | 5,
786 .tlv = { .p = db_scale_wm_dac }
789 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
790 .name = "Side Playback Switch",
791 .info = wm_mute_info,
794 .private_value = (2 << 8) | 6
797 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
798 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
799 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
800 .name = "Side Playback Volume",
804 .private_value = (2 << 8) | 6,
805 .tlv = { .p = db_scale_wm_dac }
809 static struct snd_kcontrol_new wm_controls[] __devinitdata = {
811 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
812 .name = "PCM Playback Switch",
813 .info = wm_pcm_mute_info,
814 .get = wm_pcm_mute_get,
815 .put = wm_pcm_mute_put
818 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
819 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
820 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
821 .name = "PCM Playback Volume",
822 .info = wm_pcm_vol_info,
823 .get = wm_pcm_vol_get,
824 .put = wm_pcm_vol_put,
825 .tlv = { .p = db_scale_wm_pcm }
828 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
829 .name = "DAC Deemphasis Switch",
830 .info = phase28_deemp_info,
831 .get = phase28_deemp_get,
832 .put = phase28_deemp_put
835 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
836 .name = "ADC Oversampling",
837 .info = phase28_oversampling_info,
838 .get = phase28_oversampling_get,
839 .put = phase28_oversampling_put
843 static int __devinit phase28_add_controls(struct snd_ice1712 *ice)
845 unsigned int i, counts;
848 counts = ARRAY_SIZE(phase28_dac_controls);
849 for (i = 0; i < counts; i++) {
850 err = snd_ctl_add(ice->card, snd_ctl_new1(&phase28_dac_controls[i], ice));
855 for (i = 0; i < ARRAY_SIZE(wm_controls); i++) {
856 err = snd_ctl_add(ice->card, snd_ctl_new1(&wm_controls[i], ice));
864 struct snd_ice1712_card_info snd_vt1724_phase_cards[] __devinitdata = {
866 .subvendor = VT1724_SUBDEVICE_PHASE22,
867 .name = "Terratec PHASE 22",
869 .chip_init = phase22_init,
870 .build_controls = phase22_add_controls,
871 .eeprom_size = sizeof(phase22_eeprom),
872 .eeprom_data = phase22_eeprom,
875 .subvendor = VT1724_SUBDEVICE_PHASE28,
876 .name = "Terratec PHASE 28",
878 .chip_init = phase28_init,
879 .build_controls = phase28_add_controls,
880 .eeprom_size = sizeof(phase28_eeprom),
881 .eeprom_data = phase28_eeprom,