sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <sound/core.h>
  49 #include <sound/initval.h>
  50 #include "hda_codec.h"
  51
  52
  53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  56 static char *model[SNDRV_CARDS];
  57 static int position_fix[SNDRV_CARDS];
  58 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  59 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int single_cmd;
  61 static int enable_msi;
  62
  63 module_param_array(index, int, NULL, 0444);
  64 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  65 module_param_array(id, charp, NULL, 0444);
  66 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  67 module_param_array(enable, bool, NULL, 0444);
  68 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  69 module_param_array(model, charp, NULL, 0444);
  70 MODULE_PARM_DESC(model, "Use the given board model.");
  71 module_param_array(position_fix, int, NULL, 0444);
  72 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  73                  "(0 = auto, 1 = none, 2 = POSBUF).");
  74 module_param_array(bdl_pos_adj, int, NULL, 0644);
  75 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  76 module_param_array(probe_mask, int, NULL, 0444);
  77 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  78 module_param(single_cmd, bool, 0444);
  79 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  80                  "(for debugging only).");
  81 module_param(enable_msi, int, 0444);
  82 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  83
  84 #ifdef CONFIG_SND_HDA_POWER_SAVE
  85 /* power_save option is defined in hda_codec.c */
  86
  87 /* reset the HD-audio controller in power save mode.
  88  * this may give more power-saving, but will take longer time to
  89  * wake up.
  90  */
  91 static int power_save_controller = 1;
  92 module_param(power_save_controller, bool, 0644);
  93 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  94 #endif
  95
  96 MODULE_LICENSE("GPL");
  97 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  98                          "{Intel, ICH6M},"
  99                          "{Intel, ICH7},"
 100                          "{Intel, ESB2},"
 101                          "{Intel, ICH8},"
 102                          "{Intel, ICH9},"
 103                          "{Intel, ICH10},"
 104                          "{Intel, PCH},"
 105                          "{Intel, SCH},"
 106                          "{ATI, SB450},"
 107                          "{ATI, SB600},"
 108                          "{ATI, RS600},"
 109                          "{ATI, RS690},"
 110                          "{ATI, RS780},"
 111                          "{ATI, R600},"
 112                          "{ATI, RV630},"
 113                          "{ATI, RV610},"
 114                          "{ATI, RV670},"
 115                          "{ATI, RV635},"
 116                          "{ATI, RV620},"
 117                          "{ATI, RV770},"
 118                          "{VIA, VT8251},"
 119                          "{VIA, VT8237A},"
 120                          "{SiS, SIS966},"
 121                          "{ULI, M5461}}");
 122 MODULE_DESCRIPTION("Intel HDA driver");
 123
 124 #define SFX     "hda-intel: "
 125
 126
 127 /*
 128  * registers
 129  */
 130 #define ICH6_REG_GCAP                   0x00
 131 #define ICH6_REG_VMIN                   0x02
 132 #define ICH6_REG_VMAJ                   0x03
 133 #define ICH6_REG_OUTPAY                 0x04
 134 #define ICH6_REG_INPAY                  0x06
 135 #define ICH6_REG_GCTL                   0x08
 136 #define ICH6_REG_WAKEEN                 0x0c
 137 #define ICH6_REG_STATESTS               0x0e
 138 #define ICH6_REG_GSTS                   0x10
 139 #define ICH6_REG_INTCTL                 0x20
 140 #define ICH6_REG_INTSTS                 0x24
 141 #define ICH6_REG_WALCLK                 0x30
 142 #define ICH6_REG_SYNC                   0x34
 143 #define ICH6_REG_CORBLBASE              0x40
 144 #define ICH6_REG_CORBUBASE              0x44
 145 #define ICH6_REG_CORBWP                 0x48
 146 #define ICH6_REG_CORBRP                 0x4A
 147 #define ICH6_REG_CORBCTL                0x4c
 148 #define ICH6_REG_CORBSTS                0x4d
 149 #define ICH6_REG_CORBSIZE               0x4e
 150
 151 #define ICH6_REG_RIRBLBASE              0x50
 152 #define ICH6_REG_RIRBUBASE              0x54
 153 #define ICH6_REG_RIRBWP                 0x58
 154 #define ICH6_REG_RINTCNT                0x5a
 155 #define ICH6_REG_RIRBCTL                0x5c
 156 #define ICH6_REG_RIRBSTS                0x5d
 157 #define ICH6_REG_RIRBSIZE               0x5e
 158
 159 #define ICH6_REG_IC                     0x60
 160 #define ICH6_REG_IR                     0x64
 161 #define ICH6_REG_IRS                    0x68
 162 #define   ICH6_IRS_VALID        (1<<1)
 163 #define   ICH6_IRS_BUSY         (1<<0)
 164
 165 #define ICH6_REG_DPLBASE                0x70
 166 #define ICH6_REG_DPUBASE                0x74
 167 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 168
 169 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 170 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 171
 172 /* stream register offsets from stream base */
 173 #define ICH6_REG_SD_CTL                 0x00
 174 #define ICH6_REG_SD_STS                 0x03
 175 #define ICH6_REG_SD_LPIB                0x04
 176 #define ICH6_REG_SD_CBL                 0x08
 177 #define ICH6_REG_SD_LVI                 0x0c
 178 #define ICH6_REG_SD_FIFOW               0x0e
 179 #define ICH6_REG_SD_FIFOSIZE            0x10
 180 #define ICH6_REG_SD_FORMAT              0x12
 181 #define ICH6_REG_SD_BDLPL               0x18
 182 #define ICH6_REG_SD_BDLPU               0x1c
 183
 184 /* PCI space */
 185 #define ICH6_PCIREG_TCSEL       0x44
 186
 187 /*
 188  * other constants
 189  */
 190
 191 /* max number of SDs */
 192 /* ICH, ATI and VIA have 4 playback and 4 capture */
 193 #define ICH6_NUM_CAPTURE        4
 194 #define ICH6_NUM_PLAYBACK       4
 195
 196 /* ULI has 6 playback and 5 capture */
 197 #define ULI_NUM_CAPTURE         5
 198 #define ULI_NUM_PLAYBACK        6
 199
 200 /* ATI HDMI has 1 playback and 0 capture */
 201 #define ATIHDMI_NUM_CAPTURE     0
 202 #define ATIHDMI_NUM_PLAYBACK    1
 203
 204 /* TERA has 4 playback and 3 capture */
 205 #define TERA_NUM_CAPTURE        3
 206 #define TERA_NUM_PLAYBACK       4
 207
 208 /* this number is statically defined for simplicity */
 209 #define MAX_AZX_DEV             16
 210
 211 /* max number of fragments - we may use more if allocating more pages for BDL */
 212 #define BDL_SIZE                4096
 213 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 214 #define AZX_MAX_FRAG            32
 215 /* max buffer size - no h/w limit, you can increase as you like */
 216 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 217 /* max number of PCM devics per card */
 218 #define AZX_MAX_PCMS            8
 219
 220 /* RIRB int mask: overrun[2], response[0] */
 221 #define RIRB_INT_RESPONSE       0x01
 222 #define RIRB_INT_OVERRUN        0x04
 223 #define RIRB_INT_MASK           0x05
 224
 225 /* STATESTS int mask: SD2,SD1,SD0 */
 226 #define AZX_MAX_CODECS          3
 227 #define STATESTS_INT_MASK       0x07
 228
 229 /* SD_CTL bits */
 230 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 231 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 232 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 233 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 234 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 235 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 236 #define SD_CTL_STREAM_TAG_SHIFT 20
 237
 238 /* SD_CTL and SD_STS */
 239 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 240 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 241 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 242 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 243                                  SD_INT_COMPLETE)
 244
 245 /* SD_STS */
 246 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 247
 248 /* INTCTL and INTSTS */
 249 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 250 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 251 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 252
 253 /* GCTL unsolicited response enable bit */
 254 #define ICH6_GCTL_UREN          (1<<8)
 255
 256 /* GCTL reset bit */
 257 #define ICH6_GCTL_RESET         (1<<0)
 258
 259 /* CORB/RIRB control, read/write pointer */
 260 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 261 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 262 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 263 /* below are so far hardcoded - should read registers in future */
 264 #define ICH6_MAX_CORB_ENTRIES   256
 265 #define ICH6_MAX_RIRB_ENTRIES   256
 266
 267 /* position fix mode */
 268 enum {
 269         POS_FIX_AUTO,
 270         POS_FIX_LPIB,
 271         POS_FIX_POSBUF,
 272 };
 273
 274 /* Defines for ATI HD Audio support in SB450 south bridge */
 275 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 276 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 277
 278 /* Defines for Nvidia HDA support */
 279 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 280 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 281
 282 /* Defines for Intel SCH HDA snoop control */
 283 #define INTEL_SCH_HDA_DEVC      0x78
 284 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 285
 286
 287 /*
 288  */
 289
 290 struct azx_dev {
 291         struct snd_dma_buffer bdl; /* BDL buffer */
 292         u32 *posbuf;            /* position buffer pointer */
 293
 294         unsigned int bufsize;   /* size of the play buffer in bytes */
 295         unsigned int period_bytes; /* size of the period in bytes */
 296         unsigned int frags;     /* number for period in the play buffer */
 297         unsigned int fifo_size; /* FIFO size */
 298
 299         void __iomem *sd_addr;  /* stream descriptor pointer */
 300
 301         u32 sd_int_sta_mask;    /* stream int status mask */
 302
 303         /* pcm support */
 304         struct snd_pcm_substream *substream;    /* assigned substream,
 305                                                  * set in PCM open
 306                                                  */
 307         unsigned int format_val;        /* format value to be set in the
 308                                          * controller and the codec
 309                                          */
 310         unsigned char stream_tag;       /* assigned stream */
 311         unsigned char index;            /* stream index */
 312
 313         unsigned int opened :1;
 314         unsigned int running :1;
 315         unsigned int irq_pending :1;
 316         unsigned int irq_ignore :1;
 317 };
 318
 319 /* CORB/RIRB */
 320 struct azx_rb {
 321         u32 *buf;               /* CORB/RIRB buffer
 322                                  * Each CORB entry is 4byte, RIRB is 8byte
 323                                  */
 324         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 325         /* for RIRB */
 326         unsigned short rp, wp;  /* read/write pointers */
 327         int cmds;               /* number of pending requests */
 328         u32 res;                /* last read value */
 329 };
 330
 331 struct azx {
 332         struct snd_card *card;
 333         struct pci_dev *pci;
 334         int dev_index;
 335
 336         /* chip type specific */
 337         int driver_type;
 338         int playback_streams;
 339         int playback_index_offset;
 340         int capture_streams;
 341         int capture_index_offset;
 342         int num_streams;
 343
 344         /* pci resources */
 345         unsigned long addr;
 346         void __iomem *remap_addr;
 347         int irq;
 348
 349         /* locks */
 350         spinlock_t reg_lock;
 351         struct mutex open_mutex;
 352
 353         /* streams (x num_streams) */
 354         struct azx_dev *azx_dev;
 355
 356         /* PCM */
 357         struct snd_pcm *pcm[AZX_MAX_PCMS];
 358
 359         /* HD codec */
 360         unsigned short codec_mask;
 361         struct hda_bus *bus;
 362
 363         /* CORB/RIRB */
 364         struct azx_rb corb;
 365         struct azx_rb rirb;
 366
 367         /* CORB/RIRB and position buffers */
 368         struct snd_dma_buffer rb;
 369         struct snd_dma_buffer posbuf;
 370
 371         /* flags */
 372         int position_fix;
 373         unsigned int running :1;
 374         unsigned int initialized :1;
 375         unsigned int single_cmd :1;
 376         unsigned int polling_mode :1;
 377         unsigned int msi :1;
 378         unsigned int irq_pending_warned :1;
 379
 380         /* for debugging */
 381         unsigned int last_cmd;  /* last issued command (to sync) */
 382
 383         /* for pending irqs */
 384         struct work_struct irq_pending_work;
 385 };
 386
 387 /* driver types */
 388 enum {
 389         AZX_DRIVER_ICH,
 390         AZX_DRIVER_SCH,
 391         AZX_DRIVER_ATI,
 392         AZX_DRIVER_ATIHDMI,
 393         AZX_DRIVER_VIA,
 394         AZX_DRIVER_SIS,
 395         AZX_DRIVER_ULI,
 396         AZX_DRIVER_NVIDIA,
 397         AZX_DRIVER_TERA,
 398 };
 399
 400 static char *driver_short_names[] __devinitdata = {
 401         [AZX_DRIVER_ICH] = "HDA Intel",
 402         [AZX_DRIVER_SCH] = "HDA Intel MID",
 403         [AZX_DRIVER_ATI] = "HDA ATI SB",
 404         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 405         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 406         [AZX_DRIVER_SIS] = "HDA SIS966",
 407         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 408         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 409         [AZX_DRIVER_TERA] = "HDA Teradici",
 410 };
 411
 412 /*
 413  * macros for easy use
 414  */
 415 #define azx_writel(chip,reg,value) \
 416         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 417 #define azx_readl(chip,reg) \
 418         readl((chip)->remap_addr + ICH6_REG_##reg)
 419 #define azx_writew(chip,reg,value) \
 420         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 421 #define azx_readw(chip,reg) \
 422         readw((chip)->remap_addr + ICH6_REG_##reg)
 423 #define azx_writeb(chip,reg,value) \
 424         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 425 #define azx_readb(chip,reg) \
 426         readb((chip)->remap_addr + ICH6_REG_##reg)
 427
 428 #define azx_sd_writel(dev,reg,value) \
 429         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 430 #define azx_sd_readl(dev,reg) \
 431         readl((dev)->sd_addr + ICH6_REG_##reg)
 432 #define azx_sd_writew(dev,reg,value) \
 433         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 434 #define azx_sd_readw(dev,reg) \
 435         readw((dev)->sd_addr + ICH6_REG_##reg)
 436 #define azx_sd_writeb(dev,reg,value) \
 437         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 438 #define azx_sd_readb(dev,reg) \
 439         readb((dev)->sd_addr + ICH6_REG_##reg)
 440
 441 /* for pcm support */
 442 #define get_azx_dev(substream) (substream->runtime->private_data)
 443
 444 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 445
 446 /*
 447  * Interface for HD codec
 448  */
 449
 450 /*
 451  * CORB / RIRB interface
 452  */
 453 static int azx_alloc_cmd_io(struct azx *chip)
 454 {
 455         int err;
 456
 457         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 458         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 459                                   snd_dma_pci_data(chip->pci),
 460                                   PAGE_SIZE, &chip->rb);
 461         if (err < 0) {
 462                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 463                 return err;
 464         }
 465         return 0;
 466 }
 467
 468 static void azx_init_cmd_io(struct azx *chip)
 469 {
 470         /* CORB set up */
 471         chip->corb.addr = chip->rb.addr;
 472         chip->corb.buf = (u32 *)chip->rb.area;
 473         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 474         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 475
 476         /* set the corb size to 256 entries (ULI requires explicitly) */
 477         azx_writeb(chip, CORBSIZE, 0x02);
 478         /* set the corb write pointer to 0 */
 479         azx_writew(chip, CORBWP, 0);
 480         /* reset the corb hw read pointer */
 481         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 482         /* enable corb dma */
 483         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 484
 485         /* RIRB set up */
 486         chip->rirb.addr = chip->rb.addr + 2048;
 487         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 488         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 489         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 490
 491         /* set the rirb size to 256 entries (ULI requires explicitly) */
 492         azx_writeb(chip, RIRBSIZE, 0x02);
 493         /* reset the rirb hw write pointer */
 494         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 495         /* set N=1, get RIRB response interrupt for new entry */
 496         azx_writew(chip, RINTCNT, 1);
 497         /* enable rirb dma and response irq */
 498         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 499         chip->rirb.rp = chip->rirb.cmds = 0;
 500 }
 501
 502 static void azx_free_cmd_io(struct azx *chip)
 503 {
 504         /* disable ringbuffer DMAs */
 505         azx_writeb(chip, RIRBCTL, 0);
 506         azx_writeb(chip, CORBCTL, 0);
 507 }
 508
 509 /* send a command */
 510 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
 511 {
 512         struct azx *chip = codec->bus->private_data;
 513         unsigned int wp;
 514
 515         /* add command to corb */
 516         wp = azx_readb(chip, CORBWP);
 517         wp++;
 518         wp %= ICH6_MAX_CORB_ENTRIES;
 519
 520         spin_lock_irq(&chip->reg_lock);
 521         chip->rirb.cmds++;
 522         chip->corb.buf[wp] = cpu_to_le32(val);
 523         azx_writel(chip, CORBWP, wp);
 524         spin_unlock_irq(&chip->reg_lock);
 525
 526         return 0;
 527 }
 528
 529 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 530
 531 /* retrieve RIRB entry - called from interrupt handler */
 532 static void azx_update_rirb(struct azx *chip)
 533 {
 534         unsigned int rp, wp;
 535         u32 res, res_ex;
 536
 537         wp = azx_readb(chip, RIRBWP);
 538         if (wp == chip->rirb.wp)
 539                 return;
 540         chip->rirb.wp = wp;
 541
 542         while (chip->rirb.rp != wp) {
 543                 chip->rirb.rp++;
 544                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 545
 546                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 547                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 548                 res = le32_to_cpu(chip->rirb.buf[rp]);
 549                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 550                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 551                 else if (chip->rirb.cmds) {
 552                         chip->rirb.res = res;
 553                         smp_wmb();
 554                         chip->rirb.cmds--;
 555                 }
 556         }
 557 }
 558
 559 /* receive a response */
 560 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
 561 {
 562         struct azx *chip = codec->bus->private_data;
 563         unsigned long timeout;
 564
 565  again:
 566         timeout = jiffies + msecs_to_jiffies(1000);
 567         for (;;) {
 568                 if (chip->polling_mode) {
 569                         spin_lock_irq(&chip->reg_lock);
 570                         azx_update_rirb(chip);
 571                         spin_unlock_irq(&chip->reg_lock);
 572                 }
 573                 if (!chip->rirb.cmds) {
 574                         smp_rmb();
 575                         return chip->rirb.res; /* the last value */
 576                 }
 577                 if (time_after(jiffies, timeout))
 578                         break;
 579                 if (codec->bus->needs_damn_long_delay)
 580                         msleep(2); /* temporary workaround */
 581                 else {
 582                         udelay(10);
 583                         cond_resched();
 584                 }
 585         }
 586
 587         if (chip->msi) {
 588                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 589                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 590                 free_irq(chip->irq, chip);
 591                 chip->irq = -1;
 592                 pci_disable_msi(chip->pci);
 593                 chip->msi = 0;
 594                 if (azx_acquire_irq(chip, 1) < 0)
 595                         return -1;
 596                 goto again;
 597         }
 598
 599         if (!chip->polling_mode) {
 600                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 601                            "switching to polling mode: last cmd=0x%08x\n",
 602                            chip->last_cmd);
 603                 chip->polling_mode = 1;
 604                 goto again;
 605         }
 606
 607         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 608                    "switching to single_cmd mode: last cmd=0x%08x\n",
 609                    chip->last_cmd);
 610         chip->rirb.rp = azx_readb(chip, RIRBWP);
 611         chip->rirb.cmds = 0;
 612         /* switch to single_cmd mode */
 613         chip->single_cmd = 1;
 614         azx_free_cmd_io(chip);
 615         return -1;
 616 }
 617
 618 /*
 619  * Use the single immediate command instead of CORB/RIRB for simplicity
 620  *
 621  * Note: according to Intel, this is not preferred use.  The command was
 622  *       intended for the BIOS only, and may get confused with unsolicited
 623  *       responses.  So, we shouldn't use it for normal operation from the
 624  *       driver.
 625  *       I left the codes, however, for debugging/testing purposes.
 626  */
 627
 628 /* send a command */
 629 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
 630 {
 631         struct azx *chip = codec->bus->private_data;
 632         int timeout = 50;
 633
 634         while (timeout--) {
 635                 /* check ICB busy bit */
 636                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 637                         /* Clear IRV valid bit */
 638                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 639                                    ICH6_IRS_VALID);
 640                         azx_writel(chip, IC, val);
 641                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 642                                    ICH6_IRS_BUSY);
 643                         return 0;
 644                 }
 645                 udelay(1);
 646         }
 647         if (printk_ratelimit())
 648                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 649                            azx_readw(chip, IRS), val);
 650         return -EIO;
 651 }
 652
 653 /* receive a response */
 654 static unsigned int azx_single_get_response(struct hda_codec *codec)
 655 {
 656         struct azx *chip = codec->bus->private_data;
 657         int timeout = 50;
 658
 659         while (timeout--) {
 660                 /* check IRV busy bit */
 661                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 662                         return azx_readl(chip, IR);
 663                 udelay(1);
 664         }
 665         if (printk_ratelimit())
 666                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 667                            azx_readw(chip, IRS));
 668         return (unsigned int)-1;
 669 }
 670
 671 /*
 672  * The below are the main callbacks from hda_codec.
 673  *
 674  * They are just the skeleton to call sub-callbacks according to the
 675  * current setting of chip->single_cmd.
 676  */
 677
 678 /* send a command */
 679 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
 680                         int direct, unsigned int verb,
 681                         unsigned int para)
 682 {
 683         struct azx *chip = codec->bus->private_data;
 684         u32 val;
 685
 686         val = (u32)(codec->addr & 0x0f) << 28;
 687         val |= (u32)direct << 27;
 688         val |= (u32)nid << 20;
 689         val |= verb << 8;
 690         val |= para;
 691         chip->last_cmd = val;
 692
 693         if (chip->single_cmd)
 694                 return azx_single_send_cmd(codec, val);
 695         else
 696                 return azx_corb_send_cmd(codec, val);
 697 }
 698
 699 /* get a response */
 700 static unsigned int azx_get_response(struct hda_codec *codec)
 701 {
 702         struct azx *chip = codec->bus->private_data;
 703         if (chip->single_cmd)
 704                 return azx_single_get_response(codec);
 705         else
 706                 return azx_rirb_get_response(codec);
 707 }
 708
 709 #ifdef CONFIG_SND_HDA_POWER_SAVE
 710 static void azx_power_notify(struct hda_codec *codec);
 711 #endif
 712
 713 /* reset codec link */
 714 static int azx_reset(struct azx *chip)
 715 {
 716         int count;
 717
 718         /* clear STATESTS */
 719         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 720
 721         /* reset controller */
 722         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 723
 724         count = 50;
 725         while (azx_readb(chip, GCTL) && --count)
 726                 msleep(1);
 727
 728         /* delay for >= 100us for codec PLL to settle per spec
 729          * Rev 0.9 section 5.5.1
 730          */
 731         msleep(1);
 732
 733         /* Bring controller out of reset */
 734         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 735
 736         count = 50;
 737         while (!azx_readb(chip, GCTL) && --count)
 738                 msleep(1);
 739
 740         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 741         msleep(1);
 742
 743         /* check to see if controller is ready */
 744         if (!azx_readb(chip, GCTL)) {
 745                 snd_printd("azx_reset: controller not ready!\n");
 746                 return -EBUSY;
 747         }
 748
 749         /* Accept unsolicited responses */
 750         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 751
 752         /* detect codecs */
 753         if (!chip->codec_mask) {
 754                 chip->codec_mask = azx_readw(chip, STATESTS);
 755                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 756         }
 757
 758         return 0;
 759 }
 760
 761
 762 /*
 763  * Lowlevel interface
 764  */
 765
 766 /* enable interrupts */
 767 static void azx_int_enable(struct azx *chip)
 768 {
 769         /* enable controller CIE and GIE */
 770         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 771                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 772 }
 773
 774 /* disable interrupts */
 775 static void azx_int_disable(struct azx *chip)
 776 {
 777         int i;
 778
 779         /* disable interrupts in stream descriptor */
 780         for (i = 0; i < chip->num_streams; i++) {
 781                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 782                 azx_sd_writeb(azx_dev, SD_CTL,
 783                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 784         }
 785
 786         /* disable SIE for all streams */
 787         azx_writeb(chip, INTCTL, 0);
 788
 789         /* disable controller CIE and GIE */
 790         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 791                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 792 }
 793
 794 /* clear interrupts */
 795 static void azx_int_clear(struct azx *chip)
 796 {
 797         int i;
 798
 799         /* clear stream status */
 800         for (i = 0; i < chip->num_streams; i++) {
 801                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 802                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 803         }
 804
 805         /* clear STATESTS */
 806         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 807
 808         /* clear rirb status */
 809         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 810
 811         /* clear int status */
 812         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 813 }
 814
 815 /* start a stream */
 816 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 817 {
 818         /* enable SIE */
 819         azx_writeb(chip, INTCTL,
 820                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 821         /* set DMA start and interrupt mask */
 822         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 823                       SD_CTL_DMA_START | SD_INT_MASK);
 824 }
 825
 826 /* stop a stream */
 827 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 828 {
 829         /* stop DMA */
 830         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 831                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 832         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 833         /* disable SIE */
 834         azx_writeb(chip, INTCTL,
 835                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 836 }
 837
 838
 839 /*
 840  * reset and start the controller registers
 841  */
 842 static void azx_init_chip(struct azx *chip)
 843 {
 844         if (chip->initialized)
 845                 return;
 846
 847         /* reset controller */
 848         azx_reset(chip);
 849
 850         /* initialize interrupts */
 851         azx_int_clear(chip);
 852         azx_int_enable(chip);
 853
 854         /* initialize the codec command I/O */
 855         if (!chip->single_cmd)
 856                 azx_init_cmd_io(chip);
 857
 858         /* program the position buffer */
 859         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 860         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 861
 862         chip->initialized = 1;
 863 }
 864
 865 /*
 866  * initialize the PCI registers
 867  */
 868 /* update bits in a PCI register byte */
 869 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 870                             unsigned char mask, unsigned char val)
 871 {
 872         unsigned char data;
 873
 874         pci_read_config_byte(pci, reg, &data);
 875         data &= ~mask;
 876         data |= (val & mask);
 877         pci_write_config_byte(pci, reg, data);
 878 }
 879
 880 static void azx_init_pci(struct azx *chip)
 881 {
 882         unsigned short snoop;
 883
 884         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 885          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 886          * Ensuring these bits are 0 clears playback static on some HD Audio
 887          * codecs
 888          */
 889         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 890
 891         switch (chip->driver_type) {
 892         case AZX_DRIVER_ATI:
 893                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 894                 update_pci_byte(chip->pci,
 895                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 896                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 897                 break;
 898         case AZX_DRIVER_NVIDIA:
 899                 /* For NVIDIA HDA, enable snoop */
 900                 update_pci_byte(chip->pci,
 901                                 NVIDIA_HDA_TRANSREG_ADDR,
 902                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 903                 break;
 904         case AZX_DRIVER_SCH:
 905                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 906                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 907                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 908                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 909                         pci_read_config_word(chip->pci,
 910                                 INTEL_SCH_HDA_DEVC, &snoop);
 911                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 912                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 913                                 ? "Failed" : "OK");
 914                 }
 915                 break;
 916
 917         }
 918 }
 919
 920
 921 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 922
 923 /*
 924  * interrupt handler
 925  */
 926 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 927 {
 928         struct azx *chip = dev_id;
 929         struct azx_dev *azx_dev;
 930         u32 status;
 931         int i;
 932
 933         spin_lock(&chip->reg_lock);
 934
 935         status = azx_readl(chip, INTSTS);
 936         if (status == 0) {
 937                 spin_unlock(&chip->reg_lock);
 938                 return IRQ_NONE;
 939         }
 940
 941         for (i = 0; i < chip->num_streams; i++) {
 942                 azx_dev = &chip->azx_dev[i];
 943                 if (status & azx_dev->sd_int_sta_mask) {
 944                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 945                         if (!azx_dev->substream || !azx_dev->running)
 946                                 continue;
 947                         /* ignore the first dummy IRQ (due to pos_adj) */
 948                         if (azx_dev->irq_ignore) {
 949                                 azx_dev->irq_ignore = 0;
 950                                 continue;
 951                         }
 952                         /* check whether this IRQ is really acceptable */
 953                         if (azx_position_ok(chip, azx_dev)) {
 954                                 azx_dev->irq_pending = 0;
 955                                 spin_unlock(&chip->reg_lock);
 956                                 snd_pcm_period_elapsed(azx_dev->substream);
 957                                 spin_lock(&chip->reg_lock);
 958                         } else {
 959                                 /* bogus IRQ, process it later */
 960                                 azx_dev->irq_pending = 1;
 961                                 schedule_work(&chip->irq_pending_work);
 962                         }
 963                 }
 964         }
 965
 966         /* clear rirb int */
 967         status = azx_readb(chip, RIRBSTS);
 968         if (status & RIRB_INT_MASK) {
 969                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
 970                         azx_update_rirb(chip);
 971                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 972         }
 973
 974 #if 0
 975         /* clear state status int */
 976         if (azx_readb(chip, STATESTS) & 0x04)
 977                 azx_writeb(chip, STATESTS, 0x04);
 978 #endif
 979         spin_unlock(&chip->reg_lock);
 980
 981         return IRQ_HANDLED;
 982 }
 983
 984
 985 /*
 986  * set up a BDL entry
 987  */
 988 static int setup_bdle(struct snd_pcm_substream *substream,
 989                       struct azx_dev *azx_dev, u32 **bdlp,
 990                       int ofs, int size, int with_ioc)
 991 {
 992         struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
 993         u32 *bdl = *bdlp;
 994
 995         while (size > 0) {
 996                 dma_addr_t addr;
 997                 int chunk;
 998
 999                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1000                         return -EINVAL;
1001
1002                 addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
1003                 /* program the address field of the BDL entry */
1004                 bdl[0] = cpu_to_le32((u32)addr);
1005                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1006                 /* program the size field of the BDL entry */
1007                 chunk = PAGE_SIZE - (ofs % PAGE_SIZE);
1008                 if (size < chunk)
1009                         chunk = size;
1010                 bdl[2] = cpu_to_le32(chunk);
1011                 /* program the IOC to enable interrupt
1012                  * only when the whole fragment is processed
1013                  */
1014                 size -= chunk;
1015                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1016                 bdl += 4;
1017                 azx_dev->frags++;
1018                 ofs += chunk;
1019         }
1020         *bdlp = bdl;
1021         return ofs;
1022 }
1023
1024 /*
1025  * set up BDL entries
1026  */
1027 static int azx_setup_periods(struct azx *chip,
1028                              struct snd_pcm_substream *substream,
1029                              struct azx_dev *azx_dev)
1030 {
1031         u32 *bdl;
1032         int i, ofs, periods, period_bytes;
1033         int pos_adj;
1034
1035         /* reset BDL address */
1036         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1037         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1038
1039         period_bytes = snd_pcm_lib_period_bytes(substream);
1040         azx_dev->period_bytes = period_bytes;
1041         periods = azx_dev->bufsize / period_bytes;
1042
1043         /* program the initial BDL entries */
1044         bdl = (u32 *)azx_dev->bdl.area;
1045         ofs = 0;
1046         azx_dev->frags = 0;
1047         azx_dev->irq_ignore = 0;
1048         pos_adj = bdl_pos_adj[chip->dev_index];
1049         if (pos_adj > 0) {
1050                 struct snd_pcm_runtime *runtime = substream->runtime;
1051                 int pos_align = pos_adj;
1052                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1053                 if (!pos_adj)
1054                         pos_adj = pos_align;
1055                 else
1056                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1057                                 pos_align;
1058                 pos_adj = frames_to_bytes(runtime, pos_adj);
1059                 if (pos_adj >= period_bytes) {
1060                         snd_printk(KERN_WARNING "Too big adjustment %d\n",
1061                                    bdl_pos_adj[chip->dev_index]);
1062                         pos_adj = 0;
1063                 } else {
1064                         ofs = setup_bdle(substream, azx_dev,
1065                                          &bdl, ofs, pos_adj, 1);
1066                         if (ofs < 0)
1067                                 goto error;
1068                         azx_dev->irq_ignore = 1;
1069                 }
1070         } else
1071                 pos_adj = 0;
1072         for (i = 0; i < periods; i++) {
1073                 if (i == periods - 1 && pos_adj)
1074                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1075                                          period_bytes - pos_adj, 0);
1076                 else
1077                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1078                                          period_bytes, 1);
1079                 if (ofs < 0)
1080                         goto error;
1081         }
1082         return 0;
1083
1084  error:
1085         snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1086                    azx_dev->bufsize, period_bytes);
1087         /* reset */
1088         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1089         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1090         return -EINVAL;
1091 }
1092
1093 /*
1094  * set up the SD for streaming
1095  */
1096 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1097 {
1098         unsigned char val;
1099         int timeout;
1100
1101         /* make sure the run bit is zero for SD */
1102         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1103                       ~SD_CTL_DMA_START);
1104         /* reset stream */
1105         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1106                       SD_CTL_STREAM_RESET);
1107         udelay(3);
1108         timeout = 300;
1109         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1110                --timeout)
1111                 ;
1112         val &= ~SD_CTL_STREAM_RESET;
1113         azx_sd_writeb(azx_dev, SD_CTL, val);
1114         udelay(3);
1115
1116         timeout = 300;
1117         /* waiting for hardware to report that the stream is out of reset */
1118         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1119                --timeout)
1120                 ;
1121
1122         /* program the stream_tag */
1123         azx_sd_writel(azx_dev, SD_CTL,
1124                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1125                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1126
1127         /* program the length of samples in cyclic buffer */
1128         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1129
1130         /* program the stream format */
1131         /* this value needs to be the same as the one programmed */
1132         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1133
1134         /* program the stream LVI (last valid index) of the BDL */
1135         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1136
1137         /* program the BDL address */
1138         /* lower BDL address */
1139         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1140         /* upper BDL address */
1141         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1142
1143         /* enable the position buffer */
1144         if (chip->position_fix == POS_FIX_POSBUF ||
1145             chip->position_fix == POS_FIX_AUTO) {
1146                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1147                         azx_writel(chip, DPLBASE,
1148                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1149         }
1150
1151         /* set the interrupt enable bits in the descriptor control register */
1152         azx_sd_writel(azx_dev, SD_CTL,
1153                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1154
1155         return 0;
1156 }
1157
1158
1159 /*
1160  * Codec initialization
1161  */
1162
1163 static unsigned int azx_max_codecs[] __devinitdata = {
1164         [AZX_DRIVER_ICH] = 4,           /* Some ICH9 boards use SD3 */
1165         [AZX_DRIVER_SCH] = 3,
1166         [AZX_DRIVER_ATI] = 4,
1167         [AZX_DRIVER_ATIHDMI] = 4,
1168         [AZX_DRIVER_VIA] = 3,           /* FIXME: correct? */
1169         [AZX_DRIVER_SIS] = 3,           /* FIXME: correct? */
1170         [AZX_DRIVER_ULI] = 3,           /* FIXME: correct? */
1171         [AZX_DRIVER_NVIDIA] = 3,        /* FIXME: correct? */
1172         [AZX_DRIVER_TERA] = 1,
1173 };
1174
1175 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1176                                       unsigned int codec_probe_mask)
1177 {
1178         struct hda_bus_template bus_temp;
1179         int c, codecs, audio_codecs, err;
1180
1181         memset(&bus_temp, 0, sizeof(bus_temp));
1182         bus_temp.private_data = chip;
1183         bus_temp.modelname = model;
1184         bus_temp.pci = chip->pci;
1185         bus_temp.ops.command = azx_send_cmd;
1186         bus_temp.ops.get_response = azx_get_response;
1187 #ifdef CONFIG_SND_HDA_POWER_SAVE
1188         bus_temp.ops.pm_notify = azx_power_notify;
1189 #endif
1190
1191         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1192         if (err < 0)
1193                 return err;
1194
1195         codecs = audio_codecs = 0;
1196         for (c = 0; c < AZX_MAX_CODECS; c++) {
1197                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1198                         struct hda_codec *codec;
1199                         err = snd_hda_codec_new(chip->bus, c, &codec);
1200                         if (err < 0)
1201                                 continue;
1202                         codecs++;
1203                         if (codec->afg)
1204                                 audio_codecs++;
1205                 }
1206         }
1207         if (!audio_codecs) {
1208                 /* probe additional slots if no codec is found */
1209                 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1210                         if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1211                                 err = snd_hda_codec_new(chip->bus, c, NULL);
1212                                 if (err < 0)
1213                                         continue;
1214                                 codecs++;
1215                         }
1216                 }
1217         }
1218         if (!codecs) {
1219                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1220                 return -ENXIO;
1221         }
1222
1223         return 0;
1224 }
1225
1226
1227 /*
1228  * PCM support
1229  */
1230
1231 /* assign a stream for the PCM */
1232 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1233 {
1234         int dev, i, nums;
1235         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1236                 dev = chip->playback_index_offset;
1237                 nums = chip->playback_streams;
1238         } else {
1239                 dev = chip->capture_index_offset;
1240                 nums = chip->capture_streams;
1241         }
1242         for (i = 0; i < nums; i++, dev++)
1243                 if (!chip->azx_dev[dev].opened) {
1244                         chip->azx_dev[dev].opened = 1;
1245                         return &chip->azx_dev[dev];
1246                 }
1247         return NULL;
1248 }
1249
1250 /* release the assigned stream */
1251 static inline void azx_release_device(struct azx_dev *azx_dev)
1252 {
1253         azx_dev->opened = 0;
1254 }
1255
1256 static struct snd_pcm_hardware azx_pcm_hw = {
1257         .info =                 (SNDRV_PCM_INFO_MMAP |
1258                                  SNDRV_PCM_INFO_INTERLEAVED |
1259                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1260                                  SNDRV_PCM_INFO_MMAP_VALID |
1261                                  /* No full-resume yet implemented */
1262                                  /* SNDRV_PCM_INFO_RESUME |*/
1263                                  SNDRV_PCM_INFO_PAUSE |
1264                                  SNDRV_PCM_INFO_SYNC_START),
1265         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1266         .rates =                SNDRV_PCM_RATE_48000,
1267         .rate_min =             48000,
1268         .rate_max =             48000,
1269         .channels_min =         2,
1270         .channels_max =         2,
1271         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1272         .period_bytes_min =     128,
1273         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1274         .periods_min =          2,
1275         .periods_max =          AZX_MAX_FRAG,
1276         .fifo_size =            0,
1277 };
1278
1279 struct azx_pcm {
1280         struct azx *chip;
1281         struct hda_codec *codec;
1282         struct hda_pcm_stream *hinfo[2];
1283 };
1284
1285 static int azx_pcm_open(struct snd_pcm_substream *substream)
1286 {
1287         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1288         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1289         struct azx *chip = apcm->chip;
1290         struct azx_dev *azx_dev;
1291         struct snd_pcm_runtime *runtime = substream->runtime;
1292         unsigned long flags;
1293         int err;
1294
1295         mutex_lock(&chip->open_mutex);
1296         azx_dev = azx_assign_device(chip, substream->stream);
1297         if (azx_dev == NULL) {
1298                 mutex_unlock(&chip->open_mutex);
1299                 return -EBUSY;
1300         }
1301         runtime->hw = azx_pcm_hw;
1302         runtime->hw.channels_min = hinfo->channels_min;
1303         runtime->hw.channels_max = hinfo->channels_max;
1304         runtime->hw.formats = hinfo->formats;
1305         runtime->hw.rates = hinfo->rates;
1306         snd_pcm_limit_hw_rates(runtime);
1307         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1308         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1309                                    128);
1310         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1311                                    128);
1312         snd_hda_power_up(apcm->codec);
1313         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1314         if (err < 0) {
1315                 azx_release_device(azx_dev);
1316                 snd_hda_power_down(apcm->codec);
1317                 mutex_unlock(&chip->open_mutex);
1318                 return err;
1319         }
1320         spin_lock_irqsave(&chip->reg_lock, flags);
1321         azx_dev->substream = substream;
1322         azx_dev->running = 0;
1323         spin_unlock_irqrestore(&chip->reg_lock, flags);
1324
1325         runtime->private_data = azx_dev;
1326         snd_pcm_set_sync(substream);
1327         mutex_unlock(&chip->open_mutex);
1328         return 0;
1329 }
1330
1331 static int azx_pcm_close(struct snd_pcm_substream *substream)
1332 {
1333         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1334         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1335         struct azx *chip = apcm->chip;
1336         struct azx_dev *azx_dev = get_azx_dev(substream);
1337         unsigned long flags;
1338
1339         mutex_lock(&chip->open_mutex);
1340         spin_lock_irqsave(&chip->reg_lock, flags);
1341         azx_dev->substream = NULL;
1342         azx_dev->running = 0;
1343         spin_unlock_irqrestore(&chip->reg_lock, flags);
1344         azx_release_device(azx_dev);
1345         hinfo->ops.close(hinfo, apcm->codec, substream);
1346         snd_hda_power_down(apcm->codec);
1347         mutex_unlock(&chip->open_mutex);
1348         return 0;
1349 }
1350
1351 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1352                              struct snd_pcm_hw_params *hw_params)
1353 {
1354         return snd_pcm_lib_malloc_pages(substream,
1355                                         params_buffer_bytes(hw_params));
1356 }
1357
1358 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1359 {
1360         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1361         struct azx_dev *azx_dev = get_azx_dev(substream);
1362         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1363
1364         /* reset BDL address */
1365         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1366         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1367         azx_sd_writel(azx_dev, SD_CTL, 0);
1368
1369         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1370
1371         return snd_pcm_lib_free_pages(substream);
1372 }
1373
1374 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1375 {
1376         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1377         struct azx *chip = apcm->chip;
1378         struct azx_dev *azx_dev = get_azx_dev(substream);
1379         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1380         struct snd_pcm_runtime *runtime = substream->runtime;
1381
1382         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1383         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1384                                                          runtime->channels,
1385                                                          runtime->format,
1386                                                          hinfo->maxbps);
1387         if (!azx_dev->format_val) {
1388                 snd_printk(KERN_ERR SFX
1389                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1390                            runtime->rate, runtime->channels, runtime->format);
1391                 return -EINVAL;
1392         }
1393
1394         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1395                     azx_dev->bufsize, azx_dev->format_val);
1396         if (azx_setup_periods(chip, substream, azx_dev) < 0)
1397                 return -EINVAL;
1398         azx_setup_controller(chip, azx_dev);
1399         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1400                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1401         else
1402                 azx_dev->fifo_size = 0;
1403
1404         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1405                                   azx_dev->format_val, substream);
1406 }
1407
1408 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1409 {
1410         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1411         struct azx *chip = apcm->chip;
1412         struct azx_dev *azx_dev;
1413         struct snd_pcm_substream *s;
1414         int start, nsync = 0, sbits = 0;
1415         int nwait, timeout;
1416
1417         switch (cmd) {
1418         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1419         case SNDRV_PCM_TRIGGER_RESUME:
1420         case SNDRV_PCM_TRIGGER_START:
1421                 start = 1;
1422                 break;
1423         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1424         case SNDRV_PCM_TRIGGER_SUSPEND:
1425         case SNDRV_PCM_TRIGGER_STOP:
1426                 start = 0;
1427                 break;
1428         default:
1429                 return -EINVAL;
1430         }
1431
1432         snd_pcm_group_for_each_entry(s, substream) {
1433                 if (s->pcm->card != substream->pcm->card)
1434                         continue;
1435                 azx_dev = get_azx_dev(s);
1436                 sbits |= 1 << azx_dev->index;
1437                 nsync++;
1438                 snd_pcm_trigger_done(s, substream);
1439         }
1440
1441         spin_lock(&chip->reg_lock);
1442         if (nsync > 1) {
1443                 /* first, set SYNC bits of corresponding streams */
1444                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1445         }
1446         snd_pcm_group_for_each_entry(s, substream) {
1447                 if (s->pcm->card != substream->pcm->card)
1448                         continue;
1449                 azx_dev = get_azx_dev(s);
1450                 if (start)
1451                         azx_stream_start(chip, azx_dev);
1452                 else
1453                         azx_stream_stop(chip, azx_dev);
1454                 azx_dev->running = start;
1455         }
1456         spin_unlock(&chip->reg_lock);
1457         if (start) {
1458                 if (nsync == 1)
1459                         return 0;
1460                 /* wait until all FIFOs get ready */
1461                 for (timeout = 5000; timeout; timeout--) {
1462                         nwait = 0;
1463                         snd_pcm_group_for_each_entry(s, substream) {
1464                                 if (s->pcm->card != substream->pcm->card)
1465                                         continue;
1466                                 azx_dev = get_azx_dev(s);
1467                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1468                                       SD_STS_FIFO_READY))
1469                                         nwait++;
1470                         }
1471                         if (!nwait)
1472                                 break;
1473                         cpu_relax();
1474                 }
1475         } else {
1476                 /* wait until all RUN bits are cleared */
1477                 for (timeout = 5000; timeout; timeout--) {
1478                         nwait = 0;
1479                         snd_pcm_group_for_each_entry(s, substream) {
1480                                 if (s->pcm->card != substream->pcm->card)
1481                                         continue;
1482                                 azx_dev = get_azx_dev(s);
1483                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1484                                     SD_CTL_DMA_START)
1485                                         nwait++;
1486                         }
1487                         if (!nwait)
1488                                 break;
1489                         cpu_relax();
1490                 }
1491         }
1492         if (nsync > 1) {
1493                 spin_lock(&chip->reg_lock);
1494                 /* reset SYNC bits */
1495                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1496                 spin_unlock(&chip->reg_lock);
1497         }
1498         return 0;
1499 }
1500
1501 static unsigned int azx_get_position(struct azx *chip,
1502                                      struct azx_dev *azx_dev)
1503 {
1504         unsigned int pos;
1505
1506         if (chip->position_fix == POS_FIX_POSBUF ||
1507             chip->position_fix == POS_FIX_AUTO) {
1508                 /* use the position buffer */
1509                 pos = le32_to_cpu(*azx_dev->posbuf);
1510         } else {
1511                 /* read LPIB */
1512                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1513         }
1514         if (pos >= azx_dev->bufsize)
1515                 pos = 0;
1516         return pos;
1517 }
1518
1519 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1520 {
1521         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1522         struct azx *chip = apcm->chip;
1523         struct azx_dev *azx_dev = get_azx_dev(substream);
1524         return bytes_to_frames(substream->runtime,
1525                                azx_get_position(chip, azx_dev));
1526 }
1527
1528 /*
1529  * Check whether the current DMA position is acceptable for updating
1530  * periods.  Returns non-zero if it's OK.
1531  *
1532  * Many HD-audio controllers appear pretty inaccurate about
1533  * the update-IRQ timing.  The IRQ is issued before actually the
1534  * data is processed.  So, we need to process it afterwords in a
1535  * workqueue.
1536  */
1537 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1538 {
1539         unsigned int pos;
1540
1541         pos = azx_get_position(chip, azx_dev);
1542         if (chip->position_fix == POS_FIX_AUTO) {
1543                 if (!pos) {
1544                         printk(KERN_WARNING
1545                                "hda-intel: Invalid position buffer, "
1546                                "using LPIB read method instead.\n");
1547                         chip->position_fix = POS_FIX_LPIB;
1548                         pos = azx_get_position(chip, azx_dev);
1549                 } else
1550                         chip->position_fix = POS_FIX_POSBUF;
1551         }
1552
1553         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1554                 return 0; /* NG - it's below the period boundary */
1555         return 1; /* OK, it's fine */
1556 }
1557
1558 /*
1559  * The work for pending PCM period updates.
1560  */
1561 static void azx_irq_pending_work(struct work_struct *work)
1562 {
1563         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1564         int i, pending;
1565
1566         if (!chip->irq_pending_warned) {
1567                 printk(KERN_WARNING
1568                        "hda-intel: IRQ timing workaround is activated "
1569                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1570                        chip->card->number);
1571                 chip->irq_pending_warned = 1;
1572         }
1573
1574         for (;;) {
1575                 pending = 0;
1576                 spin_lock_irq(&chip->reg_lock);
1577                 for (i = 0; i < chip->num_streams; i++) {
1578                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1579                         if (!azx_dev->irq_pending ||
1580                             !azx_dev->substream ||
1581                             !azx_dev->running)
1582                                 continue;
1583                         if (azx_position_ok(chip, azx_dev)) {
1584                                 azx_dev->irq_pending = 0;
1585                                 spin_unlock(&chip->reg_lock);
1586                                 snd_pcm_period_elapsed(azx_dev->substream);
1587                                 spin_lock(&chip->reg_lock);
1588                         } else
1589                                 pending++;
1590                 }
1591                 spin_unlock_irq(&chip->reg_lock);
1592                 if (!pending)
1593                         return;
1594                 cond_resched();
1595         }
1596 }
1597
1598 /* clear irq_pending flags and assure no on-going workq */
1599 static void azx_clear_irq_pending(struct azx *chip)
1600 {
1601         int i;
1602
1603         spin_lock_irq(&chip->reg_lock);
1604         for (i = 0; i < chip->num_streams; i++)
1605                 chip->azx_dev[i].irq_pending = 0;
1606         spin_unlock_irq(&chip->reg_lock);
1607         flush_scheduled_work();
1608 }
1609
1610 static struct snd_pcm_ops azx_pcm_ops = {
1611         .open = azx_pcm_open,
1612         .close = azx_pcm_close,
1613         .ioctl = snd_pcm_lib_ioctl,
1614         .hw_params = azx_pcm_hw_params,
1615         .hw_free = azx_pcm_hw_free,
1616         .prepare = azx_pcm_prepare,
1617         .trigger = azx_pcm_trigger,
1618         .pointer = azx_pcm_pointer,
1619         .page = snd_pcm_sgbuf_ops_page,
1620 };
1621
1622 static void azx_pcm_free(struct snd_pcm *pcm)
1623 {
1624         kfree(pcm->private_data);
1625 }
1626
1627 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1628                                       struct hda_pcm *cpcm)
1629 {
1630         int err;
1631         struct snd_pcm *pcm;
1632         struct azx_pcm *apcm;
1633
1634         /* if no substreams are defined for both playback and capture,
1635          * it's just a placeholder.  ignore it.
1636          */
1637         if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1638                 return 0;
1639
1640         snd_assert(cpcm->name, return -EINVAL);
1641
1642         err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1643                           cpcm->stream[0].substreams,
1644                           cpcm->stream[1].substreams,
1645                           &pcm);
1646         if (err < 0)
1647                 return err;
1648         strcpy(pcm->name, cpcm->name);
1649         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1650         if (apcm == NULL)
1651                 return -ENOMEM;
1652         apcm->chip = chip;
1653         apcm->codec = codec;
1654         apcm->hinfo[0] = &cpcm->stream[0];
1655         apcm->hinfo[1] = &cpcm->stream[1];
1656         pcm->private_data = apcm;
1657         pcm->private_free = azx_pcm_free;
1658         if (cpcm->stream[0].substreams)
1659                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1660         if (cpcm->stream[1].substreams)
1661                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1662         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1663                                               snd_dma_pci_data(chip->pci),
1664                                               1024 * 64, 1024 * 1024);
1665         chip->pcm[cpcm->device] = pcm;
1666         return 0;
1667 }
1668
1669 static int __devinit azx_pcm_create(struct azx *chip)
1670 {
1671         static const char *dev_name[HDA_PCM_NTYPES] = {
1672                 "Audio", "SPDIF", "HDMI", "Modem"
1673         };
1674         /* starting device index for each PCM type */
1675         static int dev_idx[HDA_PCM_NTYPES] = {
1676                 [HDA_PCM_TYPE_AUDIO] = 0,
1677                 [HDA_PCM_TYPE_SPDIF] = 1,
1678                 [HDA_PCM_TYPE_HDMI] = 3,
1679                 [HDA_PCM_TYPE_MODEM] = 6
1680         };
1681         /* normal audio device indices; not linear to keep compatibility */
1682         static int audio_idx[4] = { 0, 2, 4, 5 };
1683         struct hda_codec *codec;
1684         int c, err;
1685         int num_devs[HDA_PCM_NTYPES];
1686
1687         err = snd_hda_build_pcms(chip->bus);
1688         if (err < 0)
1689                 return err;
1690
1691         /* create audio PCMs */
1692         memset(num_devs, 0, sizeof(num_devs));
1693         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1694                 for (c = 0; c < codec->num_pcms; c++) {
1695                         struct hda_pcm *cpcm = &codec->pcm_info[c];
1696                         int type = cpcm->pcm_type;
1697                         switch (type) {
1698                         case HDA_PCM_TYPE_AUDIO:
1699                                 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1700                                         snd_printk(KERN_WARNING
1701                                                    "Too many audio devices\n");
1702                                         continue;
1703                                 }
1704                                 cpcm->device = audio_idx[num_devs[type]];
1705                                 break;
1706                         case HDA_PCM_TYPE_SPDIF:
1707                         case HDA_PCM_TYPE_HDMI:
1708                         case HDA_PCM_TYPE_MODEM:
1709                                 if (num_devs[type]) {
1710                                         snd_printk(KERN_WARNING
1711                                                    "%s already defined\n",
1712                                                    dev_name[type]);
1713                                         continue;
1714                                 }
1715                                 cpcm->device = dev_idx[type];
1716                                 break;
1717                         default:
1718                                 snd_printk(KERN_WARNING
1719                                            "Invalid PCM type %d\n", type);
1720                                 continue;
1721                         }
1722                         num_devs[type]++;
1723                         err = create_codec_pcm(chip, codec, cpcm);
1724                         if (err < 0)
1725                                 return err;
1726                 }
1727         }
1728         return 0;
1729 }
1730
1731 /*
1732  * mixer creation - all stuff is implemented in hda module
1733  */
1734 static int __devinit azx_mixer_create(struct azx *chip)
1735 {
1736         return snd_hda_build_controls(chip->bus);
1737 }
1738
1739
1740 /*
1741  * initialize SD streams
1742  */
1743 static int __devinit azx_init_stream(struct azx *chip)
1744 {
1745         int i;
1746
1747         /* initialize each stream (aka device)
1748          * assign the starting bdl address to each stream (device)
1749          * and initialize
1750          */
1751         for (i = 0; i < chip->num_streams; i++) {
1752                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1753                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1754                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1755                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1756                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1757                 azx_dev->sd_int_sta_mask = 1 << i;
1758                 /* stream tag: must be non-zero and unique */
1759                 azx_dev->index = i;
1760                 azx_dev->stream_tag = i + 1;
1761         }
1762
1763         return 0;
1764 }
1765
1766 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1767 {
1768         if (request_irq(chip->pci->irq, azx_interrupt,
1769                         chip->msi ? 0 : IRQF_SHARED,
1770                         "HDA Intel", chip)) {
1771                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1772                        "disabling device\n", chip->pci->irq);
1773                 if (do_disconnect)
1774                         snd_card_disconnect(chip->card);
1775                 return -1;
1776         }
1777         chip->irq = chip->pci->irq;
1778         pci_intx(chip->pci, !chip->msi);
1779         return 0;
1780 }
1781
1782
1783 static void azx_stop_chip(struct azx *chip)
1784 {
1785         if (!chip->initialized)
1786                 return;
1787
1788         /* disable interrupts */
1789         azx_int_disable(chip);
1790         azx_int_clear(chip);
1791
1792         /* disable CORB/RIRB */
1793         azx_free_cmd_io(chip);
1794
1795         /* disable position buffer */
1796         azx_writel(chip, DPLBASE, 0);
1797         azx_writel(chip, DPUBASE, 0);
1798
1799         chip->initialized = 0;
1800 }
1801
1802 #ifdef CONFIG_SND_HDA_POWER_SAVE
1803 /* power-up/down the controller */
1804 static void azx_power_notify(struct hda_codec *codec)
1805 {
1806         struct azx *chip = codec->bus->private_data;
1807         struct hda_codec *c;
1808         int power_on = 0;
1809
1810         list_for_each_entry(c, &codec->bus->codec_list, list) {
1811                 if (c->power_on) {
1812                         power_on = 1;
1813                         break;
1814                 }
1815         }
1816         if (power_on)
1817                 azx_init_chip(chip);
1818         else if (chip->running && power_save_controller)
1819                 azx_stop_chip(chip);
1820 }
1821 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1822
1823 #ifdef CONFIG_PM
1824 /*
1825  * power management
1826  */
1827 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1828 {
1829         struct snd_card *card = pci_get_drvdata(pci);
1830         struct azx *chip = card->private_data;
1831         int i;
1832
1833         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1834         azx_clear_irq_pending(chip);
1835         for (i = 0; i < AZX_MAX_PCMS; i++)
1836                 snd_pcm_suspend_all(chip->pcm[i]);
1837         if (chip->initialized)
1838                 snd_hda_suspend(chip->bus, state);
1839         azx_stop_chip(chip);
1840         if (chip->irq >= 0) {
1841                 free_irq(chip->irq, chip);
1842                 chip->irq = -1;
1843         }
1844         if (chip->msi)
1845                 pci_disable_msi(chip->pci);
1846         pci_disable_device(pci);
1847         pci_save_state(pci);
1848         pci_set_power_state(pci, pci_choose_state(pci, state));
1849         return 0;
1850 }
1851
1852 static int azx_resume(struct pci_dev *pci)
1853 {
1854         struct snd_card *card = pci_get_drvdata(pci);
1855         struct azx *chip = card->private_data;
1856
1857         pci_set_power_state(pci, PCI_D0);
1858         pci_restore_state(pci);
1859         if (pci_enable_device(pci) < 0) {
1860                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1861                        "disabling device\n");
1862                 snd_card_disconnect(card);
1863                 return -EIO;
1864         }
1865         pci_set_master(pci);
1866         if (chip->msi)
1867                 if (pci_enable_msi(pci) < 0)
1868                         chip->msi = 0;
1869         if (azx_acquire_irq(chip, 1) < 0)
1870                 return -EIO;
1871         azx_init_pci(chip);
1872
1873         if (snd_hda_codecs_inuse(chip->bus))
1874                 azx_init_chip(chip);
1875
1876         snd_hda_resume(chip->bus);
1877         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1878         return 0;
1879 }
1880 #endif /* CONFIG_PM */
1881
1882
1883 /*
1884  * destructor
1885  */
1886 static int azx_free(struct azx *chip)
1887 {
1888         int i;
1889
1890         if (chip->initialized) {
1891                 azx_clear_irq_pending(chip);
1892                 for (i = 0; i < chip->num_streams; i++)
1893                         azx_stream_stop(chip, &chip->azx_dev[i]);
1894                 azx_stop_chip(chip);
1895         }
1896
1897         if (chip->irq >= 0)
1898                 free_irq(chip->irq, (void*)chip);
1899         if (chip->msi)
1900                 pci_disable_msi(chip->pci);
1901         if (chip->remap_addr)
1902                 iounmap(chip->remap_addr);
1903
1904         if (chip->azx_dev) {
1905                 for (i = 0; i < chip->num_streams; i++)
1906                         if (chip->azx_dev[i].bdl.area)
1907                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1908         }
1909         if (chip->rb.area)
1910                 snd_dma_free_pages(&chip->rb);
1911         if (chip->posbuf.area)
1912                 snd_dma_free_pages(&chip->posbuf);
1913         pci_release_regions(chip->pci);
1914         pci_disable_device(chip->pci);
1915         kfree(chip->azx_dev);
1916         kfree(chip);
1917
1918         return 0;
1919 }
1920
1921 static int azx_dev_free(struct snd_device *device)
1922 {
1923         return azx_free(device->device_data);
1924 }
1925
1926 /*
1927  * white/black-listing for position_fix
1928  */
1929 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1930         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1931         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1932         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1933         {}
1934 };
1935
1936 static int __devinit check_position_fix(struct azx *chip, int fix)
1937 {
1938         const struct snd_pci_quirk *q;
1939
1940         if (fix == POS_FIX_AUTO) {
1941                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1942                 if (q) {
1943                         printk(KERN_INFO
1944                                     "hda_intel: position_fix set to %d "
1945                                     "for device %04x:%04x\n",
1946                                     q->value, q->subvendor, q->subdevice);
1947                         return q->value;
1948                 }
1949         }
1950         return fix;
1951 }
1952
1953 /*
1954  * black-lists for probe_mask
1955  */
1956 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1957         /* Thinkpad often breaks the controller communication when accessing
1958          * to the non-working (or non-existing) modem codec slot.
1959          */
1960         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1961         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1962         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1963         {}
1964 };
1965
1966 static void __devinit check_probe_mask(struct azx *chip, int dev)
1967 {
1968         const struct snd_pci_quirk *q;
1969
1970         if (probe_mask[dev] == -1) {
1971                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1972                 if (q) {
1973                         printk(KERN_INFO
1974                                "hda_intel: probe_mask set to 0x%x "
1975                                "for device %04x:%04x\n",
1976                                q->value, q->subvendor, q->subdevice);
1977                         probe_mask[dev] = q->value;
1978                 }
1979         }
1980 }
1981
1982
1983 /*
1984  * constructor
1985  */
1986 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1987                                 int dev, int driver_type,
1988                                 struct azx **rchip)
1989 {
1990         struct azx *chip;
1991         int i, err;
1992         unsigned short gcap;
1993         static struct snd_device_ops ops = {
1994                 .dev_free = azx_dev_free,
1995         };
1996
1997         *rchip = NULL;
1998
1999         err = pci_enable_device(pci);
2000         if (err < 0)
2001                 return err;
2002
2003         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2004         if (!chip) {
2005                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2006                 pci_disable_device(pci);
2007                 return -ENOMEM;
2008         }
2009
2010         spin_lock_init(&chip->reg_lock);
2011         mutex_init(&chip->open_mutex);
2012         chip->card = card;
2013         chip->pci = pci;
2014         chip->irq = -1;
2015         chip->driver_type = driver_type;
2016         chip->msi = enable_msi;
2017         chip->dev_index = dev;
2018         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2019
2020         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2021         check_probe_mask(chip, dev);
2022
2023         chip->single_cmd = single_cmd;
2024
2025         if (bdl_pos_adj[dev] < 0) {
2026                 switch (chip->driver_type) {
2027                 case AZX_DRIVER_ICH:
2028                         bdl_pos_adj[dev] = 1;
2029                         break;
2030                 default:
2031                         bdl_pos_adj[dev] = 32;
2032                         break;
2033                 }
2034         }
2035
2036 #if BITS_PER_LONG != 64
2037         /* Fix up base address on ULI M5461 */
2038         if (chip->driver_type == AZX_DRIVER_ULI) {
2039                 u16 tmp3;
2040                 pci_read_config_word(pci, 0x40, &tmp3);
2041                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2042                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2043         }
2044 #endif
2045
2046         err = pci_request_regions(pci, "ICH HD audio");
2047         if (err < 0) {
2048                 kfree(chip);
2049                 pci_disable_device(pci);
2050                 return err;
2051         }
2052
2053         chip->addr = pci_resource_start(pci, 0);
2054         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2055         if (chip->remap_addr == NULL) {
2056                 snd_printk(KERN_ERR SFX "ioremap error\n");
2057                 err = -ENXIO;
2058                 goto errout;
2059         }
2060
2061         if (chip->msi)
2062                 if (pci_enable_msi(pci) < 0)
2063                         chip->msi = 0;
2064
2065         if (azx_acquire_irq(chip, 0) < 0) {
2066                 err = -EBUSY;
2067                 goto errout;
2068         }
2069
2070         pci_set_master(pci);
2071         synchronize_irq(chip->irq);
2072
2073         gcap = azx_readw(chip, GCAP);
2074         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2075
2076         /* allow 64bit DMA address if supported by H/W */
2077         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2078                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2079
2080         /* read number of streams from GCAP register instead of using
2081          * hardcoded value
2082          */
2083         chip->capture_streams = (gcap >> 8) & 0x0f;
2084         chip->playback_streams = (gcap >> 12) & 0x0f;
2085         if (!chip->playback_streams && !chip->capture_streams) {
2086                 /* gcap didn't give any info, switching to old method */
2087
2088                 switch (chip->driver_type) {
2089                 case AZX_DRIVER_ULI:
2090                         chip->playback_streams = ULI_NUM_PLAYBACK;
2091                         chip->capture_streams = ULI_NUM_CAPTURE;
2092                         break;
2093                 case AZX_DRIVER_ATIHDMI:
2094                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2095                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2096                         break;
2097                 default:
2098                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2099                         chip->capture_streams = ICH6_NUM_CAPTURE;
2100                         break;
2101                 }
2102         }
2103         chip->capture_index_offset = 0;
2104         chip->playback_index_offset = chip->capture_streams;
2105         chip->num_streams = chip->playback_streams + chip->capture_streams;
2106         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2107                                 GFP_KERNEL);
2108         if (!chip->azx_dev) {
2109                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2110                 goto errout;
2111         }
2112
2113         for (i = 0; i < chip->num_streams; i++) {
2114                 /* allocate memory for the BDL for each stream */
2115                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2116                                           snd_dma_pci_data(chip->pci),
2117                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2118                 if (err < 0) {
2119                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2120                         goto errout;
2121                 }
2122         }
2123         /* allocate memory for the position buffer */
2124         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2125                                   snd_dma_pci_data(chip->pci),
2126                                   chip->num_streams * 8, &chip->posbuf);
2127         if (err < 0) {
2128                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2129                 goto errout;
2130         }
2131         /* allocate CORB/RIRB */
2132         if (!chip->single_cmd) {
2133                 err = azx_alloc_cmd_io(chip);
2134                 if (err < 0)
2135                         goto errout;
2136         }
2137
2138         /* initialize streams */
2139         azx_init_stream(chip);
2140
2141         /* initialize chip */
2142         azx_init_pci(chip);
2143         azx_init_chip(chip);
2144
2145         /* codec detection */
2146         if (!chip->codec_mask) {
2147                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2148                 err = -ENODEV;
2149                 goto errout;
2150         }
2151
2152         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2153         if (err <0) {
2154                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2155                 goto errout;
2156         }
2157
2158         strcpy(card->driver, "HDA-Intel");
2159         strcpy(card->shortname, driver_short_names[chip->driver_type]);
2160         sprintf(card->longname, "%s at 0x%lx irq %i",
2161                 card->shortname, chip->addr, chip->irq);
2162
2163         *rchip = chip;
2164         return 0;
2165
2166  errout:
2167         azx_free(chip);
2168         return err;
2169 }
2170
2171 static void power_down_all_codecs(struct azx *chip)
2172 {
2173 #ifdef CONFIG_SND_HDA_POWER_SAVE
2174         /* The codecs were powered up in snd_hda_codec_new().
2175          * Now all initialization done, so turn them down if possible
2176          */
2177         struct hda_codec *codec;
2178         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2179                 snd_hda_power_down(codec);
2180         }
2181 #endif
2182 }
2183
2184 static int __devinit azx_probe(struct pci_dev *pci,
2185                                const struct pci_device_id *pci_id)
2186 {
2187         static int dev;
2188         struct snd_card *card;
2189         struct azx *chip;
2190         int err;
2191
2192         if (dev >= SNDRV_CARDS)
2193                 return -ENODEV;
2194         if (!enable[dev]) {
2195                 dev++;
2196                 return -ENOENT;
2197         }
2198
2199         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2200         if (!card) {
2201                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2202                 return -ENOMEM;
2203         }
2204
2205         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2206         if (err < 0) {
2207                 snd_card_free(card);
2208                 return err;
2209         }
2210         card->private_data = chip;
2211
2212         /* create codec instances */
2213         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2214         if (err < 0) {
2215                 snd_card_free(card);
2216                 return err;
2217         }
2218
2219         /* create PCM streams */
2220         err = azx_pcm_create(chip);
2221         if (err < 0) {
2222                 snd_card_free(card);
2223                 return err;
2224         }
2225
2226         /* create mixer controls */
2227         err = azx_mixer_create(chip);
2228         if (err < 0) {
2229                 snd_card_free(card);
2230                 return err;
2231         }
2232
2233         snd_card_set_dev(card, &pci->dev);
2234
2235         err = snd_card_register(card);
2236         if (err < 0) {
2237                 snd_card_free(card);
2238                 return err;
2239         }
2240
2241         pci_set_drvdata(pci, card);
2242         chip->running = 1;
2243         power_down_all_codecs(chip);
2244
2245         dev++;
2246         return err;
2247 }
2248
2249 static void __devexit azx_remove(struct pci_dev *pci)
2250 {
2251         snd_card_free(pci_get_drvdata(pci));
2252         pci_set_drvdata(pci, NULL);
2253 }
2254
2255 /* PCI IDs */
2256 static struct pci_device_id azx_ids[] = {
2257         /* ICH 6..10 */
2258         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2259         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2260         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2261         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2262         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2263         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2264         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2265         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2266         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2267         /* PCH */
2268         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2269         /* SCH */
2270         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2271         /* ATI SB 450/600 */
2272         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2273         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2274         /* ATI HDMI */
2275         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2276         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2277         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2278         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2279         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2280         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2281         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2282         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2283         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2284         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2285         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2286         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2287         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2288         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2289         /* VIA VT8251/VT8237A */
2290         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2291         /* SIS966 */
2292         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2293         /* ULI M5461 */
2294         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2295         /* NVIDIA MCP */
2296         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2297         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2298         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2299         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2300         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2301         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2302         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2303         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2304         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2305         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2306         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2307         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2308         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2309         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2310         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2311         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2312         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2313         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2314         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2315         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2316         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2317         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2318         /* Teradici */
2319         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2320         { 0, }
2321 };
2322 MODULE_DEVICE_TABLE(pci, azx_ids);
2323
2324 /* pci_driver definition */
2325 static struct pci_driver driver = {
2326         .name = "HDA Intel",
2327         .id_table = azx_ids,
2328         .probe = azx_probe,
2329         .remove = __devexit_p(azx_remove),
2330 #ifdef CONFIG_PM
2331         .suspend = azx_suspend,
2332         .resume = azx_resume,
2333 #endif
2334 };
2335
2336 static int __init alsa_card_azx_init(void)
2337 {
2338         return pci_register_driver(&driver);
2339 }
2340
2341 static void __exit alsa_card_azx_exit(void)
2342 {
2343         pci_unregister_driver(&driver);
2344 }
2345
2346 module_init(alsa_card_azx_init)
2347 module_exit(alsa_card_azx_exit)