3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
55 static char *model[SNDRV_CARDS];
56 static int position_fix[SNDRV_CARDS];
57 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
58 static int single_cmd;
59 static int enable_msi;
61 module_param_array(index, int, NULL, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param_array(id, charp, NULL, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param_array(enable, bool, NULL, 0444);
66 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
67 module_param_array(model, charp, NULL, 0444);
68 MODULE_PARM_DESC(model, "Use the given board model.");
69 module_param_array(position_fix, int, NULL, 0444);
70 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
71 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
72 module_param_array(probe_mask, int, NULL, 0444);
73 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
74 module_param(single_cmd, bool, 0444);
75 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
76 "(for debugging only).");
77 module_param(enable_msi, int, 0444);
78 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
80 #ifdef CONFIG_SND_HDA_POWER_SAVE
81 /* power_save option is defined in hda_codec.c */
83 /* reset the HD-audio controller in power save mode.
84 * this may give more power-saving, but will take longer time to
87 static int power_save_controller = 1;
88 module_param(power_save_controller, bool, 0644);
89 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
92 MODULE_LICENSE("GPL");
93 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
117 MODULE_DESCRIPTION("Intel HDA driver");
119 #define SFX "hda-intel: "
125 #define ICH6_REG_GCAP 0x00
126 #define ICH6_REG_VMIN 0x02
127 #define ICH6_REG_VMAJ 0x03
128 #define ICH6_REG_OUTPAY 0x04
129 #define ICH6_REG_INPAY 0x06
130 #define ICH6_REG_GCTL 0x08
131 #define ICH6_REG_WAKEEN 0x0c
132 #define ICH6_REG_STATESTS 0x0e
133 #define ICH6_REG_GSTS 0x10
134 #define ICH6_REG_INTCTL 0x20
135 #define ICH6_REG_INTSTS 0x24
136 #define ICH6_REG_WALCLK 0x30
137 #define ICH6_REG_SYNC 0x34
138 #define ICH6_REG_CORBLBASE 0x40
139 #define ICH6_REG_CORBUBASE 0x44
140 #define ICH6_REG_CORBWP 0x48
141 #define ICH6_REG_CORBRP 0x4A
142 #define ICH6_REG_CORBCTL 0x4c
143 #define ICH6_REG_CORBSTS 0x4d
144 #define ICH6_REG_CORBSIZE 0x4e
146 #define ICH6_REG_RIRBLBASE 0x50
147 #define ICH6_REG_RIRBUBASE 0x54
148 #define ICH6_REG_RIRBWP 0x58
149 #define ICH6_REG_RINTCNT 0x5a
150 #define ICH6_REG_RIRBCTL 0x5c
151 #define ICH6_REG_RIRBSTS 0x5d
152 #define ICH6_REG_RIRBSIZE 0x5e
154 #define ICH6_REG_IC 0x60
155 #define ICH6_REG_IR 0x64
156 #define ICH6_REG_IRS 0x68
157 #define ICH6_IRS_VALID (1<<1)
158 #define ICH6_IRS_BUSY (1<<0)
160 #define ICH6_REG_DPLBASE 0x70
161 #define ICH6_REG_DPUBASE 0x74
162 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
164 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
165 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
167 /* stream register offsets from stream base */
168 #define ICH6_REG_SD_CTL 0x00
169 #define ICH6_REG_SD_STS 0x03
170 #define ICH6_REG_SD_LPIB 0x04
171 #define ICH6_REG_SD_CBL 0x08
172 #define ICH6_REG_SD_LVI 0x0c
173 #define ICH6_REG_SD_FIFOW 0x0e
174 #define ICH6_REG_SD_FIFOSIZE 0x10
175 #define ICH6_REG_SD_FORMAT 0x12
176 #define ICH6_REG_SD_BDLPL 0x18
177 #define ICH6_REG_SD_BDLPU 0x1c
180 #define ICH6_PCIREG_TCSEL 0x44
186 /* max number of SDs */
187 /* ICH, ATI and VIA have 4 playback and 4 capture */
188 #define ICH6_NUM_CAPTURE 4
189 #define ICH6_NUM_PLAYBACK 4
191 /* ULI has 6 playback and 5 capture */
192 #define ULI_NUM_CAPTURE 5
193 #define ULI_NUM_PLAYBACK 6
195 /* ATI HDMI has 1 playback and 0 capture */
196 #define ATIHDMI_NUM_CAPTURE 0
197 #define ATIHDMI_NUM_PLAYBACK 1
199 /* this number is statically defined for simplicity */
200 #define MAX_AZX_DEV 16
202 /* max number of fragments - we may use more if allocating more pages for BDL */
203 #define BDL_SIZE 4096
204 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
205 #define AZX_MAX_FRAG 32
206 /* max buffer size - no h/w limit, you can increase as you like */
207 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
208 /* max number of PCM devics per card */
209 #define AZX_MAX_PCMS 8
211 /* RIRB int mask: overrun[2], response[0] */
212 #define RIRB_INT_RESPONSE 0x01
213 #define RIRB_INT_OVERRUN 0x04
214 #define RIRB_INT_MASK 0x05
216 /* STATESTS int mask: SD2,SD1,SD0 */
217 #define AZX_MAX_CODECS 3
218 #define STATESTS_INT_MASK 0x07
221 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
222 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
223 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
224 #define SD_CTL_STREAM_TAG_SHIFT 20
226 /* SD_CTL and SD_STS */
227 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
228 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
229 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
230 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
234 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
236 /* INTCTL and INTSTS */
237 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
238 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
239 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
241 /* GCTL unsolicited response enable bit */
242 #define ICH6_GCTL_UREN (1<<8)
245 #define ICH6_GCTL_RESET (1<<0)
247 /* CORB/RIRB control, read/write pointer */
248 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
249 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
250 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
251 /* below are so far hardcoded - should read registers in future */
252 #define ICH6_MAX_CORB_ENTRIES 256
253 #define ICH6_MAX_RIRB_ENTRIES 256
255 /* position fix mode */
263 /* Defines for ATI HD Audio support in SB450 south bridge */
264 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
265 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
267 /* Defines for Nvidia HDA support */
268 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
269 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
271 /* Defines for Intel SCH HDA snoop control */
272 #define INTEL_SCH_HDA_DEVC 0x78
273 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
280 struct snd_dma_buffer bdl; /* BDL buffer */
281 u32 *posbuf; /* position buffer pointer */
283 unsigned int bufsize; /* size of the play buffer in bytes */
284 unsigned int frags; /* number for period in the play buffer */
285 unsigned int fifo_size; /* FIFO size */
287 void __iomem *sd_addr; /* stream descriptor pointer */
289 u32 sd_int_sta_mask; /* stream int status mask */
292 struct snd_pcm_substream *substream; /* assigned substream,
295 unsigned int format_val; /* format value to be set in the
296 * controller and the codec
298 unsigned char stream_tag; /* assigned stream */
299 unsigned char index; /* stream index */
300 /* for sanity check of position buffer */
301 unsigned int period_intr;
303 unsigned int opened :1;
304 unsigned int running :1;
309 u32 *buf; /* CORB/RIRB buffer
310 * Each CORB entry is 4byte, RIRB is 8byte
312 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
314 unsigned short rp, wp; /* read/write pointers */
315 int cmds; /* number of pending requests */
316 u32 res; /* last read value */
320 struct snd_card *card;
323 /* chip type specific */
325 int playback_streams;
326 int playback_index_offset;
328 int capture_index_offset;
333 void __iomem *remap_addr;
338 struct mutex open_mutex;
340 /* streams (x num_streams) */
341 struct azx_dev *azx_dev;
344 struct snd_pcm *pcm[AZX_MAX_PCMS];
347 unsigned short codec_mask;
354 /* CORB/RIRB and position buffers */
355 struct snd_dma_buffer rb;
356 struct snd_dma_buffer posbuf;
360 unsigned int running :1;
361 unsigned int initialized :1;
362 unsigned int single_cmd :1;
363 unsigned int polling_mode :1;
367 unsigned int last_cmd; /* last issued command (to sync) */
382 static char *driver_short_names[] __devinitdata = {
383 [AZX_DRIVER_ICH] = "HDA Intel",
384 [AZX_DRIVER_SCH] = "HDA Intel MID",
385 [AZX_DRIVER_ATI] = "HDA ATI SB",
386 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
387 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
388 [AZX_DRIVER_SIS] = "HDA SIS966",
389 [AZX_DRIVER_ULI] = "HDA ULI M5461",
390 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
394 * macros for easy use
396 #define azx_writel(chip,reg,value) \
397 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
398 #define azx_readl(chip,reg) \
399 readl((chip)->remap_addr + ICH6_REG_##reg)
400 #define azx_writew(chip,reg,value) \
401 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
402 #define azx_readw(chip,reg) \
403 readw((chip)->remap_addr + ICH6_REG_##reg)
404 #define azx_writeb(chip,reg,value) \
405 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
406 #define azx_readb(chip,reg) \
407 readb((chip)->remap_addr + ICH6_REG_##reg)
409 #define azx_sd_writel(dev,reg,value) \
410 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
411 #define azx_sd_readl(dev,reg) \
412 readl((dev)->sd_addr + ICH6_REG_##reg)
413 #define azx_sd_writew(dev,reg,value) \
414 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
415 #define azx_sd_readw(dev,reg) \
416 readw((dev)->sd_addr + ICH6_REG_##reg)
417 #define azx_sd_writeb(dev,reg,value) \
418 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
419 #define azx_sd_readb(dev,reg) \
420 readb((dev)->sd_addr + ICH6_REG_##reg)
422 /* for pcm support */
423 #define get_azx_dev(substream) (substream->runtime->private_data)
425 /* Get the upper 32bit of the given dma_addr_t
426 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
428 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
430 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
433 * Interface for HD codec
437 * CORB / RIRB interface
439 static int azx_alloc_cmd_io(struct azx *chip)
443 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
444 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
445 snd_dma_pci_data(chip->pci),
446 PAGE_SIZE, &chip->rb);
448 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
454 static void azx_init_cmd_io(struct azx *chip)
457 chip->corb.addr = chip->rb.addr;
458 chip->corb.buf = (u32 *)chip->rb.area;
459 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
460 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
462 /* set the corb size to 256 entries (ULI requires explicitly) */
463 azx_writeb(chip, CORBSIZE, 0x02);
464 /* set the corb write pointer to 0 */
465 azx_writew(chip, CORBWP, 0);
466 /* reset the corb hw read pointer */
467 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
468 /* enable corb dma */
469 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
472 chip->rirb.addr = chip->rb.addr + 2048;
473 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
474 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
475 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
477 /* set the rirb size to 256 entries (ULI requires explicitly) */
478 azx_writeb(chip, RIRBSIZE, 0x02);
479 /* reset the rirb hw write pointer */
480 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
481 /* set N=1, get RIRB response interrupt for new entry */
482 azx_writew(chip, RINTCNT, 1);
483 /* enable rirb dma and response irq */
484 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
485 chip->rirb.rp = chip->rirb.cmds = 0;
488 static void azx_free_cmd_io(struct azx *chip)
490 /* disable ringbuffer DMAs */
491 azx_writeb(chip, RIRBCTL, 0);
492 azx_writeb(chip, CORBCTL, 0);
496 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
498 struct azx *chip = codec->bus->private_data;
501 /* add command to corb */
502 wp = azx_readb(chip, CORBWP);
504 wp %= ICH6_MAX_CORB_ENTRIES;
506 spin_lock_irq(&chip->reg_lock);
508 chip->corb.buf[wp] = cpu_to_le32(val);
509 azx_writel(chip, CORBWP, wp);
510 spin_unlock_irq(&chip->reg_lock);
515 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
517 /* retrieve RIRB entry - called from interrupt handler */
518 static void azx_update_rirb(struct azx *chip)
523 wp = azx_readb(chip, RIRBWP);
524 if (wp == chip->rirb.wp)
528 while (chip->rirb.rp != wp) {
530 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
532 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
533 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
534 res = le32_to_cpu(chip->rirb.buf[rp]);
535 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
536 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
537 else if (chip->rirb.cmds) {
539 chip->rirb.res = res;
544 /* receive a response */
545 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
547 struct azx *chip = codec->bus->private_data;
548 unsigned long timeout;
551 timeout = jiffies + msecs_to_jiffies(1000);
553 if (chip->polling_mode) {
554 spin_lock_irq(&chip->reg_lock);
555 azx_update_rirb(chip);
556 spin_unlock_irq(&chip->reg_lock);
558 if (!chip->rirb.cmds)
559 return chip->rirb.res; /* the last value */
560 if (time_after(jiffies, timeout))
562 if (codec->bus->needs_damn_long_delay)
563 msleep(2); /* temporary workaround */
571 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
572 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
573 free_irq(chip->irq, chip);
575 pci_disable_msi(chip->pci);
577 if (azx_acquire_irq(chip, 1) < 0)
582 if (!chip->polling_mode) {
583 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
584 "switching to polling mode: last cmd=0x%08x\n",
586 chip->polling_mode = 1;
590 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
591 "switching to single_cmd mode: last cmd=0x%08x\n",
593 chip->rirb.rp = azx_readb(chip, RIRBWP);
595 /* switch to single_cmd mode */
596 chip->single_cmd = 1;
597 azx_free_cmd_io(chip);
602 * Use the single immediate command instead of CORB/RIRB for simplicity
604 * Note: according to Intel, this is not preferred use. The command was
605 * intended for the BIOS only, and may get confused with unsolicited
606 * responses. So, we shouldn't use it for normal operation from the
608 * I left the codes, however, for debugging/testing purposes.
612 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
614 struct azx *chip = codec->bus->private_data;
618 /* check ICB busy bit */
619 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
620 /* Clear IRV valid bit */
621 azx_writew(chip, IRS, azx_readw(chip, IRS) |
623 azx_writel(chip, IC, val);
624 azx_writew(chip, IRS, azx_readw(chip, IRS) |
630 if (printk_ratelimit())
631 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
632 azx_readw(chip, IRS), val);
636 /* receive a response */
637 static unsigned int azx_single_get_response(struct hda_codec *codec)
639 struct azx *chip = codec->bus->private_data;
643 /* check IRV busy bit */
644 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
645 return azx_readl(chip, IR);
648 if (printk_ratelimit())
649 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
650 azx_readw(chip, IRS));
651 return (unsigned int)-1;
655 * The below are the main callbacks from hda_codec.
657 * They are just the skeleton to call sub-callbacks according to the
658 * current setting of chip->single_cmd.
662 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
663 int direct, unsigned int verb,
666 struct azx *chip = codec->bus->private_data;
669 val = (u32)(codec->addr & 0x0f) << 28;
670 val |= (u32)direct << 27;
671 val |= (u32)nid << 20;
674 chip->last_cmd = val;
676 if (chip->single_cmd)
677 return azx_single_send_cmd(codec, val);
679 return azx_corb_send_cmd(codec, val);
683 static unsigned int azx_get_response(struct hda_codec *codec)
685 struct azx *chip = codec->bus->private_data;
686 if (chip->single_cmd)
687 return azx_single_get_response(codec);
689 return azx_rirb_get_response(codec);
692 #ifdef CONFIG_SND_HDA_POWER_SAVE
693 static void azx_power_notify(struct hda_codec *codec);
696 /* reset codec link */
697 static int azx_reset(struct azx *chip)
702 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
704 /* reset controller */
705 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
708 while (azx_readb(chip, GCTL) && --count)
711 /* delay for >= 100us for codec PLL to settle per spec
712 * Rev 0.9 section 5.5.1
716 /* Bring controller out of reset */
717 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
720 while (!azx_readb(chip, GCTL) && --count)
723 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
726 /* check to see if controller is ready */
727 if (!azx_readb(chip, GCTL)) {
728 snd_printd("azx_reset: controller not ready!\n");
732 /* Accept unsolicited responses */
733 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
736 if (!chip->codec_mask) {
737 chip->codec_mask = azx_readw(chip, STATESTS);
738 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
749 /* enable interrupts */
750 static void azx_int_enable(struct azx *chip)
752 /* enable controller CIE and GIE */
753 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
754 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
757 /* disable interrupts */
758 static void azx_int_disable(struct azx *chip)
762 /* disable interrupts in stream descriptor */
763 for (i = 0; i < chip->num_streams; i++) {
764 struct azx_dev *azx_dev = &chip->azx_dev[i];
765 azx_sd_writeb(azx_dev, SD_CTL,
766 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
769 /* disable SIE for all streams */
770 azx_writeb(chip, INTCTL, 0);
772 /* disable controller CIE and GIE */
773 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
774 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
777 /* clear interrupts */
778 static void azx_int_clear(struct azx *chip)
782 /* clear stream status */
783 for (i = 0; i < chip->num_streams; i++) {
784 struct azx_dev *azx_dev = &chip->azx_dev[i];
785 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
789 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
791 /* clear rirb status */
792 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
794 /* clear int status */
795 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
799 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
802 azx_writeb(chip, INTCTL,
803 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
804 /* set DMA start and interrupt mask */
805 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
806 SD_CTL_DMA_START | SD_INT_MASK);
810 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
813 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
814 ~(SD_CTL_DMA_START | SD_INT_MASK));
815 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
817 azx_writeb(chip, INTCTL,
818 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
823 * reset and start the controller registers
825 static void azx_init_chip(struct azx *chip)
827 if (chip->initialized)
830 /* reset controller */
833 /* initialize interrupts */
835 azx_int_enable(chip);
837 /* initialize the codec command I/O */
838 if (!chip->single_cmd)
839 azx_init_cmd_io(chip);
841 /* program the position buffer */
842 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
843 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
845 chip->initialized = 1;
849 * initialize the PCI registers
851 /* update bits in a PCI register byte */
852 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
853 unsigned char mask, unsigned char val)
857 pci_read_config_byte(pci, reg, &data);
859 data |= (val & mask);
860 pci_write_config_byte(pci, reg, data);
863 static void azx_init_pci(struct azx *chip)
865 unsigned short snoop;
867 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
868 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
869 * Ensuring these bits are 0 clears playback static on some HD Audio
872 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
874 switch (chip->driver_type) {
876 /* For ATI SB450 azalia HD audio, we need to enable snoop */
877 update_pci_byte(chip->pci,
878 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
879 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
881 case AZX_DRIVER_NVIDIA:
882 /* For NVIDIA HDA, enable snoop */
883 update_pci_byte(chip->pci,
884 NVIDIA_HDA_TRANSREG_ADDR,
885 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
888 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
889 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
890 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
891 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
892 pci_read_config_word(chip->pci,
893 INTEL_SCH_HDA_DEVC, &snoop);
894 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
895 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
907 static irqreturn_t azx_interrupt(int irq, void *dev_id)
909 struct azx *chip = dev_id;
910 struct azx_dev *azx_dev;
914 spin_lock(&chip->reg_lock);
916 status = azx_readl(chip, INTSTS);
918 spin_unlock(&chip->reg_lock);
922 for (i = 0; i < chip->num_streams; i++) {
923 azx_dev = &chip->azx_dev[i];
924 if (status & azx_dev->sd_int_sta_mask) {
925 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
926 if (azx_dev->substream && azx_dev->running) {
927 azx_dev->period_intr++;
928 spin_unlock(&chip->reg_lock);
929 snd_pcm_period_elapsed(azx_dev->substream);
930 spin_lock(&chip->reg_lock);
936 status = azx_readb(chip, RIRBSTS);
937 if (status & RIRB_INT_MASK) {
938 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
939 azx_update_rirb(chip);
940 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
944 /* clear state status int */
945 if (azx_readb(chip, STATESTS) & 0x04)
946 azx_writeb(chip, STATESTS, 0x04);
948 spin_unlock(&chip->reg_lock);
957 static int azx_setup_periods(struct snd_pcm_substream *substream,
958 struct azx_dev *azx_dev)
960 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
962 int i, ofs, periods, period_bytes;
964 /* reset BDL address */
965 azx_sd_writel(azx_dev, SD_BDLPL, 0);
966 azx_sd_writel(azx_dev, SD_BDLPU, 0);
968 period_bytes = snd_pcm_lib_period_bytes(substream);
969 periods = azx_dev->bufsize / period_bytes;
971 /* program the initial BDL entries */
972 bdl = (u32 *)azx_dev->bdl.area;
975 for (i = 0; i < periods; i++) {
977 if (i >= AZX_MAX_BDL_ENTRIES) {
978 snd_printk(KERN_ERR "Too many BDL entries: "
979 "buffer=%d, period=%d\n",
980 azx_dev->bufsize, period_bytes);
982 azx_sd_writel(azx_dev, SD_BDLPL, 0);
983 azx_sd_writel(azx_dev, SD_BDLPU, 0);
988 dma_addr_t addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
989 /* program the address field of the BDL entry */
990 bdl[0] = cpu_to_le32((u32)addr);
991 bdl[1] = cpu_to_le32(upper_32bit(addr));
992 /* program the size field of the BDL entry */
993 size = PAGE_SIZE - (ofs % PAGE_SIZE);
996 bdl[2] = cpu_to_le32(size);
997 /* program the IOC to enable interrupt
998 * only when the whole fragment is processed
1001 bdl[3] = rest ? 0 : cpu_to_le32(0x01);
1011 * set up the SD for streaming
1013 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1018 /* make sure the run bit is zero for SD */
1019 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1022 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1023 SD_CTL_STREAM_RESET);
1026 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1029 val &= ~SD_CTL_STREAM_RESET;
1030 azx_sd_writeb(azx_dev, SD_CTL, val);
1034 /* waiting for hardware to report that the stream is out of reset */
1035 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1039 /* program the stream_tag */
1040 azx_sd_writel(azx_dev, SD_CTL,
1041 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1042 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1044 /* program the length of samples in cyclic buffer */
1045 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1047 /* program the stream format */
1048 /* this value needs to be the same as the one programmed */
1049 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1051 /* program the stream LVI (last valid index) of the BDL */
1052 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1054 /* program the BDL address */
1055 /* lower BDL address */
1056 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1057 /* upper BDL address */
1058 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1060 /* enable the position buffer */
1061 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1062 azx_writel(chip, DPLBASE,
1063 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1065 /* set the interrupt enable bits in the descriptor control register */
1066 azx_sd_writel(azx_dev, SD_CTL,
1067 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1074 * Codec initialization
1077 static unsigned int azx_max_codecs[] __devinitdata = {
1078 [AZX_DRIVER_ICH] = 3,
1079 [AZX_DRIVER_SCH] = 3,
1080 [AZX_DRIVER_ATI] = 4,
1081 [AZX_DRIVER_ATIHDMI] = 4,
1082 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1083 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1084 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1085 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1088 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1089 unsigned int codec_probe_mask)
1091 struct hda_bus_template bus_temp;
1092 int c, codecs, audio_codecs, err;
1094 memset(&bus_temp, 0, sizeof(bus_temp));
1095 bus_temp.private_data = chip;
1096 bus_temp.modelname = model;
1097 bus_temp.pci = chip->pci;
1098 bus_temp.ops.command = azx_send_cmd;
1099 bus_temp.ops.get_response = azx_get_response;
1100 #ifdef CONFIG_SND_HDA_POWER_SAVE
1101 bus_temp.ops.pm_notify = azx_power_notify;
1104 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1108 codecs = audio_codecs = 0;
1109 for (c = 0; c < AZX_MAX_CODECS; c++) {
1110 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1111 struct hda_codec *codec;
1112 err = snd_hda_codec_new(chip->bus, c, &codec);
1120 if (!audio_codecs) {
1121 /* probe additional slots if no codec is found */
1122 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1123 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1124 err = snd_hda_codec_new(chip->bus, c, NULL);
1132 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1144 /* assign a stream for the PCM */
1145 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1148 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1149 dev = chip->playback_index_offset;
1150 nums = chip->playback_streams;
1152 dev = chip->capture_index_offset;
1153 nums = chip->capture_streams;
1155 for (i = 0; i < nums; i++, dev++)
1156 if (!chip->azx_dev[dev].opened) {
1157 chip->azx_dev[dev].opened = 1;
1158 return &chip->azx_dev[dev];
1163 /* release the assigned stream */
1164 static inline void azx_release_device(struct azx_dev *azx_dev)
1166 azx_dev->opened = 0;
1169 static struct snd_pcm_hardware azx_pcm_hw = {
1170 .info = (SNDRV_PCM_INFO_MMAP |
1171 SNDRV_PCM_INFO_INTERLEAVED |
1172 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1173 SNDRV_PCM_INFO_MMAP_VALID |
1174 /* No full-resume yet implemented */
1175 /* SNDRV_PCM_INFO_RESUME |*/
1176 SNDRV_PCM_INFO_PAUSE),
1177 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1178 .rates = SNDRV_PCM_RATE_48000,
1183 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1184 .period_bytes_min = 128,
1185 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1187 .periods_max = AZX_MAX_FRAG,
1193 struct hda_codec *codec;
1194 struct hda_pcm_stream *hinfo[2];
1197 static int azx_pcm_open(struct snd_pcm_substream *substream)
1199 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1200 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1201 struct azx *chip = apcm->chip;
1202 struct azx_dev *azx_dev;
1203 struct snd_pcm_runtime *runtime = substream->runtime;
1204 unsigned long flags;
1207 mutex_lock(&chip->open_mutex);
1208 azx_dev = azx_assign_device(chip, substream->stream);
1209 if (azx_dev == NULL) {
1210 mutex_unlock(&chip->open_mutex);
1213 runtime->hw = azx_pcm_hw;
1214 runtime->hw.channels_min = hinfo->channels_min;
1215 runtime->hw.channels_max = hinfo->channels_max;
1216 runtime->hw.formats = hinfo->formats;
1217 runtime->hw.rates = hinfo->rates;
1218 snd_pcm_limit_hw_rates(runtime);
1219 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1220 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1222 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1224 snd_hda_power_up(apcm->codec);
1225 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1227 azx_release_device(azx_dev);
1228 snd_hda_power_down(apcm->codec);
1229 mutex_unlock(&chip->open_mutex);
1232 spin_lock_irqsave(&chip->reg_lock, flags);
1233 azx_dev->substream = substream;
1234 azx_dev->running = 0;
1235 spin_unlock_irqrestore(&chip->reg_lock, flags);
1237 runtime->private_data = azx_dev;
1238 mutex_unlock(&chip->open_mutex);
1242 static int azx_pcm_close(struct snd_pcm_substream *substream)
1244 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1245 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1246 struct azx *chip = apcm->chip;
1247 struct azx_dev *azx_dev = get_azx_dev(substream);
1248 unsigned long flags;
1250 mutex_lock(&chip->open_mutex);
1251 spin_lock_irqsave(&chip->reg_lock, flags);
1252 azx_dev->substream = NULL;
1253 azx_dev->running = 0;
1254 spin_unlock_irqrestore(&chip->reg_lock, flags);
1255 azx_release_device(azx_dev);
1256 hinfo->ops.close(hinfo, apcm->codec, substream);
1257 snd_hda_power_down(apcm->codec);
1258 mutex_unlock(&chip->open_mutex);
1262 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1263 struct snd_pcm_hw_params *hw_params)
1265 return snd_pcm_lib_malloc_pages(substream,
1266 params_buffer_bytes(hw_params));
1269 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1271 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1272 struct azx_dev *azx_dev = get_azx_dev(substream);
1273 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1275 /* reset BDL address */
1276 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1277 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1278 azx_sd_writel(azx_dev, SD_CTL, 0);
1280 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1282 return snd_pcm_lib_free_pages(substream);
1285 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1287 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1288 struct azx *chip = apcm->chip;
1289 struct azx_dev *azx_dev = get_azx_dev(substream);
1290 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1291 struct snd_pcm_runtime *runtime = substream->runtime;
1293 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1294 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1298 if (!azx_dev->format_val) {
1299 snd_printk(KERN_ERR SFX
1300 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1301 runtime->rate, runtime->channels, runtime->format);
1305 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1306 azx_dev->bufsize, azx_dev->format_val);
1307 if (azx_setup_periods(substream, azx_dev) < 0)
1309 azx_setup_controller(chip, azx_dev);
1310 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1311 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1313 azx_dev->fifo_size = 0;
1315 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1316 azx_dev->format_val, substream);
1319 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1321 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1322 struct azx_dev *azx_dev = get_azx_dev(substream);
1323 struct azx *chip = apcm->chip;
1326 spin_lock(&chip->reg_lock);
1328 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1329 case SNDRV_PCM_TRIGGER_RESUME:
1330 case SNDRV_PCM_TRIGGER_START:
1331 azx_stream_start(chip, azx_dev);
1332 azx_dev->running = 1;
1334 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1335 case SNDRV_PCM_TRIGGER_SUSPEND:
1336 case SNDRV_PCM_TRIGGER_STOP:
1337 azx_stream_stop(chip, azx_dev);
1338 azx_dev->running = 0;
1343 spin_unlock(&chip->reg_lock);
1344 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1345 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1346 cmd == SNDRV_PCM_TRIGGER_STOP) {
1348 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1355 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1357 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1358 struct azx *chip = apcm->chip;
1359 struct azx_dev *azx_dev = get_azx_dev(substream);
1362 if (chip->position_fix == POS_FIX_POSBUF ||
1363 chip->position_fix == POS_FIX_AUTO) {
1364 /* use the position buffer */
1365 pos = le32_to_cpu(*azx_dev->posbuf);
1366 if (chip->position_fix == POS_FIX_AUTO &&
1367 azx_dev->period_intr == 1 && !pos) {
1369 "hda-intel: Invalid position buffer, "
1370 "using LPIB read method instead.\n");
1371 chip->position_fix = POS_FIX_NONE;
1377 pos = azx_sd_readl(azx_dev, SD_LPIB);
1378 if (chip->position_fix == POS_FIX_FIFO)
1379 pos += azx_dev->fifo_size;
1381 if (pos >= azx_dev->bufsize)
1383 return bytes_to_frames(substream->runtime, pos);
1386 static struct snd_pcm_ops azx_pcm_ops = {
1387 .open = azx_pcm_open,
1388 .close = azx_pcm_close,
1389 .ioctl = snd_pcm_lib_ioctl,
1390 .hw_params = azx_pcm_hw_params,
1391 .hw_free = azx_pcm_hw_free,
1392 .prepare = azx_pcm_prepare,
1393 .trigger = azx_pcm_trigger,
1394 .pointer = azx_pcm_pointer,
1395 .page = snd_pcm_sgbuf_ops_page,
1398 static void azx_pcm_free(struct snd_pcm *pcm)
1400 kfree(pcm->private_data);
1403 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1404 struct hda_pcm *cpcm)
1407 struct snd_pcm *pcm;
1408 struct azx_pcm *apcm;
1410 /* if no substreams are defined for both playback and capture,
1411 * it's just a placeholder. ignore it.
1413 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1416 snd_assert(cpcm->name, return -EINVAL);
1418 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1419 cpcm->stream[0].substreams,
1420 cpcm->stream[1].substreams,
1424 strcpy(pcm->name, cpcm->name);
1425 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1429 apcm->codec = codec;
1430 apcm->hinfo[0] = &cpcm->stream[0];
1431 apcm->hinfo[1] = &cpcm->stream[1];
1432 pcm->private_data = apcm;
1433 pcm->private_free = azx_pcm_free;
1434 if (cpcm->stream[0].substreams)
1435 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1436 if (cpcm->stream[1].substreams)
1437 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1438 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1439 snd_dma_pci_data(chip->pci),
1440 1024 * 64, 1024 * 1024);
1441 chip->pcm[cpcm->device] = pcm;
1445 static int __devinit azx_pcm_create(struct azx *chip)
1447 static const char *dev_name[HDA_PCM_NTYPES] = {
1448 "Audio", "SPDIF", "HDMI", "Modem"
1450 /* starting device index for each PCM type */
1451 static int dev_idx[HDA_PCM_NTYPES] = {
1452 [HDA_PCM_TYPE_AUDIO] = 0,
1453 [HDA_PCM_TYPE_SPDIF] = 1,
1454 [HDA_PCM_TYPE_HDMI] = 3,
1455 [HDA_PCM_TYPE_MODEM] = 6
1457 /* normal audio device indices; not linear to keep compatibility */
1458 static int audio_idx[4] = { 0, 2, 4, 5 };
1459 struct hda_codec *codec;
1461 int num_devs[HDA_PCM_NTYPES];
1463 err = snd_hda_build_pcms(chip->bus);
1467 /* create audio PCMs */
1468 memset(num_devs, 0, sizeof(num_devs));
1469 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1470 for (c = 0; c < codec->num_pcms; c++) {
1471 struct hda_pcm *cpcm = &codec->pcm_info[c];
1472 int type = cpcm->pcm_type;
1474 case HDA_PCM_TYPE_AUDIO:
1475 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1476 snd_printk(KERN_WARNING
1477 "Too many audio devices\n");
1480 cpcm->device = audio_idx[num_devs[type]];
1482 case HDA_PCM_TYPE_SPDIF:
1483 case HDA_PCM_TYPE_HDMI:
1484 case HDA_PCM_TYPE_MODEM:
1485 if (num_devs[type]) {
1486 snd_printk(KERN_WARNING
1487 "%s already defined\n",
1491 cpcm->device = dev_idx[type];
1494 snd_printk(KERN_WARNING
1495 "Invalid PCM type %d\n", type);
1499 err = create_codec_pcm(chip, codec, cpcm);
1508 * mixer creation - all stuff is implemented in hda module
1510 static int __devinit azx_mixer_create(struct azx *chip)
1512 return snd_hda_build_controls(chip->bus);
1517 * initialize SD streams
1519 static int __devinit azx_init_stream(struct azx *chip)
1523 /* initialize each stream (aka device)
1524 * assign the starting bdl address to each stream (device)
1527 for (i = 0; i < chip->num_streams; i++) {
1528 struct azx_dev *azx_dev = &chip->azx_dev[i];
1529 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1530 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1531 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1532 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1533 azx_dev->sd_int_sta_mask = 1 << i;
1534 /* stream tag: must be non-zero and unique */
1536 azx_dev->stream_tag = i + 1;
1542 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1544 if (request_irq(chip->pci->irq, azx_interrupt,
1545 chip->msi ? 0 : IRQF_SHARED,
1546 "HDA Intel", chip)) {
1547 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1548 "disabling device\n", chip->pci->irq);
1550 snd_card_disconnect(chip->card);
1553 chip->irq = chip->pci->irq;
1554 pci_intx(chip->pci, !chip->msi);
1559 static void azx_stop_chip(struct azx *chip)
1561 if (!chip->initialized)
1564 /* disable interrupts */
1565 azx_int_disable(chip);
1566 azx_int_clear(chip);
1568 /* disable CORB/RIRB */
1569 azx_free_cmd_io(chip);
1571 /* disable position buffer */
1572 azx_writel(chip, DPLBASE, 0);
1573 azx_writel(chip, DPUBASE, 0);
1575 chip->initialized = 0;
1578 #ifdef CONFIG_SND_HDA_POWER_SAVE
1579 /* power-up/down the controller */
1580 static void azx_power_notify(struct hda_codec *codec)
1582 struct azx *chip = codec->bus->private_data;
1583 struct hda_codec *c;
1586 list_for_each_entry(c, &codec->bus->codec_list, list) {
1593 azx_init_chip(chip);
1594 else if (chip->running && power_save_controller)
1595 azx_stop_chip(chip);
1597 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1603 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1605 struct snd_card *card = pci_get_drvdata(pci);
1606 struct azx *chip = card->private_data;
1609 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1610 for (i = 0; i < AZX_MAX_PCMS; i++)
1611 snd_pcm_suspend_all(chip->pcm[i]);
1612 if (chip->initialized)
1613 snd_hda_suspend(chip->bus, state);
1614 azx_stop_chip(chip);
1615 if (chip->irq >= 0) {
1616 synchronize_irq(chip->irq);
1617 free_irq(chip->irq, chip);
1621 pci_disable_msi(chip->pci);
1622 pci_disable_device(pci);
1623 pci_save_state(pci);
1624 pci_set_power_state(pci, pci_choose_state(pci, state));
1628 static int azx_resume(struct pci_dev *pci)
1630 struct snd_card *card = pci_get_drvdata(pci);
1631 struct azx *chip = card->private_data;
1633 pci_set_power_state(pci, PCI_D0);
1634 pci_restore_state(pci);
1635 if (pci_enable_device(pci) < 0) {
1636 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1637 "disabling device\n");
1638 snd_card_disconnect(card);
1641 pci_set_master(pci);
1643 if (pci_enable_msi(pci) < 0)
1645 if (azx_acquire_irq(chip, 1) < 0)
1649 if (snd_hda_codecs_inuse(chip->bus))
1650 azx_init_chip(chip);
1652 snd_hda_resume(chip->bus);
1653 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1656 #endif /* CONFIG_PM */
1662 static int azx_free(struct azx *chip)
1666 if (chip->initialized) {
1667 for (i = 0; i < chip->num_streams; i++)
1668 azx_stream_stop(chip, &chip->azx_dev[i]);
1669 azx_stop_chip(chip);
1672 if (chip->irq >= 0) {
1673 synchronize_irq(chip->irq);
1674 free_irq(chip->irq, (void*)chip);
1677 pci_disable_msi(chip->pci);
1678 if (chip->remap_addr)
1679 iounmap(chip->remap_addr);
1681 if (chip->azx_dev) {
1682 for (i = 0; i < chip->num_streams; i++)
1683 if (chip->azx_dev[i].bdl.area)
1684 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1687 snd_dma_free_pages(&chip->rb);
1688 if (chip->posbuf.area)
1689 snd_dma_free_pages(&chip->posbuf);
1690 pci_release_regions(chip->pci);
1691 pci_disable_device(chip->pci);
1692 kfree(chip->azx_dev);
1698 static int azx_dev_free(struct snd_device *device)
1700 return azx_free(device->device_data);
1704 * white/black-listing for position_fix
1706 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1707 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1708 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1712 static int __devinit check_position_fix(struct azx *chip, int fix)
1714 const struct snd_pci_quirk *q;
1716 if (fix == POS_FIX_AUTO) {
1717 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1720 "hda_intel: position_fix set to %d "
1721 "for device %04x:%04x\n",
1722 q->value, q->subvendor, q->subdevice);
1730 * black-lists for probe_mask
1732 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1733 /* Thinkpad often breaks the controller communication when accessing
1734 * to the non-working (or non-existing) modem codec slot.
1736 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1737 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1738 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1742 static void __devinit check_probe_mask(struct azx *chip, int dev)
1744 const struct snd_pci_quirk *q;
1746 if (probe_mask[dev] == -1) {
1747 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1750 "hda_intel: probe_mask set to 0x%x "
1751 "for device %04x:%04x\n",
1752 q->value, q->subvendor, q->subdevice);
1753 probe_mask[dev] = q->value;
1762 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1763 int dev, int driver_type,
1768 unsigned short gcap;
1769 static struct snd_device_ops ops = {
1770 .dev_free = azx_dev_free,
1775 err = pci_enable_device(pci);
1779 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1781 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1782 pci_disable_device(pci);
1786 spin_lock_init(&chip->reg_lock);
1787 mutex_init(&chip->open_mutex);
1791 chip->driver_type = driver_type;
1792 chip->msi = enable_msi;
1794 chip->position_fix = check_position_fix(chip, position_fix[dev]);
1795 check_probe_mask(chip, dev);
1797 chip->single_cmd = single_cmd;
1799 #if BITS_PER_LONG != 64
1800 /* Fix up base address on ULI M5461 */
1801 if (chip->driver_type == AZX_DRIVER_ULI) {
1803 pci_read_config_word(pci, 0x40, &tmp3);
1804 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1805 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1809 err = pci_request_regions(pci, "ICH HD audio");
1812 pci_disable_device(pci);
1816 chip->addr = pci_resource_start(pci, 0);
1817 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1818 if (chip->remap_addr == NULL) {
1819 snd_printk(KERN_ERR SFX "ioremap error\n");
1825 if (pci_enable_msi(pci) < 0)
1828 if (azx_acquire_irq(chip, 0) < 0) {
1833 pci_set_master(pci);
1834 synchronize_irq(chip->irq);
1836 gcap = azx_readw(chip, GCAP);
1837 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1839 /* allow 64bit DMA address if supported by H/W */
1840 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
1841 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
1843 /* read number of streams from GCAP register instead of using
1846 chip->capture_streams = (gcap >> 8) & 0x0f;
1847 chip->playback_streams = (gcap >> 12) & 0x0f;
1848 if (!chip->playback_streams && !chip->capture_streams) {
1849 /* gcap didn't give any info, switching to old method */
1851 switch (chip->driver_type) {
1852 case AZX_DRIVER_ULI:
1853 chip->playback_streams = ULI_NUM_PLAYBACK;
1854 chip->capture_streams = ULI_NUM_CAPTURE;
1856 case AZX_DRIVER_ATIHDMI:
1857 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1858 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1861 chip->playback_streams = ICH6_NUM_PLAYBACK;
1862 chip->capture_streams = ICH6_NUM_CAPTURE;
1866 chip->capture_index_offset = 0;
1867 chip->playback_index_offset = chip->capture_streams;
1868 chip->num_streams = chip->playback_streams + chip->capture_streams;
1869 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1871 if (!chip->azx_dev) {
1872 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1876 for (i = 0; i < chip->num_streams; i++) {
1877 /* allocate memory for the BDL for each stream */
1878 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1879 snd_dma_pci_data(chip->pci),
1880 BDL_SIZE, &chip->azx_dev[i].bdl);
1882 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1886 /* allocate memory for the position buffer */
1887 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1888 snd_dma_pci_data(chip->pci),
1889 chip->num_streams * 8, &chip->posbuf);
1891 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1894 /* allocate CORB/RIRB */
1895 if (!chip->single_cmd) {
1896 err = azx_alloc_cmd_io(chip);
1901 /* initialize streams */
1902 azx_init_stream(chip);
1904 /* initialize chip */
1906 azx_init_chip(chip);
1908 /* codec detection */
1909 if (!chip->codec_mask) {
1910 snd_printk(KERN_ERR SFX "no codecs found!\n");
1915 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1917 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1921 strcpy(card->driver, "HDA-Intel");
1922 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1923 sprintf(card->longname, "%s at 0x%lx irq %i",
1924 card->shortname, chip->addr, chip->irq);
1934 static void power_down_all_codecs(struct azx *chip)
1936 #ifdef CONFIG_SND_HDA_POWER_SAVE
1937 /* The codecs were powered up in snd_hda_codec_new().
1938 * Now all initialization done, so turn them down if possible
1940 struct hda_codec *codec;
1941 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1942 snd_hda_power_down(codec);
1947 static int __devinit azx_probe(struct pci_dev *pci,
1948 const struct pci_device_id *pci_id)
1951 struct snd_card *card;
1955 if (dev >= SNDRV_CARDS)
1962 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1964 snd_printk(KERN_ERR SFX "Error creating card!\n");
1968 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1970 snd_card_free(card);
1973 card->private_data = chip;
1975 /* create codec instances */
1976 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1978 snd_card_free(card);
1982 /* create PCM streams */
1983 err = azx_pcm_create(chip);
1985 snd_card_free(card);
1989 /* create mixer controls */
1990 err = azx_mixer_create(chip);
1992 snd_card_free(card);
1996 snd_card_set_dev(card, &pci->dev);
1998 err = snd_card_register(card);
2000 snd_card_free(card);
2004 pci_set_drvdata(pci, card);
2006 power_down_all_codecs(chip);
2012 static void __devexit azx_remove(struct pci_dev *pci)
2014 snd_card_free(pci_get_drvdata(pci));
2015 pci_set_drvdata(pci, NULL);
2019 static struct pci_device_id azx_ids[] = {
2020 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
2021 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
2022 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
2023 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
2024 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2025 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2026 { 0x8086, 0x3a3e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2027 { 0x8086, 0x3a6e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2028 { 0x8086, 0x811b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SCH }, /* SCH*/
2029 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
2030 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
2031 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
2032 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
2033 { 0x1002, 0x960f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
2034 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
2035 { 0x1002, 0xaa08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV630 HDMI */
2036 { 0x1002, 0xaa10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV610 HDMI */
2037 { 0x1002, 0xaa18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV670 HDMI */
2038 { 0x1002, 0xaa20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV635 HDMI */
2039 { 0x1002, 0xaa28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV620 HDMI */
2040 { 0x1002, 0xaa30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV770 HDMI */
2041 { 0x1002, 0xaa38, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV730 HDMI */
2042 { 0x1002, 0xaa40, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV710 HDMI */
2043 { 0x1002, 0xaa48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV740 HDMI */
2044 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
2045 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
2046 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
2047 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
2048 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
2049 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2050 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2051 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2052 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2053 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2054 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2055 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2056 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2057 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2058 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2059 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2060 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2061 { 0x10de, 0x0ac0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2062 { 0x10de, 0x0ac1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2063 { 0x10de, 0x0ac2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2064 { 0x10de, 0x0ac3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2067 MODULE_DEVICE_TABLE(pci, azx_ids);
2069 /* pci_driver definition */
2070 static struct pci_driver driver = {
2071 .name = "HDA Intel",
2072 .id_table = azx_ids,
2074 .remove = __devexit_p(azx_remove),
2076 .suspend = azx_suspend,
2077 .resume = azx_resume,
2081 static int __init alsa_card_azx_init(void)
2083 return pci_register_driver(&driver);
2086 static void __exit alsa_card_azx_exit(void)
2088 pci_unregister_driver(&driver);
2091 module_init(alsa_card_azx_init)
2092 module_exit(alsa_card_azx_exit)