sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int single_cmd;
  62 static int enable_msi;
  63
  64 module_param_array(index, int, NULL, 0444);
  65 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  66 module_param_array(id, charp, NULL, 0444);
  67 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  68 module_param_array(enable, bool, NULL, 0444);
  69 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  70 module_param_array(model, charp, NULL, 0444);
  71 MODULE_PARM_DESC(model, "Use the given board model.");
  72 module_param_array(position_fix, int, NULL, 0444);
  73 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  74                  "(0 = auto, 1 = none, 2 = POSBUF).");
  75 module_param_array(bdl_pos_adj, int, NULL, 0644);
  76 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  77 module_param_array(probe_mask, int, NULL, 0444);
  78 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  79 module_param(single_cmd, bool, 0444);
  80 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  81                  "(for debugging only).");
  82 module_param(enable_msi, int, 0444);
  83 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  84
  85 #ifdef CONFIG_SND_HDA_POWER_SAVE
  86 /* power_save option is defined in hda_codec.c */
  87
  88 /* reset the HD-audio controller in power save mode.
  89  * this may give more power-saving, but will take longer time to
  90  * wake up.
  91  */
  92 static int power_save_controller = 1;
  93 module_param(power_save_controller, bool, 0644);
  94 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  95 #endif
  96
  97 MODULE_LICENSE("GPL");
  98 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  99                          "{Intel, ICH6M},"
 100                          "{Intel, ICH7},"
 101                          "{Intel, ESB2},"
 102                          "{Intel, ICH8},"
 103                          "{Intel, ICH9},"
 104                          "{Intel, ICH10},"
 105                          "{Intel, PCH},"
 106                          "{Intel, SCH},"
 107                          "{ATI, SB450},"
 108                          "{ATI, SB600},"
 109                          "{ATI, RS600},"
 110                          "{ATI, RS690},"
 111                          "{ATI, RS780},"
 112                          "{ATI, R600},"
 113                          "{ATI, RV630},"
 114                          "{ATI, RV610},"
 115                          "{ATI, RV670},"
 116                          "{ATI, RV635},"
 117                          "{ATI, RV620},"
 118                          "{ATI, RV770},"
 119                          "{VIA, VT8251},"
 120                          "{VIA, VT8237A},"
 121                          "{SiS, SIS966},"
 122                          "{ULI, M5461}}");
 123 MODULE_DESCRIPTION("Intel HDA driver");
 124
 125 #define SFX     "hda-intel: "
 126
 127
 128 /*
 129  * registers
 130  */
 131 #define ICH6_REG_GCAP                   0x00
 132 #define ICH6_REG_VMIN                   0x02
 133 #define ICH6_REG_VMAJ                   0x03
 134 #define ICH6_REG_OUTPAY                 0x04
 135 #define ICH6_REG_INPAY                  0x06
 136 #define ICH6_REG_GCTL                   0x08
 137 #define ICH6_REG_WAKEEN                 0x0c
 138 #define ICH6_REG_STATESTS               0x0e
 139 #define ICH6_REG_GSTS                   0x10
 140 #define ICH6_REG_INTCTL                 0x20
 141 #define ICH6_REG_INTSTS                 0x24
 142 #define ICH6_REG_WALCLK                 0x30
 143 #define ICH6_REG_SYNC                   0x34
 144 #define ICH6_REG_CORBLBASE              0x40
 145 #define ICH6_REG_CORBUBASE              0x44
 146 #define ICH6_REG_CORBWP                 0x48
 147 #define ICH6_REG_CORBRP                 0x4A
 148 #define ICH6_REG_CORBCTL                0x4c
 149 #define ICH6_REG_CORBSTS                0x4d
 150 #define ICH6_REG_CORBSIZE               0x4e
 151
 152 #define ICH6_REG_RIRBLBASE              0x50
 153 #define ICH6_REG_RIRBUBASE              0x54
 154 #define ICH6_REG_RIRBWP                 0x58
 155 #define ICH6_REG_RINTCNT                0x5a
 156 #define ICH6_REG_RIRBCTL                0x5c
 157 #define ICH6_REG_RIRBSTS                0x5d
 158 #define ICH6_REG_RIRBSIZE               0x5e
 159
 160 #define ICH6_REG_IC                     0x60
 161 #define ICH6_REG_IR                     0x64
 162 #define ICH6_REG_IRS                    0x68
 163 #define   ICH6_IRS_VALID        (1<<1)
 164 #define   ICH6_IRS_BUSY         (1<<0)
 165
 166 #define ICH6_REG_DPLBASE                0x70
 167 #define ICH6_REG_DPUBASE                0x74
 168 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 169
 170 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 171 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 172
 173 /* stream register offsets from stream base */
 174 #define ICH6_REG_SD_CTL                 0x00
 175 #define ICH6_REG_SD_STS                 0x03
 176 #define ICH6_REG_SD_LPIB                0x04
 177 #define ICH6_REG_SD_CBL                 0x08
 178 #define ICH6_REG_SD_LVI                 0x0c
 179 #define ICH6_REG_SD_FIFOW               0x0e
 180 #define ICH6_REG_SD_FIFOSIZE            0x10
 181 #define ICH6_REG_SD_FORMAT              0x12
 182 #define ICH6_REG_SD_BDLPL               0x18
 183 #define ICH6_REG_SD_BDLPU               0x1c
 184
 185 /* PCI space */
 186 #define ICH6_PCIREG_TCSEL       0x44
 187
 188 /*
 189  * other constants
 190  */
 191
 192 /* max number of SDs */
 193 /* ICH, ATI and VIA have 4 playback and 4 capture */
 194 #define ICH6_NUM_CAPTURE        4
 195 #define ICH6_NUM_PLAYBACK       4
 196
 197 /* ULI has 6 playback and 5 capture */
 198 #define ULI_NUM_CAPTURE         5
 199 #define ULI_NUM_PLAYBACK        6
 200
 201 /* ATI HDMI has 1 playback and 0 capture */
 202 #define ATIHDMI_NUM_CAPTURE     0
 203 #define ATIHDMI_NUM_PLAYBACK    1
 204
 205 /* TERA has 4 playback and 3 capture */
 206 #define TERA_NUM_CAPTURE        3
 207 #define TERA_NUM_PLAYBACK       4
 208
 209 /* this number is statically defined for simplicity */
 210 #define MAX_AZX_DEV             16
 211
 212 /* max number of fragments - we may use more if allocating more pages for BDL */
 213 #define BDL_SIZE                4096
 214 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 215 #define AZX_MAX_FRAG            32
 216 /* max buffer size - no h/w limit, you can increase as you like */
 217 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 218 /* max number of PCM devics per card */
 219 #define AZX_MAX_PCMS            8
 220
 221 /* RIRB int mask: overrun[2], response[0] */
 222 #define RIRB_INT_RESPONSE       0x01
 223 #define RIRB_INT_OVERRUN        0x04
 224 #define RIRB_INT_MASK           0x05
 225
 226 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 227 #define AZX_MAX_CODECS          4
 228 #define STATESTS_INT_MASK       0x0f
 229
 230 /* SD_CTL bits */
 231 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 232 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 233 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 234 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 235 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 236 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 237 #define SD_CTL_STREAM_TAG_SHIFT 20
 238
 239 /* SD_CTL and SD_STS */
 240 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 241 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 242 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 243 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 244                                  SD_INT_COMPLETE)
 245
 246 /* SD_STS */
 247 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 248
 249 /* INTCTL and INTSTS */
 250 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 251 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 252 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 253
 254 /* GCTL unsolicited response enable bit */
 255 #define ICH6_GCTL_UREN          (1<<8)
 256
 257 /* GCTL reset bit */
 258 #define ICH6_GCTL_RESET         (1<<0)
 259
 260 /* CORB/RIRB control, read/write pointer */
 261 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 262 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 263 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 264 /* below are so far hardcoded - should read registers in future */
 265 #define ICH6_MAX_CORB_ENTRIES   256
 266 #define ICH6_MAX_RIRB_ENTRIES   256
 267
 268 /* position fix mode */
 269 enum {
 270         POS_FIX_AUTO,
 271         POS_FIX_LPIB,
 272         POS_FIX_POSBUF,
 273 };
 274
 275 /* Defines for ATI HD Audio support in SB450 south bridge */
 276 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 277 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 278
 279 /* Defines for Nvidia HDA support */
 280 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 281 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 282 #define NVIDIA_HDA_ISTRM_COH          0x4d
 283 #define NVIDIA_HDA_OSTRM_COH          0x4c
 284 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 285
 286 /* Defines for Intel SCH HDA snoop control */
 287 #define INTEL_SCH_HDA_DEVC      0x78
 288 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 289
 290 /* Define IN stream 0 FIFO size offset in VIA controller */
 291 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 292 /* Define VIA HD Audio Device ID*/
 293 #define VIA_HDAC_DEVICE_ID              0x3288
 294
 295
 296 /*
 297  */
 298
 299 struct azx_dev {
 300         struct snd_dma_buffer bdl; /* BDL buffer */
 301         u32 *posbuf;            /* position buffer pointer */
 302
 303         unsigned int bufsize;   /* size of the play buffer in bytes */
 304         unsigned int period_bytes; /* size of the period in bytes */
 305         unsigned int frags;     /* number for period in the play buffer */
 306         unsigned int fifo_size; /* FIFO size */
 307
 308         void __iomem *sd_addr;  /* stream descriptor pointer */
 309
 310         u32 sd_int_sta_mask;    /* stream int status mask */
 311
 312         /* pcm support */
 313         struct snd_pcm_substream *substream;    /* assigned substream,
 314                                                  * set in PCM open
 315                                                  */
 316         unsigned int format_val;        /* format value to be set in the
 317                                          * controller and the codec
 318                                          */
 319         unsigned char stream_tag;       /* assigned stream */
 320         unsigned char index;            /* stream index */
 321
 322         unsigned int opened :1;
 323         unsigned int running :1;
 324         unsigned int irq_pending :1;
 325         unsigned int irq_ignore :1;
 326         /*
 327          * For VIA:
 328          *  A flag to ensure DMA position is 0
 329          *  when link position is not greater than FIFO size
 330          */
 331         unsigned int insufficient :1;
 332 };
 333
 334 /* CORB/RIRB */
 335 struct azx_rb {
 336         u32 *buf;               /* CORB/RIRB buffer
 337                                  * Each CORB entry is 4byte, RIRB is 8byte
 338                                  */
 339         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 340         /* for RIRB */
 341         unsigned short rp, wp;  /* read/write pointers */
 342         int cmds;               /* number of pending requests */
 343         u32 res;                /* last read value */
 344 };
 345
 346 struct azx {
 347         struct snd_card *card;
 348         struct pci_dev *pci;
 349         int dev_index;
 350
 351         /* chip type specific */
 352         int driver_type;
 353         int playback_streams;
 354         int playback_index_offset;
 355         int capture_streams;
 356         int capture_index_offset;
 357         int num_streams;
 358
 359         /* pci resources */
 360         unsigned long addr;
 361         void __iomem *remap_addr;
 362         int irq;
 363
 364         /* locks */
 365         spinlock_t reg_lock;
 366         struct mutex open_mutex;
 367
 368         /* streams (x num_streams) */
 369         struct azx_dev *azx_dev;
 370
 371         /* PCM */
 372         struct snd_pcm *pcm[AZX_MAX_PCMS];
 373
 374         /* HD codec */
 375         unsigned short codec_mask;
 376         struct hda_bus *bus;
 377
 378         /* CORB/RIRB */
 379         struct azx_rb corb;
 380         struct azx_rb rirb;
 381
 382         /* CORB/RIRB and position buffers */
 383         struct snd_dma_buffer rb;
 384         struct snd_dma_buffer posbuf;
 385
 386         /* flags */
 387         int position_fix;
 388         unsigned int running :1;
 389         unsigned int initialized :1;
 390         unsigned int single_cmd :1;
 391         unsigned int polling_mode :1;
 392         unsigned int msi :1;
 393         unsigned int irq_pending_warned :1;
 394         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 395
 396         /* for debugging */
 397         unsigned int last_cmd;  /* last issued command (to sync) */
 398
 399         /* for pending irqs */
 400         struct work_struct irq_pending_work;
 401
 402         /* reboot notifier (for mysterious hangup problem at power-down) */
 403         struct notifier_block reboot_notifier;
 404 };
 405
 406 /* driver types */
 407 enum {
 408         AZX_DRIVER_ICH,
 409         AZX_DRIVER_SCH,
 410         AZX_DRIVER_ATI,
 411         AZX_DRIVER_ATIHDMI,
 412         AZX_DRIVER_VIA,
 413         AZX_DRIVER_SIS,
 414         AZX_DRIVER_ULI,
 415         AZX_DRIVER_NVIDIA,
 416         AZX_DRIVER_TERA,
 417         AZX_NUM_DRIVERS, /* keep this as last entry */
 418 };
 419
 420 static char *driver_short_names[] __devinitdata = {
 421         [AZX_DRIVER_ICH] = "HDA Intel",
 422         [AZX_DRIVER_SCH] = "HDA Intel MID",
 423         [AZX_DRIVER_ATI] = "HDA ATI SB",
 424         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 425         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 426         [AZX_DRIVER_SIS] = "HDA SIS966",
 427         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 428         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 429         [AZX_DRIVER_TERA] = "HDA Teradici",
 430 };
 431
 432 /*
 433  * macros for easy use
 434  */
 435 #define azx_writel(chip,reg,value) \
 436         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 437 #define azx_readl(chip,reg) \
 438         readl((chip)->remap_addr + ICH6_REG_##reg)
 439 #define azx_writew(chip,reg,value) \
 440         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 441 #define azx_readw(chip,reg) \
 442         readw((chip)->remap_addr + ICH6_REG_##reg)
 443 #define azx_writeb(chip,reg,value) \
 444         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 445 #define azx_readb(chip,reg) \
 446         readb((chip)->remap_addr + ICH6_REG_##reg)
 447
 448 #define azx_sd_writel(dev,reg,value) \
 449         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 450 #define azx_sd_readl(dev,reg) \
 451         readl((dev)->sd_addr + ICH6_REG_##reg)
 452 #define azx_sd_writew(dev,reg,value) \
 453         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 454 #define azx_sd_readw(dev,reg) \
 455         readw((dev)->sd_addr + ICH6_REG_##reg)
 456 #define azx_sd_writeb(dev,reg,value) \
 457         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 458 #define azx_sd_readb(dev,reg) \
 459         readb((dev)->sd_addr + ICH6_REG_##reg)
 460
 461 /* for pcm support */
 462 #define get_azx_dev(substream) (substream->runtime->private_data)
 463
 464 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 465
 466 /*
 467  * Interface for HD codec
 468  */
 469
 470 /*
 471  * CORB / RIRB interface
 472  */
 473 static int azx_alloc_cmd_io(struct azx *chip)
 474 {
 475         int err;
 476
 477         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 478         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 479                                   snd_dma_pci_data(chip->pci),
 480                                   PAGE_SIZE, &chip->rb);
 481         if (err < 0) {
 482                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 483                 return err;
 484         }
 485         return 0;
 486 }
 487
 488 static void azx_init_cmd_io(struct azx *chip)
 489 {
 490         /* CORB set up */
 491         chip->corb.addr = chip->rb.addr;
 492         chip->corb.buf = (u32 *)chip->rb.area;
 493         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 494         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 495
 496         /* set the corb size to 256 entries (ULI requires explicitly) */
 497         azx_writeb(chip, CORBSIZE, 0x02);
 498         /* set the corb write pointer to 0 */
 499         azx_writew(chip, CORBWP, 0);
 500         /* reset the corb hw read pointer */
 501         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 502         /* enable corb dma */
 503         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 504
 505         /* RIRB set up */
 506         chip->rirb.addr = chip->rb.addr + 2048;
 507         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 508         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 509         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 510
 511         /* set the rirb size to 256 entries (ULI requires explicitly) */
 512         azx_writeb(chip, RIRBSIZE, 0x02);
 513         /* reset the rirb hw write pointer */
 514         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 515         /* set N=1, get RIRB response interrupt for new entry */
 516         azx_writew(chip, RINTCNT, 1);
 517         /* enable rirb dma and response irq */
 518         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 519         chip->rirb.rp = chip->rirb.cmds = 0;
 520 }
 521
 522 static void azx_free_cmd_io(struct azx *chip)
 523 {
 524         /* disable ringbuffer DMAs */
 525         azx_writeb(chip, RIRBCTL, 0);
 526         azx_writeb(chip, CORBCTL, 0);
 527 }
 528
 529 /* send a command */
 530 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 531 {
 532         struct azx *chip = bus->private_data;
 533         unsigned int wp;
 534
 535         /* add command to corb */
 536         wp = azx_readb(chip, CORBWP);
 537         wp++;
 538         wp %= ICH6_MAX_CORB_ENTRIES;
 539
 540         spin_lock_irq(&chip->reg_lock);
 541         chip->rirb.cmds++;
 542         chip->corb.buf[wp] = cpu_to_le32(val);
 543         azx_writel(chip, CORBWP, wp);
 544         spin_unlock_irq(&chip->reg_lock);
 545
 546         return 0;
 547 }
 548
 549 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 550
 551 /* retrieve RIRB entry - called from interrupt handler */
 552 static void azx_update_rirb(struct azx *chip)
 553 {
 554         unsigned int rp, wp;
 555         u32 res, res_ex;
 556
 557         wp = azx_readb(chip, RIRBWP);
 558         if (wp == chip->rirb.wp)
 559                 return;
 560         chip->rirb.wp = wp;
 561
 562         while (chip->rirb.rp != wp) {
 563                 chip->rirb.rp++;
 564                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 565
 566                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 567                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 568                 res = le32_to_cpu(chip->rirb.buf[rp]);
 569                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 570                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 571                 else if (chip->rirb.cmds) {
 572                         chip->rirb.res = res;
 573                         smp_wmb();
 574                         chip->rirb.cmds--;
 575                 }
 576         }
 577 }
 578
 579 /* receive a response */
 580 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
 581 {
 582         struct azx *chip = bus->private_data;
 583         unsigned long timeout;
 584
 585  again:
 586         timeout = jiffies + msecs_to_jiffies(1000);
 587         for (;;) {
 588                 if (chip->polling_mode) {
 589                         spin_lock_irq(&chip->reg_lock);
 590                         azx_update_rirb(chip);
 591                         spin_unlock_irq(&chip->reg_lock);
 592                 }
 593                 if (!chip->rirb.cmds) {
 594                         smp_rmb();
 595                         return chip->rirb.res; /* the last value */
 596                 }
 597                 if (time_after(jiffies, timeout))
 598                         break;
 599                 if (bus->needs_damn_long_delay)
 600                         msleep(2); /* temporary workaround */
 601                 else {
 602                         udelay(10);
 603                         cond_resched();
 604                 }
 605         }
 606
 607         if (chip->msi) {
 608                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 609                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 610                 free_irq(chip->irq, chip);
 611                 chip->irq = -1;
 612                 pci_disable_msi(chip->pci);
 613                 chip->msi = 0;
 614                 if (azx_acquire_irq(chip, 1) < 0)
 615                         return -1;
 616                 goto again;
 617         }
 618
 619         if (!chip->polling_mode) {
 620                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 621                            "switching to polling mode: last cmd=0x%08x\n",
 622                            chip->last_cmd);
 623                 chip->polling_mode = 1;
 624                 goto again;
 625         }
 626
 627         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 628                    "switching to single_cmd mode: last cmd=0x%08x\n",
 629                    chip->last_cmd);
 630         chip->rirb.rp = azx_readb(chip, RIRBWP);
 631         chip->rirb.cmds = 0;
 632         /* switch to single_cmd mode */
 633         chip->single_cmd = 1;
 634         azx_free_cmd_io(chip);
 635         return -1;
 636 }
 637
 638 /*
 639  * Use the single immediate command instead of CORB/RIRB for simplicity
 640  *
 641  * Note: according to Intel, this is not preferred use.  The command was
 642  *       intended for the BIOS only, and may get confused with unsolicited
 643  *       responses.  So, we shouldn't use it for normal operation from the
 644  *       driver.
 645  *       I left the codes, however, for debugging/testing purposes.
 646  */
 647
 648 /* send a command */
 649 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 650 {
 651         struct azx *chip = bus->private_data;
 652         int timeout = 50;
 653
 654         while (timeout--) {
 655                 /* check ICB busy bit */
 656                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 657                         /* Clear IRV valid bit */
 658                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 659                                    ICH6_IRS_VALID);
 660                         azx_writel(chip, IC, val);
 661                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 662                                    ICH6_IRS_BUSY);
 663                         return 0;
 664                 }
 665                 udelay(1);
 666         }
 667         if (printk_ratelimit())
 668                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 669                            azx_readw(chip, IRS), val);
 670         return -EIO;
 671 }
 672
 673 /* receive a response */
 674 static unsigned int azx_single_get_response(struct hda_bus *bus)
 675 {
 676         struct azx *chip = bus->private_data;
 677         int timeout = 50;
 678
 679         while (timeout--) {
 680                 /* check IRV busy bit */
 681                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 682                         return azx_readl(chip, IR);
 683                 udelay(1);
 684         }
 685         if (printk_ratelimit())
 686                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 687                            azx_readw(chip, IRS));
 688         return (unsigned int)-1;
 689 }
 690
 691 /*
 692  * The below are the main callbacks from hda_codec.
 693  *
 694  * They are just the skeleton to call sub-callbacks according to the
 695  * current setting of chip->single_cmd.
 696  */
 697
 698 /* send a command */
 699 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 700 {
 701         struct azx *chip = bus->private_data;
 702
 703         chip->last_cmd = val;
 704         if (chip->single_cmd)
 705                 return azx_single_send_cmd(bus, val);
 706         else
 707                 return azx_corb_send_cmd(bus, val);
 708 }
 709
 710 /* get a response */
 711 static unsigned int azx_get_response(struct hda_bus *bus)
 712 {
 713         struct azx *chip = bus->private_data;
 714         if (chip->single_cmd)
 715                 return azx_single_get_response(bus);
 716         else
 717                 return azx_rirb_get_response(bus);
 718 }
 719
 720 #ifdef CONFIG_SND_HDA_POWER_SAVE
 721 static void azx_power_notify(struct hda_bus *bus);
 722 #endif
 723
 724 /* reset codec link */
 725 static int azx_reset(struct azx *chip)
 726 {
 727         int count;
 728
 729         /* clear STATESTS */
 730         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 731
 732         /* reset controller */
 733         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 734
 735         count = 50;
 736         while (azx_readb(chip, GCTL) && --count)
 737                 msleep(1);
 738
 739         /* delay for >= 100us for codec PLL to settle per spec
 740          * Rev 0.9 section 5.5.1
 741          */
 742         msleep(1);
 743
 744         /* Bring controller out of reset */
 745         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 746
 747         count = 50;
 748         while (!azx_readb(chip, GCTL) && --count)
 749                 msleep(1);
 750
 751         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 752         msleep(1);
 753
 754         /* check to see if controller is ready */
 755         if (!azx_readb(chip, GCTL)) {
 756                 snd_printd("azx_reset: controller not ready!\n");
 757                 return -EBUSY;
 758         }
 759
 760         /* Accept unsolicited responses */
 761         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 762
 763         /* detect codecs */
 764         if (!chip->codec_mask) {
 765                 chip->codec_mask = azx_readw(chip, STATESTS);
 766                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 767         }
 768
 769         return 0;
 770 }
 771
 772
 773 /*
 774  * Lowlevel interface
 775  */
 776
 777 /* enable interrupts */
 778 static void azx_int_enable(struct azx *chip)
 779 {
 780         /* enable controller CIE and GIE */
 781         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 782                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 783 }
 784
 785 /* disable interrupts */
 786 static void azx_int_disable(struct azx *chip)
 787 {
 788         int i;
 789
 790         /* disable interrupts in stream descriptor */
 791         for (i = 0; i < chip->num_streams; i++) {
 792                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 793                 azx_sd_writeb(azx_dev, SD_CTL,
 794                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 795         }
 796
 797         /* disable SIE for all streams */
 798         azx_writeb(chip, INTCTL, 0);
 799
 800         /* disable controller CIE and GIE */
 801         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 802                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 803 }
 804
 805 /* clear interrupts */
 806 static void azx_int_clear(struct azx *chip)
 807 {
 808         int i;
 809
 810         /* clear stream status */
 811         for (i = 0; i < chip->num_streams; i++) {
 812                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 813                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 814         }
 815
 816         /* clear STATESTS */
 817         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 818
 819         /* clear rirb status */
 820         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 821
 822         /* clear int status */
 823         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 824 }
 825
 826 /* start a stream */
 827 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 828 {
 829         /*
 830          * Before stream start, initialize parameter
 831          */
 832         azx_dev->insufficient = 1;
 833
 834         /* enable SIE */
 835         azx_writeb(chip, INTCTL,
 836                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 837         /* set DMA start and interrupt mask */
 838         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 839                       SD_CTL_DMA_START | SD_INT_MASK);
 840 }
 841
 842 /* stop a stream */
 843 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 844 {
 845         /* stop DMA */
 846         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 847                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 848         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 849         /* disable SIE */
 850         azx_writeb(chip, INTCTL,
 851                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 852 }
 853
 854
 855 /*
 856  * reset and start the controller registers
 857  */
 858 static void azx_init_chip(struct azx *chip)
 859 {
 860         if (chip->initialized)
 861                 return;
 862
 863         /* reset controller */
 864         azx_reset(chip);
 865
 866         /* initialize interrupts */
 867         azx_int_clear(chip);
 868         azx_int_enable(chip);
 869
 870         /* initialize the codec command I/O */
 871         if (!chip->single_cmd)
 872                 azx_init_cmd_io(chip);
 873
 874         /* program the position buffer */
 875         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 876         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 877
 878         chip->initialized = 1;
 879 }
 880
 881 /*
 882  * initialize the PCI registers
 883  */
 884 /* update bits in a PCI register byte */
 885 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 886                             unsigned char mask, unsigned char val)
 887 {
 888         unsigned char data;
 889
 890         pci_read_config_byte(pci, reg, &data);
 891         data &= ~mask;
 892         data |= (val & mask);
 893         pci_write_config_byte(pci, reg, data);
 894 }
 895
 896 static void azx_init_pci(struct azx *chip)
 897 {
 898         unsigned short snoop;
 899
 900         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 901          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 902          * Ensuring these bits are 0 clears playback static on some HD Audio
 903          * codecs
 904          */
 905         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 906
 907         switch (chip->driver_type) {
 908         case AZX_DRIVER_ATI:
 909                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 910                 update_pci_byte(chip->pci,
 911                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 912                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 913                 break;
 914         case AZX_DRIVER_NVIDIA:
 915                 /* For NVIDIA HDA, enable snoop */
 916                 update_pci_byte(chip->pci,
 917                                 NVIDIA_HDA_TRANSREG_ADDR,
 918                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 919                 update_pci_byte(chip->pci,
 920                                 NVIDIA_HDA_ISTRM_COH,
 921                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 922                 update_pci_byte(chip->pci,
 923                                 NVIDIA_HDA_OSTRM_COH,
 924                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 925                 break;
 926         case AZX_DRIVER_SCH:
 927                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 928                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 929                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 930                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 931                         pci_read_config_word(chip->pci,
 932                                 INTEL_SCH_HDA_DEVC, &snoop);
 933                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 934                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 935                                 ? "Failed" : "OK");
 936                 }
 937                 break;
 938
 939         }
 940 }
 941
 942
 943 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 944
 945 /*
 946  * interrupt handler
 947  */
 948 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 949 {
 950         struct azx *chip = dev_id;
 951         struct azx_dev *azx_dev;
 952         u32 status;
 953         int i;
 954
 955         spin_lock(&chip->reg_lock);
 956
 957         status = azx_readl(chip, INTSTS);
 958         if (status == 0) {
 959                 spin_unlock(&chip->reg_lock);
 960                 return IRQ_NONE;
 961         }
 962
 963         for (i = 0; i < chip->num_streams; i++) {
 964                 azx_dev = &chip->azx_dev[i];
 965                 if (status & azx_dev->sd_int_sta_mask) {
 966                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 967                         if (!azx_dev->substream || !azx_dev->running)
 968                                 continue;
 969                         /* ignore the first dummy IRQ (due to pos_adj) */
 970                         if (azx_dev->irq_ignore) {
 971                                 azx_dev->irq_ignore = 0;
 972                                 continue;
 973                         }
 974                         /* check whether this IRQ is really acceptable */
 975                         if (azx_position_ok(chip, azx_dev)) {
 976                                 azx_dev->irq_pending = 0;
 977                                 spin_unlock(&chip->reg_lock);
 978                                 snd_pcm_period_elapsed(azx_dev->substream);
 979                                 spin_lock(&chip->reg_lock);
 980                         } else {
 981                                 /* bogus IRQ, process it later */
 982                                 azx_dev->irq_pending = 1;
 983                                 schedule_work(&chip->irq_pending_work);
 984                         }
 985                 }
 986         }
 987
 988         /* clear rirb int */
 989         status = azx_readb(chip, RIRBSTS);
 990         if (status & RIRB_INT_MASK) {
 991                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
 992                         azx_update_rirb(chip);
 993                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 994         }
 995
 996 #if 0
 997         /* clear state status int */
 998         if (azx_readb(chip, STATESTS) & 0x04)
 999                 azx_writeb(chip, STATESTS, 0x04);
1000 #endif
1001         spin_unlock(&chip->reg_lock);
1002
1003         return IRQ_HANDLED;
1004 }
1005
1006
1007 /*
1008  * set up a BDL entry
1009  */
1010 static int setup_bdle(struct snd_pcm_substream *substream,
1011                       struct azx_dev *azx_dev, u32 **bdlp,
1012                       int ofs, int size, int with_ioc)
1013 {
1014         u32 *bdl = *bdlp;
1015
1016         while (size > 0) {
1017                 dma_addr_t addr;
1018                 int chunk;
1019
1020                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1021                         return -EINVAL;
1022
1023                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1024                 /* program the address field of the BDL entry */
1025                 bdl[0] = cpu_to_le32((u32)addr);
1026                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1027                 /* program the size field of the BDL entry */
1028                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1029                 bdl[2] = cpu_to_le32(chunk);
1030                 /* program the IOC to enable interrupt
1031                  * only when the whole fragment is processed
1032                  */
1033                 size -= chunk;
1034                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1035                 bdl += 4;
1036                 azx_dev->frags++;
1037                 ofs += chunk;
1038         }
1039         *bdlp = bdl;
1040         return ofs;
1041 }
1042
1043 /*
1044  * set up BDL entries
1045  */
1046 static int azx_setup_periods(struct azx *chip,
1047                              struct snd_pcm_substream *substream,
1048                              struct azx_dev *azx_dev)
1049 {
1050         u32 *bdl;
1051         int i, ofs, periods, period_bytes;
1052         int pos_adj;
1053
1054         /* reset BDL address */
1055         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1056         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1057
1058         period_bytes = snd_pcm_lib_period_bytes(substream);
1059         azx_dev->period_bytes = period_bytes;
1060         periods = azx_dev->bufsize / period_bytes;
1061
1062         /* program the initial BDL entries */
1063         bdl = (u32 *)azx_dev->bdl.area;
1064         ofs = 0;
1065         azx_dev->frags = 0;
1066         azx_dev->irq_ignore = 0;
1067         pos_adj = bdl_pos_adj[chip->dev_index];
1068         if (pos_adj > 0) {
1069                 struct snd_pcm_runtime *runtime = substream->runtime;
1070                 int pos_align = pos_adj;
1071                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1072                 if (!pos_adj)
1073                         pos_adj = pos_align;
1074                 else
1075                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1076                                 pos_align;
1077                 pos_adj = frames_to_bytes(runtime, pos_adj);
1078                 if (pos_adj >= period_bytes) {
1079                         snd_printk(KERN_WARNING "Too big adjustment %d\n",
1080                                    bdl_pos_adj[chip->dev_index]);
1081                         pos_adj = 0;
1082                 } else {
1083                         ofs = setup_bdle(substream, azx_dev,
1084                                          &bdl, ofs, pos_adj, 1);
1085                         if (ofs < 0)
1086                                 goto error;
1087                         azx_dev->irq_ignore = 1;
1088                 }
1089         } else
1090                 pos_adj = 0;
1091         for (i = 0; i < periods; i++) {
1092                 if (i == periods - 1 && pos_adj)
1093                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1094                                          period_bytes - pos_adj, 0);
1095                 else
1096                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1097                                          period_bytes, 1);
1098                 if (ofs < 0)
1099                         goto error;
1100         }
1101         return 0;
1102
1103  error:
1104         snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1105                    azx_dev->bufsize, period_bytes);
1106         /* reset */
1107         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1108         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1109         return -EINVAL;
1110 }
1111
1112 /*
1113  * set up the SD for streaming
1114  */
1115 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1116 {
1117         unsigned char val;
1118         int timeout;
1119
1120         /* make sure the run bit is zero for SD */
1121         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1122                       ~SD_CTL_DMA_START);
1123         /* reset stream */
1124         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1125                       SD_CTL_STREAM_RESET);
1126         udelay(3);
1127         timeout = 300;
1128         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1129                --timeout)
1130                 ;
1131         val &= ~SD_CTL_STREAM_RESET;
1132         azx_sd_writeb(azx_dev, SD_CTL, val);
1133         udelay(3);
1134
1135         timeout = 300;
1136         /* waiting for hardware to report that the stream is out of reset */
1137         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1138                --timeout)
1139                 ;
1140
1141         /* program the stream_tag */
1142         azx_sd_writel(azx_dev, SD_CTL,
1143                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1144                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1145
1146         /* program the length of samples in cyclic buffer */
1147         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1148
1149         /* program the stream format */
1150         /* this value needs to be the same as the one programmed */
1151         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1152
1153         /* program the stream LVI (last valid index) of the BDL */
1154         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1155
1156         /* program the BDL address */
1157         /* lower BDL address */
1158         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1159         /* upper BDL address */
1160         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1161
1162         /* enable the position buffer */
1163         if (chip->position_fix == POS_FIX_POSBUF ||
1164             chip->position_fix == POS_FIX_AUTO ||
1165             chip->via_dmapos_patch) {
1166                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1167                         azx_writel(chip, DPLBASE,
1168                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1169         }
1170
1171         /* set the interrupt enable bits in the descriptor control register */
1172         azx_sd_writel(azx_dev, SD_CTL,
1173                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1174
1175         return 0;
1176 }
1177
1178 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1179                                  struct hda_pcm *cpcm);
1180
1181 /*
1182  * Codec initialization
1183  */
1184
1185 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1186 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1187         [AZX_DRIVER_TERA] = 1,
1188 };
1189
1190 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1191                                       unsigned int codec_probe_mask)
1192 {
1193         struct hda_bus_template bus_temp;
1194         int c, codecs, err;
1195         int max_slots;
1196
1197         memset(&bus_temp, 0, sizeof(bus_temp));
1198         bus_temp.private_data = chip;
1199         bus_temp.modelname = model;
1200         bus_temp.pci = chip->pci;
1201         bus_temp.ops.command = azx_send_cmd;
1202         bus_temp.ops.get_response = azx_get_response;
1203         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1204 #ifdef CONFIG_SND_HDA_POWER_SAVE
1205         bus_temp.ops.pm_notify = azx_power_notify;
1206 #endif
1207
1208         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1209         if (err < 0)
1210                 return err;
1211
1212         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1213                 chip->bus->needs_damn_long_delay = 1;
1214
1215         codecs = 0;
1216         max_slots = azx_max_codecs[chip->driver_type];
1217         if (!max_slots)
1218                 max_slots = AZX_MAX_CODECS;
1219         for (c = 0; c < max_slots; c++) {
1220                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1221                         struct hda_codec *codec;
1222                         err = snd_hda_codec_new(chip->bus, c, &codec);
1223                         if (err < 0)
1224                                 continue;
1225                         codecs++;
1226                 }
1227         }
1228         if (!codecs) {
1229                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1230                 return -ENXIO;
1231         }
1232
1233         return 0;
1234 }
1235
1236
1237 /*
1238  * PCM support
1239  */
1240
1241 /* assign a stream for the PCM */
1242 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1243 {
1244         int dev, i, nums;
1245         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1246                 dev = chip->playback_index_offset;
1247                 nums = chip->playback_streams;
1248         } else {
1249                 dev = chip->capture_index_offset;
1250                 nums = chip->capture_streams;
1251         }
1252         for (i = 0; i < nums; i++, dev++)
1253                 if (!chip->azx_dev[dev].opened) {
1254                         chip->azx_dev[dev].opened = 1;
1255                         return &chip->azx_dev[dev];
1256                 }
1257         return NULL;
1258 }
1259
1260 /* release the assigned stream */
1261 static inline void azx_release_device(struct azx_dev *azx_dev)
1262 {
1263         azx_dev->opened = 0;
1264 }
1265
1266 static struct snd_pcm_hardware azx_pcm_hw = {
1267         .info =                 (SNDRV_PCM_INFO_MMAP |
1268                                  SNDRV_PCM_INFO_INTERLEAVED |
1269                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1270                                  SNDRV_PCM_INFO_MMAP_VALID |
1271                                  /* No full-resume yet implemented */
1272                                  /* SNDRV_PCM_INFO_RESUME |*/
1273                                  SNDRV_PCM_INFO_PAUSE |
1274                                  SNDRV_PCM_INFO_SYNC_START),
1275         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1276         .rates =                SNDRV_PCM_RATE_48000,
1277         .rate_min =             48000,
1278         .rate_max =             48000,
1279         .channels_min =         2,
1280         .channels_max =         2,
1281         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1282         .period_bytes_min =     128,
1283         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1284         .periods_min =          2,
1285         .periods_max =          AZX_MAX_FRAG,
1286         .fifo_size =            0,
1287 };
1288
1289 struct azx_pcm {
1290         struct azx *chip;
1291         struct hda_codec *codec;
1292         struct hda_pcm_stream *hinfo[2];
1293 };
1294
1295 static int azx_pcm_open(struct snd_pcm_substream *substream)
1296 {
1297         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1298         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1299         struct azx *chip = apcm->chip;
1300         struct azx_dev *azx_dev;
1301         struct snd_pcm_runtime *runtime = substream->runtime;
1302         unsigned long flags;
1303         int err;
1304
1305         mutex_lock(&chip->open_mutex);
1306         azx_dev = azx_assign_device(chip, substream->stream);
1307         if (azx_dev == NULL) {
1308                 mutex_unlock(&chip->open_mutex);
1309                 return -EBUSY;
1310         }
1311         runtime->hw = azx_pcm_hw;
1312         runtime->hw.channels_min = hinfo->channels_min;
1313         runtime->hw.channels_max = hinfo->channels_max;
1314         runtime->hw.formats = hinfo->formats;
1315         runtime->hw.rates = hinfo->rates;
1316         snd_pcm_limit_hw_rates(runtime);
1317         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1318         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1319                                    128);
1320         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1321                                    128);
1322         snd_hda_power_up(apcm->codec);
1323         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1324         if (err < 0) {
1325                 azx_release_device(azx_dev);
1326                 snd_hda_power_down(apcm->codec);
1327                 mutex_unlock(&chip->open_mutex);
1328                 return err;
1329         }
1330         spin_lock_irqsave(&chip->reg_lock, flags);
1331         azx_dev->substream = substream;
1332         azx_dev->running = 0;
1333         spin_unlock_irqrestore(&chip->reg_lock, flags);
1334
1335         runtime->private_data = azx_dev;
1336         snd_pcm_set_sync(substream);
1337         mutex_unlock(&chip->open_mutex);
1338         return 0;
1339 }
1340
1341 static int azx_pcm_close(struct snd_pcm_substream *substream)
1342 {
1343         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1344         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1345         struct azx *chip = apcm->chip;
1346         struct azx_dev *azx_dev = get_azx_dev(substream);
1347         unsigned long flags;
1348
1349         mutex_lock(&chip->open_mutex);
1350         spin_lock_irqsave(&chip->reg_lock, flags);
1351         azx_dev->substream = NULL;
1352         azx_dev->running = 0;
1353         spin_unlock_irqrestore(&chip->reg_lock, flags);
1354         azx_release_device(azx_dev);
1355         hinfo->ops.close(hinfo, apcm->codec, substream);
1356         snd_hda_power_down(apcm->codec);
1357         mutex_unlock(&chip->open_mutex);
1358         return 0;
1359 }
1360
1361 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1362                              struct snd_pcm_hw_params *hw_params)
1363 {
1364         return snd_pcm_lib_malloc_pages(substream,
1365                                         params_buffer_bytes(hw_params));
1366 }
1367
1368 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1369 {
1370         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1371         struct azx_dev *azx_dev = get_azx_dev(substream);
1372         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1373
1374         /* reset BDL address */
1375         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1376         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1377         azx_sd_writel(azx_dev, SD_CTL, 0);
1378
1379         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1380
1381         return snd_pcm_lib_free_pages(substream);
1382 }
1383
1384 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1385 {
1386         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1387         struct azx *chip = apcm->chip;
1388         struct azx_dev *azx_dev = get_azx_dev(substream);
1389         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1390         struct snd_pcm_runtime *runtime = substream->runtime;
1391
1392         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1393         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1394                                                          runtime->channels,
1395                                                          runtime->format,
1396                                                          hinfo->maxbps);
1397         if (!azx_dev->format_val) {
1398                 snd_printk(KERN_ERR SFX
1399                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1400                            runtime->rate, runtime->channels, runtime->format);
1401                 return -EINVAL;
1402         }
1403
1404         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1405                     azx_dev->bufsize, azx_dev->format_val);
1406         if (azx_setup_periods(chip, substream, azx_dev) < 0)
1407                 return -EINVAL;
1408         azx_setup_controller(chip, azx_dev);
1409         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1410                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1411         else
1412                 azx_dev->fifo_size = 0;
1413
1414         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1415                                   azx_dev->format_val, substream);
1416 }
1417
1418 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1419 {
1420         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1421         struct azx *chip = apcm->chip;
1422         struct azx_dev *azx_dev;
1423         struct snd_pcm_substream *s;
1424         int start, nsync = 0, sbits = 0;
1425         int nwait, timeout;
1426
1427         switch (cmd) {
1428         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1429         case SNDRV_PCM_TRIGGER_RESUME:
1430         case SNDRV_PCM_TRIGGER_START:
1431                 start = 1;
1432                 break;
1433         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1434         case SNDRV_PCM_TRIGGER_SUSPEND:
1435         case SNDRV_PCM_TRIGGER_STOP:
1436                 start = 0;
1437                 break;
1438         default:
1439                 return -EINVAL;
1440         }
1441
1442         snd_pcm_group_for_each_entry(s, substream) {
1443                 if (s->pcm->card != substream->pcm->card)
1444                         continue;
1445                 azx_dev = get_azx_dev(s);
1446                 sbits |= 1 << azx_dev->index;
1447                 nsync++;
1448                 snd_pcm_trigger_done(s, substream);
1449         }
1450
1451         spin_lock(&chip->reg_lock);
1452         if (nsync > 1) {
1453                 /* first, set SYNC bits of corresponding streams */
1454                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1455         }
1456         snd_pcm_group_for_each_entry(s, substream) {
1457                 if (s->pcm->card != substream->pcm->card)
1458                         continue;
1459                 azx_dev = get_azx_dev(s);
1460                 if (start)
1461                         azx_stream_start(chip, azx_dev);
1462                 else
1463                         azx_stream_stop(chip, azx_dev);
1464                 azx_dev->running = start;
1465         }
1466         spin_unlock(&chip->reg_lock);
1467         if (start) {
1468                 if (nsync == 1)
1469                         return 0;
1470                 /* wait until all FIFOs get ready */
1471                 for (timeout = 5000; timeout; timeout--) {
1472                         nwait = 0;
1473                         snd_pcm_group_for_each_entry(s, substream) {
1474                                 if (s->pcm->card != substream->pcm->card)
1475                                         continue;
1476                                 azx_dev = get_azx_dev(s);
1477                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1478                                       SD_STS_FIFO_READY))
1479                                         nwait++;
1480                         }
1481                         if (!nwait)
1482                                 break;
1483                         cpu_relax();
1484                 }
1485         } else {
1486                 /* wait until all RUN bits are cleared */
1487                 for (timeout = 5000; timeout; timeout--) {
1488                         nwait = 0;
1489                         snd_pcm_group_for_each_entry(s, substream) {
1490                                 if (s->pcm->card != substream->pcm->card)
1491                                         continue;
1492                                 azx_dev = get_azx_dev(s);
1493                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1494                                     SD_CTL_DMA_START)
1495                                         nwait++;
1496                         }
1497                         if (!nwait)
1498                                 break;
1499                         cpu_relax();
1500                 }
1501         }
1502         if (nsync > 1) {
1503                 spin_lock(&chip->reg_lock);
1504                 /* reset SYNC bits */
1505                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1506                 spin_unlock(&chip->reg_lock);
1507         }
1508         return 0;
1509 }
1510
1511 /* get the current DMA position with correction on VIA chips */
1512 static unsigned int azx_via_get_position(struct azx *chip,
1513                                          struct azx_dev *azx_dev)
1514 {
1515         unsigned int link_pos, mini_pos, bound_pos;
1516         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1517         unsigned int fifo_size;
1518
1519         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1520         if (azx_dev->index >= 4) {
1521                 /* Playback, no problem using link position */
1522                 return link_pos;
1523         }
1524
1525         /* Capture */
1526         /* For new chipset,
1527          * use mod to get the DMA position just like old chipset
1528          */
1529         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1530         mod_dma_pos %= azx_dev->period_bytes;
1531
1532         /* azx_dev->fifo_size can't get FIFO size of in stream.
1533          * Get from base address + offset.
1534          */
1535         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1536
1537         if (azx_dev->insufficient) {
1538                 /* Link position never gather than FIFO size */
1539                 if (link_pos <= fifo_size)
1540                         return 0;
1541
1542                 azx_dev->insufficient = 0;
1543         }
1544
1545         if (link_pos <= fifo_size)
1546                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1547         else
1548                 mini_pos = link_pos - fifo_size;
1549
1550         /* Find nearest previous boudary */
1551         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1552         mod_link_pos = link_pos % azx_dev->period_bytes;
1553         if (mod_link_pos >= fifo_size)
1554                 bound_pos = link_pos - mod_link_pos;
1555         else if (mod_dma_pos >= mod_mini_pos)
1556                 bound_pos = mini_pos - mod_mini_pos;
1557         else {
1558                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1559                 if (bound_pos >= azx_dev->bufsize)
1560                         bound_pos = 0;
1561         }
1562
1563         /* Calculate real DMA position we want */
1564         return bound_pos + mod_dma_pos;
1565 }
1566
1567 static unsigned int azx_get_position(struct azx *chip,
1568                                      struct azx_dev *azx_dev)
1569 {
1570         unsigned int pos;
1571
1572         if (chip->via_dmapos_patch)
1573                 pos = azx_via_get_position(chip, azx_dev);
1574         else if (chip->position_fix == POS_FIX_POSBUF ||
1575                  chip->position_fix == POS_FIX_AUTO) {
1576                 /* use the position buffer */
1577                 pos = le32_to_cpu(*azx_dev->posbuf);
1578         } else {
1579                 /* read LPIB */
1580                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1581         }
1582         if (pos >= azx_dev->bufsize)
1583                 pos = 0;
1584         return pos;
1585 }
1586
1587 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1588 {
1589         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1590         struct azx *chip = apcm->chip;
1591         struct azx_dev *azx_dev = get_azx_dev(substream);
1592         return bytes_to_frames(substream->runtime,
1593                                azx_get_position(chip, azx_dev));
1594 }
1595
1596 /*
1597  * Check whether the current DMA position is acceptable for updating
1598  * periods.  Returns non-zero if it's OK.
1599  *
1600  * Many HD-audio controllers appear pretty inaccurate about
1601  * the update-IRQ timing.  The IRQ is issued before actually the
1602  * data is processed.  So, we need to process it afterwords in a
1603  * workqueue.
1604  */
1605 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1606 {
1607         unsigned int pos;
1608
1609         pos = azx_get_position(chip, azx_dev);
1610         if (chip->position_fix == POS_FIX_AUTO) {
1611                 if (!pos) {
1612                         printk(KERN_WARNING
1613                                "hda-intel: Invalid position buffer, "
1614                                "using LPIB read method instead.\n");
1615                         chip->position_fix = POS_FIX_LPIB;
1616                         pos = azx_get_position(chip, azx_dev);
1617                 } else
1618                         chip->position_fix = POS_FIX_POSBUF;
1619         }
1620
1621         if (!bdl_pos_adj[chip->dev_index])
1622                 return 1; /* no delayed ack */
1623         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1624                 return 0; /* NG - it's below the period boundary */
1625         return 1; /* OK, it's fine */
1626 }
1627
1628 /*
1629  * The work for pending PCM period updates.
1630  */
1631 static void azx_irq_pending_work(struct work_struct *work)
1632 {
1633         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1634         int i, pending;
1635
1636         if (!chip->irq_pending_warned) {
1637                 printk(KERN_WARNING
1638                        "hda-intel: IRQ timing workaround is activated "
1639                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1640                        chip->card->number);
1641                 chip->irq_pending_warned = 1;
1642         }
1643
1644         for (;;) {
1645                 pending = 0;
1646                 spin_lock_irq(&chip->reg_lock);
1647                 for (i = 0; i < chip->num_streams; i++) {
1648                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1649                         if (!azx_dev->irq_pending ||
1650                             !azx_dev->substream ||
1651                             !azx_dev->running)
1652                                 continue;
1653                         if (azx_position_ok(chip, azx_dev)) {
1654                                 azx_dev->irq_pending = 0;
1655                                 spin_unlock(&chip->reg_lock);
1656                                 snd_pcm_period_elapsed(azx_dev->substream);
1657                                 spin_lock(&chip->reg_lock);
1658                         } else
1659                                 pending++;
1660                 }
1661                 spin_unlock_irq(&chip->reg_lock);
1662                 if (!pending)
1663                         return;
1664                 cond_resched();
1665         }
1666 }
1667
1668 /* clear irq_pending flags and assure no on-going workq */
1669 static void azx_clear_irq_pending(struct azx *chip)
1670 {
1671         int i;
1672
1673         spin_lock_irq(&chip->reg_lock);
1674         for (i = 0; i < chip->num_streams; i++)
1675                 chip->azx_dev[i].irq_pending = 0;
1676         spin_unlock_irq(&chip->reg_lock);
1677         flush_scheduled_work();
1678 }
1679
1680 static struct snd_pcm_ops azx_pcm_ops = {
1681         .open = azx_pcm_open,
1682         .close = azx_pcm_close,
1683         .ioctl = snd_pcm_lib_ioctl,
1684         .hw_params = azx_pcm_hw_params,
1685         .hw_free = azx_pcm_hw_free,
1686         .prepare = azx_pcm_prepare,
1687         .trigger = azx_pcm_trigger,
1688         .pointer = azx_pcm_pointer,
1689         .page = snd_pcm_sgbuf_ops_page,
1690 };
1691
1692 static void azx_pcm_free(struct snd_pcm *pcm)
1693 {
1694         struct azx_pcm *apcm = pcm->private_data;
1695         if (apcm) {
1696                 apcm->chip->pcm[pcm->device] = NULL;
1697                 kfree(apcm);
1698         }
1699 }
1700
1701 static int
1702 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1703                       struct hda_pcm *cpcm)
1704 {
1705         struct azx *chip = bus->private_data;
1706         struct snd_pcm *pcm;
1707         struct azx_pcm *apcm;
1708         int pcm_dev = cpcm->device;
1709         int s, err;
1710
1711         if (pcm_dev >= AZX_MAX_PCMS) {
1712                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1713                            pcm_dev);
1714                 return -EINVAL;
1715         }
1716         if (chip->pcm[pcm_dev]) {
1717                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1718                 return -EBUSY;
1719         }
1720         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1721                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1722                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1723                           &pcm);
1724         if (err < 0)
1725                 return err;
1726         strcpy(pcm->name, cpcm->name);
1727         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1728         if (apcm == NULL)
1729                 return -ENOMEM;
1730         apcm->chip = chip;
1731         apcm->codec = codec;
1732         pcm->private_data = apcm;
1733         pcm->private_free = azx_pcm_free;
1734         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1735                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1736         chip->pcm[pcm_dev] = pcm;
1737         cpcm->pcm = pcm;
1738         for (s = 0; s < 2; s++) {
1739                 apcm->hinfo[s] = &cpcm->stream[s];
1740                 if (cpcm->stream[s].substreams)
1741                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1742         }
1743         /* buffer pre-allocation */
1744         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1745                                               snd_dma_pci_data(chip->pci),
1746                                               1024 * 64, 32 * 1024 * 1024);
1747         return 0;
1748 }
1749
1750 /*
1751  * mixer creation - all stuff is implemented in hda module
1752  */
1753 static int __devinit azx_mixer_create(struct azx *chip)
1754 {
1755         return snd_hda_build_controls(chip->bus);
1756 }
1757
1758
1759 /*
1760  * initialize SD streams
1761  */
1762 static int __devinit azx_init_stream(struct azx *chip)
1763 {
1764         int i;
1765
1766         /* initialize each stream (aka device)
1767          * assign the starting bdl address to each stream (device)
1768          * and initialize
1769          */
1770         for (i = 0; i < chip->num_streams; i++) {
1771                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1772                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1773                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1774                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1775                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1776                 azx_dev->sd_int_sta_mask = 1 << i;
1777                 /* stream tag: must be non-zero and unique */
1778                 azx_dev->index = i;
1779                 azx_dev->stream_tag = i + 1;
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1786 {
1787         if (request_irq(chip->pci->irq, azx_interrupt,
1788                         chip->msi ? 0 : IRQF_SHARED,
1789                         "HDA Intel", chip)) {
1790                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1791                        "disabling device\n", chip->pci->irq);
1792                 if (do_disconnect)
1793                         snd_card_disconnect(chip->card);
1794                 return -1;
1795         }
1796         chip->irq = chip->pci->irq;
1797         pci_intx(chip->pci, !chip->msi);
1798         return 0;
1799 }
1800
1801
1802 static void azx_stop_chip(struct azx *chip)
1803 {
1804         if (!chip->initialized)
1805                 return;
1806
1807         /* disable interrupts */
1808         azx_int_disable(chip);
1809         azx_int_clear(chip);
1810
1811         /* disable CORB/RIRB */
1812         azx_free_cmd_io(chip);
1813
1814         /* disable position buffer */
1815         azx_writel(chip, DPLBASE, 0);
1816         azx_writel(chip, DPUBASE, 0);
1817
1818         chip->initialized = 0;
1819 }
1820
1821 #ifdef CONFIG_SND_HDA_POWER_SAVE
1822 /* power-up/down the controller */
1823 static void azx_power_notify(struct hda_bus *bus)
1824 {
1825         struct azx *chip = bus->private_data;
1826         struct hda_codec *c;
1827         int power_on = 0;
1828
1829         list_for_each_entry(c, &bus->codec_list, list) {
1830                 if (c->power_on) {
1831                         power_on = 1;
1832                         break;
1833                 }
1834         }
1835         if (power_on)
1836                 azx_init_chip(chip);
1837         else if (chip->running && power_save_controller)
1838                 azx_stop_chip(chip);
1839 }
1840 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1841
1842 #ifdef CONFIG_PM
1843 /*
1844  * power management
1845  */
1846 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1847 {
1848         struct snd_card *card = pci_get_drvdata(pci);
1849         struct azx *chip = card->private_data;
1850         int i;
1851
1852         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1853         azx_clear_irq_pending(chip);
1854         for (i = 0; i < AZX_MAX_PCMS; i++)
1855                 snd_pcm_suspend_all(chip->pcm[i]);
1856         if (chip->initialized)
1857                 snd_hda_suspend(chip->bus, state);
1858         azx_stop_chip(chip);
1859         if (chip->irq >= 0) {
1860                 free_irq(chip->irq, chip);
1861                 chip->irq = -1;
1862         }
1863         if (chip->msi)
1864                 pci_disable_msi(chip->pci);
1865         pci_disable_device(pci);
1866         pci_save_state(pci);
1867         pci_set_power_state(pci, pci_choose_state(pci, state));
1868         return 0;
1869 }
1870
1871 static int azx_resume(struct pci_dev *pci)
1872 {
1873         struct snd_card *card = pci_get_drvdata(pci);
1874         struct azx *chip = card->private_data;
1875
1876         pci_set_power_state(pci, PCI_D0);
1877         pci_restore_state(pci);
1878         if (pci_enable_device(pci) < 0) {
1879                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1880                        "disabling device\n");
1881                 snd_card_disconnect(card);
1882                 return -EIO;
1883         }
1884         pci_set_master(pci);
1885         if (chip->msi)
1886                 if (pci_enable_msi(pci) < 0)
1887                         chip->msi = 0;
1888         if (azx_acquire_irq(chip, 1) < 0)
1889                 return -EIO;
1890         azx_init_pci(chip);
1891
1892         if (snd_hda_codecs_inuse(chip->bus))
1893                 azx_init_chip(chip);
1894
1895         snd_hda_resume(chip->bus);
1896         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1897         return 0;
1898 }
1899 #endif /* CONFIG_PM */
1900
1901
1902 /*
1903  * reboot notifier for hang-up problem at power-down
1904  */
1905 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1906 {
1907         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1908         azx_stop_chip(chip);
1909         return NOTIFY_OK;
1910 }
1911
1912 static void azx_notifier_register(struct azx *chip)
1913 {
1914         chip->reboot_notifier.notifier_call = azx_halt;
1915         register_reboot_notifier(&chip->reboot_notifier);
1916 }
1917
1918 static void azx_notifier_unregister(struct azx *chip)
1919 {
1920         if (chip->reboot_notifier.notifier_call)
1921                 unregister_reboot_notifier(&chip->reboot_notifier);
1922 }
1923
1924 /*
1925  * destructor
1926  */
1927 static int azx_free(struct azx *chip)
1928 {
1929         int i;
1930
1931         azx_notifier_unregister(chip);
1932
1933         if (chip->initialized) {
1934                 azx_clear_irq_pending(chip);
1935                 for (i = 0; i < chip->num_streams; i++)
1936                         azx_stream_stop(chip, &chip->azx_dev[i]);
1937                 azx_stop_chip(chip);
1938         }
1939
1940         if (chip->irq >= 0)
1941                 free_irq(chip->irq, (void*)chip);
1942         if (chip->msi)
1943                 pci_disable_msi(chip->pci);
1944         if (chip->remap_addr)
1945                 iounmap(chip->remap_addr);
1946
1947         if (chip->azx_dev) {
1948                 for (i = 0; i < chip->num_streams; i++)
1949                         if (chip->azx_dev[i].bdl.area)
1950                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1951         }
1952         if (chip->rb.area)
1953                 snd_dma_free_pages(&chip->rb);
1954         if (chip->posbuf.area)
1955                 snd_dma_free_pages(&chip->posbuf);
1956         pci_release_regions(chip->pci);
1957         pci_disable_device(chip->pci);
1958         kfree(chip->azx_dev);
1959         kfree(chip);
1960
1961         return 0;
1962 }
1963
1964 static int azx_dev_free(struct snd_device *device)
1965 {
1966         return azx_free(device->device_data);
1967 }
1968
1969 /*
1970  * white/black-listing for position_fix
1971  */
1972 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1973         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1974         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1975         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1976         {}
1977 };
1978
1979 static int __devinit check_position_fix(struct azx *chip, int fix)
1980 {
1981         const struct snd_pci_quirk *q;
1982
1983         /* Check VIA HD Audio Controller exist */
1984         if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
1985             chip->pci->device == VIA_HDAC_DEVICE_ID) {
1986                 chip->via_dmapos_patch = 1;
1987                 /* Use link position directly, avoid any transfer problem. */
1988                 return POS_FIX_LPIB;
1989         }
1990         chip->via_dmapos_patch = 0;
1991
1992         if (fix == POS_FIX_AUTO) {
1993                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1994                 if (q) {
1995                         printk(KERN_INFO
1996                                     "hda_intel: position_fix set to %d "
1997                                     "for device %04x:%04x\n",
1998                                     q->value, q->subvendor, q->subdevice);
1999                         return q->value;
2000                 }
2001         }
2002         return fix;
2003 }
2004
2005 /*
2006  * black-lists for probe_mask
2007  */
2008 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2009         /* Thinkpad often breaks the controller communication when accessing
2010          * to the non-working (or non-existing) modem codec slot.
2011          */
2012         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2013         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2014         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2015         {}
2016 };
2017
2018 static void __devinit check_probe_mask(struct azx *chip, int dev)
2019 {
2020         const struct snd_pci_quirk *q;
2021
2022         if (probe_mask[dev] == -1) {
2023                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2024                 if (q) {
2025                         printk(KERN_INFO
2026                                "hda_intel: probe_mask set to 0x%x "
2027                                "for device %04x:%04x\n",
2028                                q->value, q->subvendor, q->subdevice);
2029                         probe_mask[dev] = q->value;
2030                 }
2031         }
2032 }
2033
2034
2035 /*
2036  * constructor
2037  */
2038 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2039                                 int dev, int driver_type,
2040                                 struct azx **rchip)
2041 {
2042         struct azx *chip;
2043         int i, err;
2044         unsigned short gcap;
2045         static struct snd_device_ops ops = {
2046                 .dev_free = azx_dev_free,
2047         };
2048
2049         *rchip = NULL;
2050
2051         err = pci_enable_device(pci);
2052         if (err < 0)
2053                 return err;
2054
2055         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2056         if (!chip) {
2057                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2058                 pci_disable_device(pci);
2059                 return -ENOMEM;
2060         }
2061
2062         spin_lock_init(&chip->reg_lock);
2063         mutex_init(&chip->open_mutex);
2064         chip->card = card;
2065         chip->pci = pci;
2066         chip->irq = -1;
2067         chip->driver_type = driver_type;
2068         chip->msi = enable_msi;
2069         chip->dev_index = dev;
2070         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2071
2072         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2073         check_probe_mask(chip, dev);
2074
2075         chip->single_cmd = single_cmd;
2076
2077         if (bdl_pos_adj[dev] < 0) {
2078                 switch (chip->driver_type) {
2079                 case AZX_DRIVER_ICH:
2080                         bdl_pos_adj[dev] = 1;
2081                         break;
2082                 default:
2083                         bdl_pos_adj[dev] = 32;
2084                         break;
2085                 }
2086         }
2087
2088 #if BITS_PER_LONG != 64
2089         /* Fix up base address on ULI M5461 */
2090         if (chip->driver_type == AZX_DRIVER_ULI) {
2091                 u16 tmp3;
2092                 pci_read_config_word(pci, 0x40, &tmp3);
2093                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2094                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2095         }
2096 #endif
2097
2098         err = pci_request_regions(pci, "ICH HD audio");
2099         if (err < 0) {
2100                 kfree(chip);
2101                 pci_disable_device(pci);
2102                 return err;
2103         }
2104
2105         chip->addr = pci_resource_start(pci, 0);
2106         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2107         if (chip->remap_addr == NULL) {
2108                 snd_printk(KERN_ERR SFX "ioremap error\n");
2109                 err = -ENXIO;
2110                 goto errout;
2111         }
2112
2113         if (chip->msi)
2114                 if (pci_enable_msi(pci) < 0)
2115                         chip->msi = 0;
2116
2117         if (azx_acquire_irq(chip, 0) < 0) {
2118                 err = -EBUSY;
2119                 goto errout;
2120         }
2121
2122         pci_set_master(pci);
2123         synchronize_irq(chip->irq);
2124
2125         gcap = azx_readw(chip, GCAP);
2126         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2127
2128         /* allow 64bit DMA address if supported by H/W */
2129         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2130                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2131
2132         /* read number of streams from GCAP register instead of using
2133          * hardcoded value
2134          */
2135         chip->capture_streams = (gcap >> 8) & 0x0f;
2136         chip->playback_streams = (gcap >> 12) & 0x0f;
2137         if (!chip->playback_streams && !chip->capture_streams) {
2138                 /* gcap didn't give any info, switching to old method */
2139
2140                 switch (chip->driver_type) {
2141                 case AZX_DRIVER_ULI:
2142                         chip->playback_streams = ULI_NUM_PLAYBACK;
2143                         chip->capture_streams = ULI_NUM_CAPTURE;
2144                         break;
2145                 case AZX_DRIVER_ATIHDMI:
2146                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2147                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2148                         break;
2149                 default:
2150                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2151                         chip->capture_streams = ICH6_NUM_CAPTURE;
2152                         break;
2153                 }
2154         }
2155         chip->capture_index_offset = 0;
2156         chip->playback_index_offset = chip->capture_streams;
2157         chip->num_streams = chip->playback_streams + chip->capture_streams;
2158         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2159                                 GFP_KERNEL);
2160         if (!chip->azx_dev) {
2161                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2162                 goto errout;
2163         }
2164
2165         for (i = 0; i < chip->num_streams; i++) {
2166                 /* allocate memory for the BDL for each stream */
2167                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2168                                           snd_dma_pci_data(chip->pci),
2169                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2170                 if (err < 0) {
2171                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2172                         goto errout;
2173                 }
2174         }
2175         /* allocate memory for the position buffer */
2176         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2177                                   snd_dma_pci_data(chip->pci),
2178                                   chip->num_streams * 8, &chip->posbuf);
2179         if (err < 0) {
2180                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2181                 goto errout;
2182         }
2183         /* allocate CORB/RIRB */
2184         if (!chip->single_cmd) {
2185                 err = azx_alloc_cmd_io(chip);
2186                 if (err < 0)
2187                         goto errout;
2188         }
2189
2190         /* initialize streams */
2191         azx_init_stream(chip);
2192
2193         /* initialize chip */
2194         azx_init_pci(chip);
2195         azx_init_chip(chip);
2196
2197         /* codec detection */
2198         if (!chip->codec_mask) {
2199                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2200                 err = -ENODEV;
2201                 goto errout;
2202         }
2203
2204         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2205         if (err <0) {
2206                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2207                 goto errout;
2208         }
2209
2210         strcpy(card->driver, "HDA-Intel");
2211         strcpy(card->shortname, driver_short_names[chip->driver_type]);
2212         sprintf(card->longname, "%s at 0x%lx irq %i",
2213                 card->shortname, chip->addr, chip->irq);
2214
2215         *rchip = chip;
2216         return 0;
2217
2218  errout:
2219         azx_free(chip);
2220         return err;
2221 }
2222
2223 static void power_down_all_codecs(struct azx *chip)
2224 {
2225 #ifdef CONFIG_SND_HDA_POWER_SAVE
2226         /* The codecs were powered up in snd_hda_codec_new().
2227          * Now all initialization done, so turn them down if possible
2228          */
2229         struct hda_codec *codec;
2230         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2231                 snd_hda_power_down(codec);
2232         }
2233 #endif
2234 }
2235
2236 static int __devinit azx_probe(struct pci_dev *pci,
2237                                const struct pci_device_id *pci_id)
2238 {
2239         static int dev;
2240         struct snd_card *card;
2241         struct azx *chip;
2242         int err;
2243
2244         if (dev >= SNDRV_CARDS)
2245                 return -ENODEV;
2246         if (!enable[dev]) {
2247                 dev++;
2248                 return -ENOENT;
2249         }
2250
2251         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2252         if (!card) {
2253                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2254                 return -ENOMEM;
2255         }
2256
2257         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2258         if (err < 0) {
2259                 snd_card_free(card);
2260                 return err;
2261         }
2262         card->private_data = chip;
2263
2264         /* create codec instances */
2265         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2266         if (err < 0) {
2267                 snd_card_free(card);
2268                 return err;
2269         }
2270
2271         /* create PCM streams */
2272         err = snd_hda_build_pcms(chip->bus);
2273         if (err < 0) {
2274                 snd_card_free(card);
2275                 return err;
2276         }
2277
2278         /* create mixer controls */
2279         err = azx_mixer_create(chip);
2280         if (err < 0) {
2281                 snd_card_free(card);
2282                 return err;
2283         }
2284
2285         snd_card_set_dev(card, &pci->dev);
2286
2287         err = snd_card_register(card);
2288         if (err < 0) {
2289                 snd_card_free(card);
2290                 return err;
2291         }
2292
2293         pci_set_drvdata(pci, card);
2294         chip->running = 1;
2295         power_down_all_codecs(chip);
2296         azx_notifier_register(chip);
2297
2298         dev++;
2299         return err;
2300 }
2301
2302 static void __devexit azx_remove(struct pci_dev *pci)
2303 {
2304         snd_card_free(pci_get_drvdata(pci));
2305         pci_set_drvdata(pci, NULL);
2306 }
2307
2308 /* PCI IDs */
2309 static struct pci_device_id azx_ids[] = {
2310         /* ICH 6..10 */
2311         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2312         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2313         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2314         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2315         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2316         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2317         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2318         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2319         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2320         /* PCH */
2321         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2322         /* SCH */
2323         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2324         /* ATI SB 450/600 */
2325         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2326         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2327         /* ATI HDMI */
2328         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2329         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2330         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2331         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2332         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2333         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2334         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2335         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2336         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2337         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2338         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2339         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2340         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2341         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2342         /* VIA VT8251/VT8237A */
2343         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2344         /* SIS966 */
2345         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2346         /* ULI M5461 */
2347         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2348         /* NVIDIA MCP */
2349         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2350         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2351         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2352         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2353         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2354         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2355         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2356         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2357         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2358         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2359         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2360         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2361         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2362         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2363         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2364         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2365         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2366         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2367         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2368         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2369         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2370         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2371         /* Teradici */
2372         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2373         { 0, }
2374 };
2375 MODULE_DEVICE_TABLE(pci, azx_ids);
2376
2377 /* pci_driver definition */
2378 static struct pci_driver driver = {
2379         .name = "HDA Intel",
2380         .id_table = azx_ids,
2381         .probe = azx_probe,
2382         .remove = __devexit_p(azx_remove),
2383 #ifdef CONFIG_PM
2384         .suspend = azx_suspend,
2385         .resume = azx_resume,
2386 #endif
2387 };
2388
2389 static int __init alsa_card_azx_init(void)
2390 {
2391         return pci_register_driver(&driver);
2392 }
2393
2394 static void __exit alsa_card_azx_exit(void)
2395 {
2396         pci_unregister_driver(&driver);
2397 }
2398
2399 module_init(alsa_card_azx_init)
2400 module_exit(alsa_card_azx_exit)