3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56 static char *model[SNDRV_CARDS];
57 static int position_fix[SNDRV_CARDS];
58 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
59 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int single_cmd;
61 static int enable_msi;
63 module_param_array(index, int, NULL, 0444);
64 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
65 module_param_array(id, charp, NULL, 0444);
66 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
67 module_param_array(enable, bool, NULL, 0444);
68 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
69 module_param_array(model, charp, NULL, 0444);
70 MODULE_PARM_DESC(model, "Use the given board model.");
71 module_param_array(position_fix, int, NULL, 0444);
72 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
73 "(0 = auto, 1 = none, 2 = POSBUF).");
74 module_param_array(bdl_pos_adj, int, NULL, 0644);
75 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
76 module_param_array(probe_mask, int, NULL, 0444);
77 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
78 module_param(single_cmd, bool, 0444);
79 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
80 "(for debugging only).");
81 module_param(enable_msi, int, 0444);
82 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
84 #ifdef CONFIG_SND_HDA_POWER_SAVE
85 /* power_save option is defined in hda_codec.c */
87 /* reset the HD-audio controller in power save mode.
88 * this may give more power-saving, but will take longer time to
91 static int power_save_controller = 1;
92 module_param(power_save_controller, bool, 0644);
93 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
96 MODULE_LICENSE("GPL");
97 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
122 MODULE_DESCRIPTION("Intel HDA driver");
124 #define SFX "hda-intel: "
130 #define ICH6_REG_GCAP 0x00
131 #define ICH6_REG_VMIN 0x02
132 #define ICH6_REG_VMAJ 0x03
133 #define ICH6_REG_OUTPAY 0x04
134 #define ICH6_REG_INPAY 0x06
135 #define ICH6_REG_GCTL 0x08
136 #define ICH6_REG_WAKEEN 0x0c
137 #define ICH6_REG_STATESTS 0x0e
138 #define ICH6_REG_GSTS 0x10
139 #define ICH6_REG_INTCTL 0x20
140 #define ICH6_REG_INTSTS 0x24
141 #define ICH6_REG_WALCLK 0x30
142 #define ICH6_REG_SYNC 0x34
143 #define ICH6_REG_CORBLBASE 0x40
144 #define ICH6_REG_CORBUBASE 0x44
145 #define ICH6_REG_CORBWP 0x48
146 #define ICH6_REG_CORBRP 0x4A
147 #define ICH6_REG_CORBCTL 0x4c
148 #define ICH6_REG_CORBSTS 0x4d
149 #define ICH6_REG_CORBSIZE 0x4e
151 #define ICH6_REG_RIRBLBASE 0x50
152 #define ICH6_REG_RIRBUBASE 0x54
153 #define ICH6_REG_RIRBWP 0x58
154 #define ICH6_REG_RINTCNT 0x5a
155 #define ICH6_REG_RIRBCTL 0x5c
156 #define ICH6_REG_RIRBSTS 0x5d
157 #define ICH6_REG_RIRBSIZE 0x5e
159 #define ICH6_REG_IC 0x60
160 #define ICH6_REG_IR 0x64
161 #define ICH6_REG_IRS 0x68
162 #define ICH6_IRS_VALID (1<<1)
163 #define ICH6_IRS_BUSY (1<<0)
165 #define ICH6_REG_DPLBASE 0x70
166 #define ICH6_REG_DPUBASE 0x74
167 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
169 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
170 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
172 /* stream register offsets from stream base */
173 #define ICH6_REG_SD_CTL 0x00
174 #define ICH6_REG_SD_STS 0x03
175 #define ICH6_REG_SD_LPIB 0x04
176 #define ICH6_REG_SD_CBL 0x08
177 #define ICH6_REG_SD_LVI 0x0c
178 #define ICH6_REG_SD_FIFOW 0x0e
179 #define ICH6_REG_SD_FIFOSIZE 0x10
180 #define ICH6_REG_SD_FORMAT 0x12
181 #define ICH6_REG_SD_BDLPL 0x18
182 #define ICH6_REG_SD_BDLPU 0x1c
185 #define ICH6_PCIREG_TCSEL 0x44
191 /* max number of SDs */
192 /* ICH, ATI and VIA have 4 playback and 4 capture */
193 #define ICH6_NUM_CAPTURE 4
194 #define ICH6_NUM_PLAYBACK 4
196 /* ULI has 6 playback and 5 capture */
197 #define ULI_NUM_CAPTURE 5
198 #define ULI_NUM_PLAYBACK 6
200 /* ATI HDMI has 1 playback and 0 capture */
201 #define ATIHDMI_NUM_CAPTURE 0
202 #define ATIHDMI_NUM_PLAYBACK 1
204 /* TERA has 4 playback and 3 capture */
205 #define TERA_NUM_CAPTURE 3
206 #define TERA_NUM_PLAYBACK 4
208 /* this number is statically defined for simplicity */
209 #define MAX_AZX_DEV 16
211 /* max number of fragments - we may use more if allocating more pages for BDL */
212 #define BDL_SIZE 4096
213 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
214 #define AZX_MAX_FRAG 32
215 /* max buffer size - no h/w limit, you can increase as you like */
216 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
217 /* max number of PCM devics per card */
218 #define AZX_MAX_PCMS 8
220 /* RIRB int mask: overrun[2], response[0] */
221 #define RIRB_INT_RESPONSE 0x01
222 #define RIRB_INT_OVERRUN 0x04
223 #define RIRB_INT_MASK 0x05
225 /* STATESTS int mask: S3,SD2,SD1,SD0 */
226 #define AZX_MAX_CODECS 4
227 #define STATESTS_INT_MASK 0x0f
230 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
231 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
232 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
233 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
234 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
235 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
236 #define SD_CTL_STREAM_TAG_SHIFT 20
238 /* SD_CTL and SD_STS */
239 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
240 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
241 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
242 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
246 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
248 /* INTCTL and INTSTS */
249 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
250 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
251 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
253 /* GCTL unsolicited response enable bit */
254 #define ICH6_GCTL_UREN (1<<8)
257 #define ICH6_GCTL_RESET (1<<0)
259 /* CORB/RIRB control, read/write pointer */
260 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
261 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
262 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
263 /* below are so far hardcoded - should read registers in future */
264 #define ICH6_MAX_CORB_ENTRIES 256
265 #define ICH6_MAX_RIRB_ENTRIES 256
267 /* position fix mode */
274 /* Defines for ATI HD Audio support in SB450 south bridge */
275 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
276 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
278 /* Defines for Nvidia HDA support */
279 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
280 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
281 #define NVIDIA_HDA_ISTRM_COH 0x4d
282 #define NVIDIA_HDA_OSTRM_COH 0x4c
283 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
285 /* Defines for Intel SCH HDA snoop control */
286 #define INTEL_SCH_HDA_DEVC 0x78
287 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
289 /* Define IN stream 0 FIFO size offset in VIA controller */
290 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
291 /* Define VIA HD Audio Device ID*/
292 #define VIA_HDAC_DEVICE_ID 0x3288
299 struct snd_dma_buffer bdl; /* BDL buffer */
300 u32 *posbuf; /* position buffer pointer */
302 unsigned int bufsize; /* size of the play buffer in bytes */
303 unsigned int period_bytes; /* size of the period in bytes */
304 unsigned int frags; /* number for period in the play buffer */
305 unsigned int fifo_size; /* FIFO size */
307 void __iomem *sd_addr; /* stream descriptor pointer */
309 u32 sd_int_sta_mask; /* stream int status mask */
312 struct snd_pcm_substream *substream; /* assigned substream,
315 unsigned int format_val; /* format value to be set in the
316 * controller and the codec
318 unsigned char stream_tag; /* assigned stream */
319 unsigned char index; /* stream index */
321 unsigned int opened :1;
322 unsigned int running :1;
323 unsigned int irq_pending :1;
324 unsigned int irq_ignore :1;
327 * A flag to ensure DMA position is 0
328 * when link position is not greater than FIFO size
330 unsigned int insufficient :1;
335 u32 *buf; /* CORB/RIRB buffer
336 * Each CORB entry is 4byte, RIRB is 8byte
338 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
340 unsigned short rp, wp; /* read/write pointers */
341 int cmds; /* number of pending requests */
342 u32 res; /* last read value */
346 struct snd_card *card;
350 /* chip type specific */
352 int playback_streams;
353 int playback_index_offset;
355 int capture_index_offset;
360 void __iomem *remap_addr;
365 struct mutex open_mutex;
367 /* streams (x num_streams) */
368 struct azx_dev *azx_dev;
371 struct snd_pcm *pcm[AZX_MAX_PCMS];
374 unsigned short codec_mask;
381 /* CORB/RIRB and position buffers */
382 struct snd_dma_buffer rb;
383 struct snd_dma_buffer posbuf;
387 unsigned int running :1;
388 unsigned int initialized :1;
389 unsigned int single_cmd :1;
390 unsigned int polling_mode :1;
392 unsigned int irq_pending_warned :1;
393 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
396 unsigned int last_cmd; /* last issued command (to sync) */
398 /* for pending irqs */
399 struct work_struct irq_pending_work;
413 AZX_NUM_DRIVERS, /* keep this as last entry */
416 static char *driver_short_names[] __devinitdata = {
417 [AZX_DRIVER_ICH] = "HDA Intel",
418 [AZX_DRIVER_SCH] = "HDA Intel MID",
419 [AZX_DRIVER_ATI] = "HDA ATI SB",
420 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
421 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
422 [AZX_DRIVER_SIS] = "HDA SIS966",
423 [AZX_DRIVER_ULI] = "HDA ULI M5461",
424 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
425 [AZX_DRIVER_TERA] = "HDA Teradici",
429 * macros for easy use
431 #define azx_writel(chip,reg,value) \
432 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
433 #define azx_readl(chip,reg) \
434 readl((chip)->remap_addr + ICH6_REG_##reg)
435 #define azx_writew(chip,reg,value) \
436 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
437 #define azx_readw(chip,reg) \
438 readw((chip)->remap_addr + ICH6_REG_##reg)
439 #define azx_writeb(chip,reg,value) \
440 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
441 #define azx_readb(chip,reg) \
442 readb((chip)->remap_addr + ICH6_REG_##reg)
444 #define azx_sd_writel(dev,reg,value) \
445 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
446 #define azx_sd_readl(dev,reg) \
447 readl((dev)->sd_addr + ICH6_REG_##reg)
448 #define azx_sd_writew(dev,reg,value) \
449 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
450 #define azx_sd_readw(dev,reg) \
451 readw((dev)->sd_addr + ICH6_REG_##reg)
452 #define azx_sd_writeb(dev,reg,value) \
453 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
454 #define azx_sd_readb(dev,reg) \
455 readb((dev)->sd_addr + ICH6_REG_##reg)
457 /* for pcm support */
458 #define get_azx_dev(substream) (substream->runtime->private_data)
460 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
463 * Interface for HD codec
467 * CORB / RIRB interface
469 static int azx_alloc_cmd_io(struct azx *chip)
473 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
474 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
475 snd_dma_pci_data(chip->pci),
476 PAGE_SIZE, &chip->rb);
478 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
484 static void azx_init_cmd_io(struct azx *chip)
487 chip->corb.addr = chip->rb.addr;
488 chip->corb.buf = (u32 *)chip->rb.area;
489 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
490 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
492 /* set the corb size to 256 entries (ULI requires explicitly) */
493 azx_writeb(chip, CORBSIZE, 0x02);
494 /* set the corb write pointer to 0 */
495 azx_writew(chip, CORBWP, 0);
496 /* reset the corb hw read pointer */
497 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
498 /* enable corb dma */
499 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
502 chip->rirb.addr = chip->rb.addr + 2048;
503 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
504 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
505 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
507 /* set the rirb size to 256 entries (ULI requires explicitly) */
508 azx_writeb(chip, RIRBSIZE, 0x02);
509 /* reset the rirb hw write pointer */
510 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
511 /* set N=1, get RIRB response interrupt for new entry */
512 azx_writew(chip, RINTCNT, 1);
513 /* enable rirb dma and response irq */
514 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
515 chip->rirb.rp = chip->rirb.cmds = 0;
518 static void azx_free_cmd_io(struct azx *chip)
520 /* disable ringbuffer DMAs */
521 azx_writeb(chip, RIRBCTL, 0);
522 azx_writeb(chip, CORBCTL, 0);
526 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
528 struct azx *chip = codec->bus->private_data;
531 /* add command to corb */
532 wp = azx_readb(chip, CORBWP);
534 wp %= ICH6_MAX_CORB_ENTRIES;
536 spin_lock_irq(&chip->reg_lock);
538 chip->corb.buf[wp] = cpu_to_le32(val);
539 azx_writel(chip, CORBWP, wp);
540 spin_unlock_irq(&chip->reg_lock);
545 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
547 /* retrieve RIRB entry - called from interrupt handler */
548 static void azx_update_rirb(struct azx *chip)
553 wp = azx_readb(chip, RIRBWP);
554 if (wp == chip->rirb.wp)
558 while (chip->rirb.rp != wp) {
560 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
562 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
563 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
564 res = le32_to_cpu(chip->rirb.buf[rp]);
565 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
566 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
567 else if (chip->rirb.cmds) {
568 chip->rirb.res = res;
575 /* receive a response */
576 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
578 struct azx *chip = codec->bus->private_data;
579 unsigned long timeout;
582 timeout = jiffies + msecs_to_jiffies(1000);
584 if (chip->polling_mode) {
585 spin_lock_irq(&chip->reg_lock);
586 azx_update_rirb(chip);
587 spin_unlock_irq(&chip->reg_lock);
589 if (!chip->rirb.cmds) {
591 return chip->rirb.res; /* the last value */
593 if (time_after(jiffies, timeout))
595 if (codec->bus->needs_damn_long_delay)
596 msleep(2); /* temporary workaround */
604 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
605 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
606 free_irq(chip->irq, chip);
608 pci_disable_msi(chip->pci);
610 if (azx_acquire_irq(chip, 1) < 0)
615 if (!chip->polling_mode) {
616 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
617 "switching to polling mode: last cmd=0x%08x\n",
619 chip->polling_mode = 1;
623 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
624 "switching to single_cmd mode: last cmd=0x%08x\n",
626 chip->rirb.rp = azx_readb(chip, RIRBWP);
628 /* switch to single_cmd mode */
629 chip->single_cmd = 1;
630 azx_free_cmd_io(chip);
635 * Use the single immediate command instead of CORB/RIRB for simplicity
637 * Note: according to Intel, this is not preferred use. The command was
638 * intended for the BIOS only, and may get confused with unsolicited
639 * responses. So, we shouldn't use it for normal operation from the
641 * I left the codes, however, for debugging/testing purposes.
645 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
647 struct azx *chip = codec->bus->private_data;
651 /* check ICB busy bit */
652 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
653 /* Clear IRV valid bit */
654 azx_writew(chip, IRS, azx_readw(chip, IRS) |
656 azx_writel(chip, IC, val);
657 azx_writew(chip, IRS, azx_readw(chip, IRS) |
663 if (printk_ratelimit())
664 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
665 azx_readw(chip, IRS), val);
669 /* receive a response */
670 static unsigned int azx_single_get_response(struct hda_codec *codec)
672 struct azx *chip = codec->bus->private_data;
676 /* check IRV busy bit */
677 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
678 return azx_readl(chip, IR);
681 if (printk_ratelimit())
682 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
683 azx_readw(chip, IRS));
684 return (unsigned int)-1;
688 * The below are the main callbacks from hda_codec.
690 * They are just the skeleton to call sub-callbacks according to the
691 * current setting of chip->single_cmd.
695 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
696 int direct, unsigned int verb,
699 struct azx *chip = codec->bus->private_data;
702 val = (u32)(codec->addr & 0x0f) << 28;
703 val |= (u32)direct << 27;
704 val |= (u32)nid << 20;
707 chip->last_cmd = val;
709 if (chip->single_cmd)
710 return azx_single_send_cmd(codec, val);
712 return azx_corb_send_cmd(codec, val);
716 static unsigned int azx_get_response(struct hda_codec *codec)
718 struct azx *chip = codec->bus->private_data;
719 if (chip->single_cmd)
720 return azx_single_get_response(codec);
722 return azx_rirb_get_response(codec);
725 #ifdef CONFIG_SND_HDA_POWER_SAVE
726 static void azx_power_notify(struct hda_codec *codec);
729 /* reset codec link */
730 static int azx_reset(struct azx *chip)
735 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
737 /* reset controller */
738 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
741 while (azx_readb(chip, GCTL) && --count)
744 /* delay for >= 100us for codec PLL to settle per spec
745 * Rev 0.9 section 5.5.1
749 /* Bring controller out of reset */
750 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
753 while (!azx_readb(chip, GCTL) && --count)
756 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
759 /* check to see if controller is ready */
760 if (!azx_readb(chip, GCTL)) {
761 snd_printd("azx_reset: controller not ready!\n");
765 /* Accept unsolicited responses */
766 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
769 if (!chip->codec_mask) {
770 chip->codec_mask = azx_readw(chip, STATESTS);
771 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
782 /* enable interrupts */
783 static void azx_int_enable(struct azx *chip)
785 /* enable controller CIE and GIE */
786 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
787 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
790 /* disable interrupts */
791 static void azx_int_disable(struct azx *chip)
795 /* disable interrupts in stream descriptor */
796 for (i = 0; i < chip->num_streams; i++) {
797 struct azx_dev *azx_dev = &chip->azx_dev[i];
798 azx_sd_writeb(azx_dev, SD_CTL,
799 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
802 /* disable SIE for all streams */
803 azx_writeb(chip, INTCTL, 0);
805 /* disable controller CIE and GIE */
806 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
807 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
810 /* clear interrupts */
811 static void azx_int_clear(struct azx *chip)
815 /* clear stream status */
816 for (i = 0; i < chip->num_streams; i++) {
817 struct azx_dev *azx_dev = &chip->azx_dev[i];
818 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
822 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
824 /* clear rirb status */
825 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
827 /* clear int status */
828 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
832 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
835 * Before stream start, initialize parameter
837 azx_dev->insufficient = 1;
840 azx_writeb(chip, INTCTL,
841 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
842 /* set DMA start and interrupt mask */
843 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
844 SD_CTL_DMA_START | SD_INT_MASK);
848 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
851 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
852 ~(SD_CTL_DMA_START | SD_INT_MASK));
853 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
855 azx_writeb(chip, INTCTL,
856 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
861 * reset and start the controller registers
863 static void azx_init_chip(struct azx *chip)
865 if (chip->initialized)
868 /* reset controller */
871 /* initialize interrupts */
873 azx_int_enable(chip);
875 /* initialize the codec command I/O */
876 if (!chip->single_cmd)
877 azx_init_cmd_io(chip);
879 /* program the position buffer */
880 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
881 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
883 chip->initialized = 1;
887 * initialize the PCI registers
889 /* update bits in a PCI register byte */
890 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
891 unsigned char mask, unsigned char val)
895 pci_read_config_byte(pci, reg, &data);
897 data |= (val & mask);
898 pci_write_config_byte(pci, reg, data);
901 static void azx_init_pci(struct azx *chip)
903 unsigned short snoop;
905 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
906 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
907 * Ensuring these bits are 0 clears playback static on some HD Audio
910 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
912 switch (chip->driver_type) {
914 /* For ATI SB450 azalia HD audio, we need to enable snoop */
915 update_pci_byte(chip->pci,
916 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
917 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
919 case AZX_DRIVER_NVIDIA:
920 /* For NVIDIA HDA, enable snoop */
921 update_pci_byte(chip->pci,
922 NVIDIA_HDA_TRANSREG_ADDR,
923 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
924 update_pci_byte(chip->pci,
925 NVIDIA_HDA_ISTRM_COH,
926 0x01, NVIDIA_HDA_ENABLE_COHBIT);
927 update_pci_byte(chip->pci,
928 NVIDIA_HDA_OSTRM_COH,
929 0x01, NVIDIA_HDA_ENABLE_COHBIT);
932 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
933 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
934 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
935 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
936 pci_read_config_word(chip->pci,
937 INTEL_SCH_HDA_DEVC, &snoop);
938 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
939 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
948 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
953 static irqreturn_t azx_interrupt(int irq, void *dev_id)
955 struct azx *chip = dev_id;
956 struct azx_dev *azx_dev;
960 spin_lock(&chip->reg_lock);
962 status = azx_readl(chip, INTSTS);
964 spin_unlock(&chip->reg_lock);
968 for (i = 0; i < chip->num_streams; i++) {
969 azx_dev = &chip->azx_dev[i];
970 if (status & azx_dev->sd_int_sta_mask) {
971 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
972 if (!azx_dev->substream || !azx_dev->running)
974 /* ignore the first dummy IRQ (due to pos_adj) */
975 if (azx_dev->irq_ignore) {
976 azx_dev->irq_ignore = 0;
979 /* check whether this IRQ is really acceptable */
980 if (azx_position_ok(chip, azx_dev)) {
981 azx_dev->irq_pending = 0;
982 spin_unlock(&chip->reg_lock);
983 snd_pcm_period_elapsed(azx_dev->substream);
984 spin_lock(&chip->reg_lock);
986 /* bogus IRQ, process it later */
987 azx_dev->irq_pending = 1;
988 schedule_work(&chip->irq_pending_work);
994 status = azx_readb(chip, RIRBSTS);
995 if (status & RIRB_INT_MASK) {
996 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
997 azx_update_rirb(chip);
998 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1002 /* clear state status int */
1003 if (azx_readb(chip, STATESTS) & 0x04)
1004 azx_writeb(chip, STATESTS, 0x04);
1006 spin_unlock(&chip->reg_lock);
1013 * set up a BDL entry
1015 static int setup_bdle(struct snd_pcm_substream *substream,
1016 struct azx_dev *azx_dev, u32 **bdlp,
1017 int ofs, int size, int with_ioc)
1025 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1028 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1029 /* program the address field of the BDL entry */
1030 bdl[0] = cpu_to_le32((u32)addr);
1031 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1032 /* program the size field of the BDL entry */
1033 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1034 bdl[2] = cpu_to_le32(chunk);
1035 /* program the IOC to enable interrupt
1036 * only when the whole fragment is processed
1039 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1049 * set up BDL entries
1051 static int azx_setup_periods(struct azx *chip,
1052 struct snd_pcm_substream *substream,
1053 struct azx_dev *azx_dev)
1056 int i, ofs, periods, period_bytes;
1059 /* reset BDL address */
1060 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1061 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1063 period_bytes = snd_pcm_lib_period_bytes(substream);
1064 azx_dev->period_bytes = period_bytes;
1065 periods = azx_dev->bufsize / period_bytes;
1067 /* program the initial BDL entries */
1068 bdl = (u32 *)azx_dev->bdl.area;
1071 azx_dev->irq_ignore = 0;
1072 pos_adj = bdl_pos_adj[chip->dev_index];
1074 struct snd_pcm_runtime *runtime = substream->runtime;
1075 int pos_align = pos_adj;
1076 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1078 pos_adj = pos_align;
1080 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1082 pos_adj = frames_to_bytes(runtime, pos_adj);
1083 if (pos_adj >= period_bytes) {
1084 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1085 bdl_pos_adj[chip->dev_index]);
1088 ofs = setup_bdle(substream, azx_dev,
1089 &bdl, ofs, pos_adj, 1);
1092 azx_dev->irq_ignore = 1;
1096 for (i = 0; i < periods; i++) {
1097 if (i == periods - 1 && pos_adj)
1098 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1099 period_bytes - pos_adj, 0);
1101 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1109 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1110 azx_dev->bufsize, period_bytes);
1112 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1113 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1118 * set up the SD for streaming
1120 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1125 /* make sure the run bit is zero for SD */
1126 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1129 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1130 SD_CTL_STREAM_RESET);
1133 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1136 val &= ~SD_CTL_STREAM_RESET;
1137 azx_sd_writeb(azx_dev, SD_CTL, val);
1141 /* waiting for hardware to report that the stream is out of reset */
1142 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1146 /* program the stream_tag */
1147 azx_sd_writel(azx_dev, SD_CTL,
1148 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1149 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1151 /* program the length of samples in cyclic buffer */
1152 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1154 /* program the stream format */
1155 /* this value needs to be the same as the one programmed */
1156 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1158 /* program the stream LVI (last valid index) of the BDL */
1159 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1161 /* program the BDL address */
1162 /* lower BDL address */
1163 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1164 /* upper BDL address */
1165 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1167 /* enable the position buffer */
1168 if (chip->position_fix == POS_FIX_POSBUF ||
1169 chip->position_fix == POS_FIX_AUTO ||
1170 chip->via_dmapos_patch) {
1171 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1172 azx_writel(chip, DPLBASE,
1173 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1176 /* set the interrupt enable bits in the descriptor control register */
1177 azx_sd_writel(azx_dev, SD_CTL,
1178 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1183 static int azx_attach_pcm_stream(struct hda_codec *codec, struct hda_pcm *cpcm);
1186 * Codec initialization
1189 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1190 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1191 [AZX_DRIVER_TERA] = 1,
1194 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1195 unsigned int codec_probe_mask)
1197 struct hda_bus_template bus_temp;
1201 memset(&bus_temp, 0, sizeof(bus_temp));
1202 bus_temp.private_data = chip;
1203 bus_temp.modelname = model;
1204 bus_temp.pci = chip->pci;
1205 bus_temp.ops.command = azx_send_cmd;
1206 bus_temp.ops.get_response = azx_get_response;
1207 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1208 #ifdef CONFIG_SND_HDA_POWER_SAVE
1209 bus_temp.ops.pm_notify = azx_power_notify;
1212 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1216 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1217 chip->bus->needs_damn_long_delay = 1;
1220 max_slots = azx_max_codecs[chip->driver_type];
1222 max_slots = AZX_MAX_CODECS;
1223 for (c = 0; c < max_slots; c++) {
1224 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1225 struct hda_codec *codec;
1226 err = snd_hda_codec_new(chip->bus, c, &codec);
1233 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1245 /* assign a stream for the PCM */
1246 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1249 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1250 dev = chip->playback_index_offset;
1251 nums = chip->playback_streams;
1253 dev = chip->capture_index_offset;
1254 nums = chip->capture_streams;
1256 for (i = 0; i < nums; i++, dev++)
1257 if (!chip->azx_dev[dev].opened) {
1258 chip->azx_dev[dev].opened = 1;
1259 return &chip->azx_dev[dev];
1264 /* release the assigned stream */
1265 static inline void azx_release_device(struct azx_dev *azx_dev)
1267 azx_dev->opened = 0;
1270 static struct snd_pcm_hardware azx_pcm_hw = {
1271 .info = (SNDRV_PCM_INFO_MMAP |
1272 SNDRV_PCM_INFO_INTERLEAVED |
1273 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1274 SNDRV_PCM_INFO_MMAP_VALID |
1275 /* No full-resume yet implemented */
1276 /* SNDRV_PCM_INFO_RESUME |*/
1277 SNDRV_PCM_INFO_PAUSE |
1278 SNDRV_PCM_INFO_SYNC_START),
1279 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1280 .rates = SNDRV_PCM_RATE_48000,
1285 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1286 .period_bytes_min = 128,
1287 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1289 .periods_max = AZX_MAX_FRAG,
1295 struct hda_codec *codec;
1296 struct hda_pcm_stream *hinfo[2];
1299 static int azx_pcm_open(struct snd_pcm_substream *substream)
1301 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1302 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1303 struct azx *chip = apcm->chip;
1304 struct azx_dev *azx_dev;
1305 struct snd_pcm_runtime *runtime = substream->runtime;
1306 unsigned long flags;
1309 mutex_lock(&chip->open_mutex);
1310 azx_dev = azx_assign_device(chip, substream->stream);
1311 if (azx_dev == NULL) {
1312 mutex_unlock(&chip->open_mutex);
1315 runtime->hw = azx_pcm_hw;
1316 runtime->hw.channels_min = hinfo->channels_min;
1317 runtime->hw.channels_max = hinfo->channels_max;
1318 runtime->hw.formats = hinfo->formats;
1319 runtime->hw.rates = hinfo->rates;
1320 snd_pcm_limit_hw_rates(runtime);
1321 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1322 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1324 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1326 snd_hda_power_up(apcm->codec);
1327 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1329 azx_release_device(azx_dev);
1330 snd_hda_power_down(apcm->codec);
1331 mutex_unlock(&chip->open_mutex);
1334 spin_lock_irqsave(&chip->reg_lock, flags);
1335 azx_dev->substream = substream;
1336 azx_dev->running = 0;
1337 spin_unlock_irqrestore(&chip->reg_lock, flags);
1339 runtime->private_data = azx_dev;
1340 snd_pcm_set_sync(substream);
1341 mutex_unlock(&chip->open_mutex);
1345 static int azx_pcm_close(struct snd_pcm_substream *substream)
1347 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1348 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1349 struct azx *chip = apcm->chip;
1350 struct azx_dev *azx_dev = get_azx_dev(substream);
1351 unsigned long flags;
1353 mutex_lock(&chip->open_mutex);
1354 spin_lock_irqsave(&chip->reg_lock, flags);
1355 azx_dev->substream = NULL;
1356 azx_dev->running = 0;
1357 spin_unlock_irqrestore(&chip->reg_lock, flags);
1358 azx_release_device(azx_dev);
1359 hinfo->ops.close(hinfo, apcm->codec, substream);
1360 snd_hda_power_down(apcm->codec);
1361 mutex_unlock(&chip->open_mutex);
1365 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1366 struct snd_pcm_hw_params *hw_params)
1368 return snd_pcm_lib_malloc_pages(substream,
1369 params_buffer_bytes(hw_params));
1372 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1374 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1375 struct azx_dev *azx_dev = get_azx_dev(substream);
1376 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1378 /* reset BDL address */
1379 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1380 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1381 azx_sd_writel(azx_dev, SD_CTL, 0);
1383 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1385 return snd_pcm_lib_free_pages(substream);
1388 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1390 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1391 struct azx *chip = apcm->chip;
1392 struct azx_dev *azx_dev = get_azx_dev(substream);
1393 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1394 struct snd_pcm_runtime *runtime = substream->runtime;
1396 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1397 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1401 if (!azx_dev->format_val) {
1402 snd_printk(KERN_ERR SFX
1403 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1404 runtime->rate, runtime->channels, runtime->format);
1408 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1409 azx_dev->bufsize, azx_dev->format_val);
1410 if (azx_setup_periods(chip, substream, azx_dev) < 0)
1412 azx_setup_controller(chip, azx_dev);
1413 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1414 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1416 azx_dev->fifo_size = 0;
1418 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1419 azx_dev->format_val, substream);
1422 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1424 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1425 struct azx *chip = apcm->chip;
1426 struct azx_dev *azx_dev;
1427 struct snd_pcm_substream *s;
1428 int start, nsync = 0, sbits = 0;
1432 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1433 case SNDRV_PCM_TRIGGER_RESUME:
1434 case SNDRV_PCM_TRIGGER_START:
1437 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1438 case SNDRV_PCM_TRIGGER_SUSPEND:
1439 case SNDRV_PCM_TRIGGER_STOP:
1446 snd_pcm_group_for_each_entry(s, substream) {
1447 if (s->pcm->card != substream->pcm->card)
1449 azx_dev = get_azx_dev(s);
1450 sbits |= 1 << azx_dev->index;
1452 snd_pcm_trigger_done(s, substream);
1455 spin_lock(&chip->reg_lock);
1457 /* first, set SYNC bits of corresponding streams */
1458 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1460 snd_pcm_group_for_each_entry(s, substream) {
1461 if (s->pcm->card != substream->pcm->card)
1463 azx_dev = get_azx_dev(s);
1465 azx_stream_start(chip, azx_dev);
1467 azx_stream_stop(chip, azx_dev);
1468 azx_dev->running = start;
1470 spin_unlock(&chip->reg_lock);
1474 /* wait until all FIFOs get ready */
1475 for (timeout = 5000; timeout; timeout--) {
1477 snd_pcm_group_for_each_entry(s, substream) {
1478 if (s->pcm->card != substream->pcm->card)
1480 azx_dev = get_azx_dev(s);
1481 if (!(azx_sd_readb(azx_dev, SD_STS) &
1490 /* wait until all RUN bits are cleared */
1491 for (timeout = 5000; timeout; timeout--) {
1493 snd_pcm_group_for_each_entry(s, substream) {
1494 if (s->pcm->card != substream->pcm->card)
1496 azx_dev = get_azx_dev(s);
1497 if (azx_sd_readb(azx_dev, SD_CTL) &
1507 spin_lock(&chip->reg_lock);
1508 /* reset SYNC bits */
1509 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1510 spin_unlock(&chip->reg_lock);
1515 /* get the current DMA position with correction on VIA chips */
1516 static unsigned int azx_via_get_position(struct azx *chip,
1517 struct azx_dev *azx_dev)
1519 unsigned int link_pos, mini_pos, bound_pos;
1520 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1521 unsigned int fifo_size;
1523 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1524 if (azx_dev->index >= 4) {
1525 /* Playback, no problem using link position */
1531 * use mod to get the DMA position just like old chipset
1533 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1534 mod_dma_pos %= azx_dev->period_bytes;
1536 /* azx_dev->fifo_size can't get FIFO size of in stream.
1537 * Get from base address + offset.
1539 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1541 if (azx_dev->insufficient) {
1542 /* Link position never gather than FIFO size */
1543 if (link_pos <= fifo_size)
1546 azx_dev->insufficient = 0;
1549 if (link_pos <= fifo_size)
1550 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1552 mini_pos = link_pos - fifo_size;
1554 /* Find nearest previous boudary */
1555 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1556 mod_link_pos = link_pos % azx_dev->period_bytes;
1557 if (mod_link_pos >= fifo_size)
1558 bound_pos = link_pos - mod_link_pos;
1559 else if (mod_dma_pos >= mod_mini_pos)
1560 bound_pos = mini_pos - mod_mini_pos;
1562 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1563 if (bound_pos >= azx_dev->bufsize)
1567 /* Calculate real DMA position we want */
1568 return bound_pos + mod_dma_pos;
1571 static unsigned int azx_get_position(struct azx *chip,
1572 struct azx_dev *azx_dev)
1576 if (chip->via_dmapos_patch)
1577 pos = azx_via_get_position(chip, azx_dev);
1578 else if (chip->position_fix == POS_FIX_POSBUF ||
1579 chip->position_fix == POS_FIX_AUTO) {
1580 /* use the position buffer */
1581 pos = le32_to_cpu(*azx_dev->posbuf);
1584 pos = azx_sd_readl(azx_dev, SD_LPIB);
1586 if (pos >= azx_dev->bufsize)
1591 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1593 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1594 struct azx *chip = apcm->chip;
1595 struct azx_dev *azx_dev = get_azx_dev(substream);
1596 return bytes_to_frames(substream->runtime,
1597 azx_get_position(chip, azx_dev));
1601 * Check whether the current DMA position is acceptable for updating
1602 * periods. Returns non-zero if it's OK.
1604 * Many HD-audio controllers appear pretty inaccurate about
1605 * the update-IRQ timing. The IRQ is issued before actually the
1606 * data is processed. So, we need to process it afterwords in a
1609 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1613 pos = azx_get_position(chip, azx_dev);
1614 if (chip->position_fix == POS_FIX_AUTO) {
1617 "hda-intel: Invalid position buffer, "
1618 "using LPIB read method instead.\n");
1619 chip->position_fix = POS_FIX_LPIB;
1620 pos = azx_get_position(chip, azx_dev);
1622 chip->position_fix = POS_FIX_POSBUF;
1625 if (!bdl_pos_adj[chip->dev_index])
1626 return 1; /* no delayed ack */
1627 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1628 return 0; /* NG - it's below the period boundary */
1629 return 1; /* OK, it's fine */
1633 * The work for pending PCM period updates.
1635 static void azx_irq_pending_work(struct work_struct *work)
1637 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1640 if (!chip->irq_pending_warned) {
1642 "hda-intel: IRQ timing workaround is activated "
1643 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1644 chip->card->number);
1645 chip->irq_pending_warned = 1;
1650 spin_lock_irq(&chip->reg_lock);
1651 for (i = 0; i < chip->num_streams; i++) {
1652 struct azx_dev *azx_dev = &chip->azx_dev[i];
1653 if (!azx_dev->irq_pending ||
1654 !azx_dev->substream ||
1657 if (azx_position_ok(chip, azx_dev)) {
1658 azx_dev->irq_pending = 0;
1659 spin_unlock(&chip->reg_lock);
1660 snd_pcm_period_elapsed(azx_dev->substream);
1661 spin_lock(&chip->reg_lock);
1665 spin_unlock_irq(&chip->reg_lock);
1672 /* clear irq_pending flags and assure no on-going workq */
1673 static void azx_clear_irq_pending(struct azx *chip)
1677 spin_lock_irq(&chip->reg_lock);
1678 for (i = 0; i < chip->num_streams; i++)
1679 chip->azx_dev[i].irq_pending = 0;
1680 spin_unlock_irq(&chip->reg_lock);
1681 flush_scheduled_work();
1684 static struct snd_pcm_ops azx_pcm_ops = {
1685 .open = azx_pcm_open,
1686 .close = azx_pcm_close,
1687 .ioctl = snd_pcm_lib_ioctl,
1688 .hw_params = azx_pcm_hw_params,
1689 .hw_free = azx_pcm_hw_free,
1690 .prepare = azx_pcm_prepare,
1691 .trigger = azx_pcm_trigger,
1692 .pointer = azx_pcm_pointer,
1693 .page = snd_pcm_sgbuf_ops_page,
1696 static void azx_pcm_free(struct snd_pcm *pcm)
1698 struct azx_pcm *apcm = pcm->private_data;
1700 apcm->chip->pcm[pcm->device] = NULL;
1706 azx_attach_pcm_stream(struct hda_codec *codec, struct hda_pcm *cpcm)
1708 struct azx *chip = codec->bus->private_data;
1709 struct snd_pcm *pcm;
1710 struct azx_pcm *apcm;
1711 int pcm_dev = cpcm->device;
1714 if (pcm_dev >= AZX_MAX_PCMS) {
1715 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1719 if (chip->pcm[pcm_dev]) {
1720 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1723 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1724 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1725 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1729 strcpy(pcm->name, cpcm->name);
1730 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1734 apcm->codec = codec;
1735 pcm->private_data = apcm;
1736 pcm->private_free = azx_pcm_free;
1737 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1738 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1739 chip->pcm[pcm_dev] = pcm;
1741 for (s = 0; s < 2; s++) {
1742 apcm->hinfo[s] = &cpcm->stream[s];
1743 if (cpcm->stream[s].substreams)
1744 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1746 /* buffer pre-allocation */
1747 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1748 snd_dma_pci_data(chip->pci),
1749 1024 * 64, 32 * 1024 * 1024);
1754 * mixer creation - all stuff is implemented in hda module
1756 static int __devinit azx_mixer_create(struct azx *chip)
1758 return snd_hda_build_controls(chip->bus);
1763 * initialize SD streams
1765 static int __devinit azx_init_stream(struct azx *chip)
1769 /* initialize each stream (aka device)
1770 * assign the starting bdl address to each stream (device)
1773 for (i = 0; i < chip->num_streams; i++) {
1774 struct azx_dev *azx_dev = &chip->azx_dev[i];
1775 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1776 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1777 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1778 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1779 azx_dev->sd_int_sta_mask = 1 << i;
1780 /* stream tag: must be non-zero and unique */
1782 azx_dev->stream_tag = i + 1;
1788 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1790 if (request_irq(chip->pci->irq, azx_interrupt,
1791 chip->msi ? 0 : IRQF_SHARED,
1792 "HDA Intel", chip)) {
1793 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1794 "disabling device\n", chip->pci->irq);
1796 snd_card_disconnect(chip->card);
1799 chip->irq = chip->pci->irq;
1800 pci_intx(chip->pci, !chip->msi);
1805 static void azx_stop_chip(struct azx *chip)
1807 if (!chip->initialized)
1810 /* disable interrupts */
1811 azx_int_disable(chip);
1812 azx_int_clear(chip);
1814 /* disable CORB/RIRB */
1815 azx_free_cmd_io(chip);
1817 /* disable position buffer */
1818 azx_writel(chip, DPLBASE, 0);
1819 azx_writel(chip, DPUBASE, 0);
1821 chip->initialized = 0;
1824 #ifdef CONFIG_SND_HDA_POWER_SAVE
1825 /* power-up/down the controller */
1826 static void azx_power_notify(struct hda_codec *codec)
1828 struct azx *chip = codec->bus->private_data;
1829 struct hda_codec *c;
1832 list_for_each_entry(c, &codec->bus->codec_list, list) {
1839 azx_init_chip(chip);
1840 else if (chip->running && power_save_controller)
1841 azx_stop_chip(chip);
1843 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1849 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1851 struct snd_card *card = pci_get_drvdata(pci);
1852 struct azx *chip = card->private_data;
1855 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1856 azx_clear_irq_pending(chip);
1857 for (i = 0; i < AZX_MAX_PCMS; i++)
1858 snd_pcm_suspend_all(chip->pcm[i]);
1859 if (chip->initialized)
1860 snd_hda_suspend(chip->bus, state);
1861 azx_stop_chip(chip);
1862 if (chip->irq >= 0) {
1863 free_irq(chip->irq, chip);
1867 pci_disable_msi(chip->pci);
1868 pci_disable_device(pci);
1869 pci_save_state(pci);
1870 pci_set_power_state(pci, pci_choose_state(pci, state));
1874 static int azx_resume(struct pci_dev *pci)
1876 struct snd_card *card = pci_get_drvdata(pci);
1877 struct azx *chip = card->private_data;
1879 pci_set_power_state(pci, PCI_D0);
1880 pci_restore_state(pci);
1881 if (pci_enable_device(pci) < 0) {
1882 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1883 "disabling device\n");
1884 snd_card_disconnect(card);
1887 pci_set_master(pci);
1889 if (pci_enable_msi(pci) < 0)
1891 if (azx_acquire_irq(chip, 1) < 0)
1895 if (snd_hda_codecs_inuse(chip->bus))
1896 azx_init_chip(chip);
1898 snd_hda_resume(chip->bus);
1899 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1902 #endif /* CONFIG_PM */
1908 static int azx_free(struct azx *chip)
1912 if (chip->initialized) {
1913 azx_clear_irq_pending(chip);
1914 for (i = 0; i < chip->num_streams; i++)
1915 azx_stream_stop(chip, &chip->azx_dev[i]);
1916 azx_stop_chip(chip);
1920 free_irq(chip->irq, (void*)chip);
1922 pci_disable_msi(chip->pci);
1923 if (chip->remap_addr)
1924 iounmap(chip->remap_addr);
1926 if (chip->azx_dev) {
1927 for (i = 0; i < chip->num_streams; i++)
1928 if (chip->azx_dev[i].bdl.area)
1929 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1932 snd_dma_free_pages(&chip->rb);
1933 if (chip->posbuf.area)
1934 snd_dma_free_pages(&chip->posbuf);
1935 pci_release_regions(chip->pci);
1936 pci_disable_device(chip->pci);
1937 kfree(chip->azx_dev);
1943 static int azx_dev_free(struct snd_device *device)
1945 return azx_free(device->device_data);
1949 * white/black-listing for position_fix
1951 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1952 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1953 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1954 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1958 static int __devinit check_position_fix(struct azx *chip, int fix)
1960 const struct snd_pci_quirk *q;
1962 /* Check VIA HD Audio Controller exist */
1963 if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
1964 chip->pci->device == VIA_HDAC_DEVICE_ID) {
1965 chip->via_dmapos_patch = 1;
1966 /* Use link position directly, avoid any transfer problem. */
1967 return POS_FIX_LPIB;
1969 chip->via_dmapos_patch = 0;
1971 if (fix == POS_FIX_AUTO) {
1972 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1975 "hda_intel: position_fix set to %d "
1976 "for device %04x:%04x\n",
1977 q->value, q->subvendor, q->subdevice);
1985 * black-lists for probe_mask
1987 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1988 /* Thinkpad often breaks the controller communication when accessing
1989 * to the non-working (or non-existing) modem codec slot.
1991 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1992 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1993 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1997 static void __devinit check_probe_mask(struct azx *chip, int dev)
1999 const struct snd_pci_quirk *q;
2001 if (probe_mask[dev] == -1) {
2002 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2005 "hda_intel: probe_mask set to 0x%x "
2006 "for device %04x:%04x\n",
2007 q->value, q->subvendor, q->subdevice);
2008 probe_mask[dev] = q->value;
2017 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2018 int dev, int driver_type,
2023 unsigned short gcap;
2024 static struct snd_device_ops ops = {
2025 .dev_free = azx_dev_free,
2030 err = pci_enable_device(pci);
2034 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2036 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2037 pci_disable_device(pci);
2041 spin_lock_init(&chip->reg_lock);
2042 mutex_init(&chip->open_mutex);
2046 chip->driver_type = driver_type;
2047 chip->msi = enable_msi;
2048 chip->dev_index = dev;
2049 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2051 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2052 check_probe_mask(chip, dev);
2054 chip->single_cmd = single_cmd;
2056 if (bdl_pos_adj[dev] < 0) {
2057 switch (chip->driver_type) {
2058 case AZX_DRIVER_ICH:
2059 bdl_pos_adj[dev] = 1;
2062 bdl_pos_adj[dev] = 32;
2067 #if BITS_PER_LONG != 64
2068 /* Fix up base address on ULI M5461 */
2069 if (chip->driver_type == AZX_DRIVER_ULI) {
2071 pci_read_config_word(pci, 0x40, &tmp3);
2072 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2073 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2077 err = pci_request_regions(pci, "ICH HD audio");
2080 pci_disable_device(pci);
2084 chip->addr = pci_resource_start(pci, 0);
2085 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2086 if (chip->remap_addr == NULL) {
2087 snd_printk(KERN_ERR SFX "ioremap error\n");
2093 if (pci_enable_msi(pci) < 0)
2096 if (azx_acquire_irq(chip, 0) < 0) {
2101 pci_set_master(pci);
2102 synchronize_irq(chip->irq);
2104 gcap = azx_readw(chip, GCAP);
2105 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2107 /* allow 64bit DMA address if supported by H/W */
2108 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2109 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2111 /* read number of streams from GCAP register instead of using
2114 chip->capture_streams = (gcap >> 8) & 0x0f;
2115 chip->playback_streams = (gcap >> 12) & 0x0f;
2116 if (!chip->playback_streams && !chip->capture_streams) {
2117 /* gcap didn't give any info, switching to old method */
2119 switch (chip->driver_type) {
2120 case AZX_DRIVER_ULI:
2121 chip->playback_streams = ULI_NUM_PLAYBACK;
2122 chip->capture_streams = ULI_NUM_CAPTURE;
2124 case AZX_DRIVER_ATIHDMI:
2125 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2126 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2129 chip->playback_streams = ICH6_NUM_PLAYBACK;
2130 chip->capture_streams = ICH6_NUM_CAPTURE;
2134 chip->capture_index_offset = 0;
2135 chip->playback_index_offset = chip->capture_streams;
2136 chip->num_streams = chip->playback_streams + chip->capture_streams;
2137 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2139 if (!chip->azx_dev) {
2140 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2144 for (i = 0; i < chip->num_streams; i++) {
2145 /* allocate memory for the BDL for each stream */
2146 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2147 snd_dma_pci_data(chip->pci),
2148 BDL_SIZE, &chip->azx_dev[i].bdl);
2150 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2154 /* allocate memory for the position buffer */
2155 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2156 snd_dma_pci_data(chip->pci),
2157 chip->num_streams * 8, &chip->posbuf);
2159 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2162 /* allocate CORB/RIRB */
2163 if (!chip->single_cmd) {
2164 err = azx_alloc_cmd_io(chip);
2169 /* initialize streams */
2170 azx_init_stream(chip);
2172 /* initialize chip */
2174 azx_init_chip(chip);
2176 /* codec detection */
2177 if (!chip->codec_mask) {
2178 snd_printk(KERN_ERR SFX "no codecs found!\n");
2183 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2185 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2189 strcpy(card->driver, "HDA-Intel");
2190 strcpy(card->shortname, driver_short_names[chip->driver_type]);
2191 sprintf(card->longname, "%s at 0x%lx irq %i",
2192 card->shortname, chip->addr, chip->irq);
2202 static void power_down_all_codecs(struct azx *chip)
2204 #ifdef CONFIG_SND_HDA_POWER_SAVE
2205 /* The codecs were powered up in snd_hda_codec_new().
2206 * Now all initialization done, so turn them down if possible
2208 struct hda_codec *codec;
2209 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2210 snd_hda_power_down(codec);
2215 static int __devinit azx_probe(struct pci_dev *pci,
2216 const struct pci_device_id *pci_id)
2219 struct snd_card *card;
2223 if (dev >= SNDRV_CARDS)
2230 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2232 snd_printk(KERN_ERR SFX "Error creating card!\n");
2236 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2238 snd_card_free(card);
2241 card->private_data = chip;
2243 /* create codec instances */
2244 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2246 snd_card_free(card);
2250 /* create PCM streams */
2251 err = snd_hda_build_pcms(chip->bus);
2253 snd_card_free(card);
2257 /* create mixer controls */
2258 err = azx_mixer_create(chip);
2260 snd_card_free(card);
2264 snd_card_set_dev(card, &pci->dev);
2266 err = snd_card_register(card);
2268 snd_card_free(card);
2272 pci_set_drvdata(pci, card);
2274 power_down_all_codecs(chip);
2280 static void __devexit azx_remove(struct pci_dev *pci)
2282 snd_card_free(pci_get_drvdata(pci));
2283 pci_set_drvdata(pci, NULL);
2287 static struct pci_device_id azx_ids[] = {
2289 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2290 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2291 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2292 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2293 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2294 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2295 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2296 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2297 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2299 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2301 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2302 /* ATI SB 450/600 */
2303 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2304 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2306 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2307 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2308 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2309 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2310 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2311 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2312 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2313 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2314 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2315 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2316 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2317 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2318 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2319 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2320 /* VIA VT8251/VT8237A */
2321 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2323 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2325 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2327 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2328 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2329 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2330 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2331 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2332 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2333 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2334 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2335 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2336 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2337 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2338 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2339 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2340 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2341 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2342 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2343 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2344 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2345 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2346 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2347 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2348 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2350 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2353 MODULE_DEVICE_TABLE(pci, azx_ids);
2355 /* pci_driver definition */
2356 static struct pci_driver driver = {
2357 .name = "HDA Intel",
2358 .id_table = azx_ids,
2360 .remove = __devexit_p(azx_remove),
2362 .suspend = azx_suspend,
2363 .resume = azx_resume,
2367 static int __init alsa_card_azx_init(void)
2369 return pci_register_driver(&driver);
2372 static void __exit alsa_card_azx_exit(void)
2374 pci_unregister_driver(&driver);
2377 module_init(alsa_card_azx_init)
2378 module_exit(alsa_card_azx_exit)