sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int single_cmd;
  62 static int enable_msi;
  63
  64 module_param_array(index, int, NULL, 0444);
  65 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  66 module_param_array(id, charp, NULL, 0444);
  67 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  68 module_param_array(enable, bool, NULL, 0444);
  69 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  70 module_param_array(model, charp, NULL, 0444);
  71 MODULE_PARM_DESC(model, "Use the given board model.");
  72 module_param_array(position_fix, int, NULL, 0444);
  73 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  74                  "(0 = auto, 1 = none, 2 = POSBUF).");
  75 module_param_array(bdl_pos_adj, int, NULL, 0644);
  76 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  77 module_param_array(probe_mask, int, NULL, 0444);
  78 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  79 module_param(single_cmd, bool, 0444);
  80 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  81                  "(for debugging only).");
  82 module_param(enable_msi, int, 0444);
  83 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  84
  85 #ifdef CONFIG_SND_HDA_POWER_SAVE
  86 /* power_save option is defined in hda_codec.c */
  87
  88 /* reset the HD-audio controller in power save mode.
  89  * this may give more power-saving, but will take longer time to
  90  * wake up.
  91  */
  92 static int power_save_controller = 1;
  93 module_param(power_save_controller, bool, 0644);
  94 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  95 #endif
  96
  97 MODULE_LICENSE("GPL");
  98 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  99                          "{Intel, ICH6M},"
 100                          "{Intel, ICH7},"
 101                          "{Intel, ESB2},"
 102                          "{Intel, ICH8},"
 103                          "{Intel, ICH9},"
 104                          "{Intel, ICH10},"
 105                          "{Intel, PCH},"
 106                          "{Intel, SCH},"
 107                          "{ATI, SB450},"
 108                          "{ATI, SB600},"
 109                          "{ATI, RS600},"
 110                          "{ATI, RS690},"
 111                          "{ATI, RS780},"
 112                          "{ATI, R600},"
 113                          "{ATI, RV630},"
 114                          "{ATI, RV610},"
 115                          "{ATI, RV670},"
 116                          "{ATI, RV635},"
 117                          "{ATI, RV620},"
 118                          "{ATI, RV770},"
 119                          "{VIA, VT8251},"
 120                          "{VIA, VT8237A},"
 121                          "{SiS, SIS966},"
 122                          "{ULI, M5461}}");
 123 MODULE_DESCRIPTION("Intel HDA driver");
 124
 125 #define SFX     "hda-intel: "
 126
 127
 128 /*
 129  * registers
 130  */
 131 #define ICH6_REG_GCAP                   0x00
 132 #define ICH6_REG_VMIN                   0x02
 133 #define ICH6_REG_VMAJ                   0x03
 134 #define ICH6_REG_OUTPAY                 0x04
 135 #define ICH6_REG_INPAY                  0x06
 136 #define ICH6_REG_GCTL                   0x08
 137 #define ICH6_REG_WAKEEN                 0x0c
 138 #define ICH6_REG_STATESTS               0x0e
 139 #define ICH6_REG_GSTS                   0x10
 140 #define ICH6_REG_INTCTL                 0x20
 141 #define ICH6_REG_INTSTS                 0x24
 142 #define ICH6_REG_WALCLK                 0x30
 143 #define ICH6_REG_SYNC                   0x34
 144 #define ICH6_REG_CORBLBASE              0x40
 145 #define ICH6_REG_CORBUBASE              0x44
 146 #define ICH6_REG_CORBWP                 0x48
 147 #define ICH6_REG_CORBRP                 0x4A
 148 #define ICH6_REG_CORBCTL                0x4c
 149 #define ICH6_REG_CORBSTS                0x4d
 150 #define ICH6_REG_CORBSIZE               0x4e
 151
 152 #define ICH6_REG_RIRBLBASE              0x50
 153 #define ICH6_REG_RIRBUBASE              0x54
 154 #define ICH6_REG_RIRBWP                 0x58
 155 #define ICH6_REG_RINTCNT                0x5a
 156 #define ICH6_REG_RIRBCTL                0x5c
 157 #define ICH6_REG_RIRBSTS                0x5d
 158 #define ICH6_REG_RIRBSIZE               0x5e
 159
 160 #define ICH6_REG_IC                     0x60
 161 #define ICH6_REG_IR                     0x64
 162 #define ICH6_REG_IRS                    0x68
 163 #define   ICH6_IRS_VALID        (1<<1)
 164 #define   ICH6_IRS_BUSY         (1<<0)
 165
 166 #define ICH6_REG_DPLBASE                0x70
 167 #define ICH6_REG_DPUBASE                0x74
 168 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 169
 170 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 171 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 172
 173 /* stream register offsets from stream base */
 174 #define ICH6_REG_SD_CTL                 0x00
 175 #define ICH6_REG_SD_STS                 0x03
 176 #define ICH6_REG_SD_LPIB                0x04
 177 #define ICH6_REG_SD_CBL                 0x08
 178 #define ICH6_REG_SD_LVI                 0x0c
 179 #define ICH6_REG_SD_FIFOW               0x0e
 180 #define ICH6_REG_SD_FIFOSIZE            0x10
 181 #define ICH6_REG_SD_FORMAT              0x12
 182 #define ICH6_REG_SD_BDLPL               0x18
 183 #define ICH6_REG_SD_BDLPU               0x1c
 184
 185 /* PCI space */
 186 #define ICH6_PCIREG_TCSEL       0x44
 187
 188 /*
 189  * other constants
 190  */
 191
 192 /* max number of SDs */
 193 /* ICH, ATI and VIA have 4 playback and 4 capture */
 194 #define ICH6_NUM_CAPTURE        4
 195 #define ICH6_NUM_PLAYBACK       4
 196
 197 /* ULI has 6 playback and 5 capture */
 198 #define ULI_NUM_CAPTURE         5
 199 #define ULI_NUM_PLAYBACK        6
 200
 201 /* ATI HDMI has 1 playback and 0 capture */
 202 #define ATIHDMI_NUM_CAPTURE     0
 203 #define ATIHDMI_NUM_PLAYBACK    1
 204
 205 /* TERA has 4 playback and 3 capture */
 206 #define TERA_NUM_CAPTURE        3
 207 #define TERA_NUM_PLAYBACK       4
 208
 209 /* this number is statically defined for simplicity */
 210 #define MAX_AZX_DEV             16
 211
 212 /* max number of fragments - we may use more if allocating more pages for BDL */
 213 #define BDL_SIZE                4096
 214 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 215 #define AZX_MAX_FRAG            32
 216 /* max buffer size - no h/w limit, you can increase as you like */
 217 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 218 /* max number of PCM devics per card */
 219 #define AZX_MAX_PCMS            8
 220
 221 /* RIRB int mask: overrun[2], response[0] */
 222 #define RIRB_INT_RESPONSE       0x01
 223 #define RIRB_INT_OVERRUN        0x04
 224 #define RIRB_INT_MASK           0x05
 225
 226 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 227 #define AZX_MAX_CODECS          4
 228 #define STATESTS_INT_MASK       0x0f
 229
 230 /* SD_CTL bits */
 231 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 232 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 233 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 234 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 235 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 236 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 237 #define SD_CTL_STREAM_TAG_SHIFT 20
 238
 239 /* SD_CTL and SD_STS */
 240 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 241 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 242 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 243 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 244                                  SD_INT_COMPLETE)
 245
 246 /* SD_STS */
 247 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 248
 249 /* INTCTL and INTSTS */
 250 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 251 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 252 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 253
 254 /* GCTL unsolicited response enable bit */
 255 #define ICH6_GCTL_UREN          (1<<8)
 256
 257 /* GCTL reset bit */
 258 #define ICH6_GCTL_RESET         (1<<0)
 259
 260 /* CORB/RIRB control, read/write pointer */
 261 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 262 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 263 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 264 /* below are so far hardcoded - should read registers in future */
 265 #define ICH6_MAX_CORB_ENTRIES   256
 266 #define ICH6_MAX_RIRB_ENTRIES   256
 267
 268 /* position fix mode */
 269 enum {
 270         POS_FIX_AUTO,
 271         POS_FIX_LPIB,
 272         POS_FIX_POSBUF,
 273 };
 274
 275 /* Defines for ATI HD Audio support in SB450 south bridge */
 276 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 277 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 278
 279 /* Defines for Nvidia HDA support */
 280 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 281 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 282 #define NVIDIA_HDA_ISTRM_COH          0x4d
 283 #define NVIDIA_HDA_OSTRM_COH          0x4c
 284 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 285
 286 /* Defines for Intel SCH HDA snoop control */
 287 #define INTEL_SCH_HDA_DEVC      0x78
 288 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 289
 290 /* Define IN stream 0 FIFO size offset in VIA controller */
 291 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 292 /* Define VIA HD Audio Device ID*/
 293 #define VIA_HDAC_DEVICE_ID              0x3288
 294
 295
 296 /*
 297  */
 298
 299 struct azx_dev {
 300         struct snd_dma_buffer bdl; /* BDL buffer */
 301         u32 *posbuf;            /* position buffer pointer */
 302
 303         unsigned int bufsize;   /* size of the play buffer in bytes */
 304         unsigned int period_bytes; /* size of the period in bytes */
 305         unsigned int frags;     /* number for period in the play buffer */
 306         unsigned int fifo_size; /* FIFO size */
 307
 308         void __iomem *sd_addr;  /* stream descriptor pointer */
 309
 310         u32 sd_int_sta_mask;    /* stream int status mask */
 311
 312         /* pcm support */
 313         struct snd_pcm_substream *substream;    /* assigned substream,
 314                                                  * set in PCM open
 315                                                  */
 316         unsigned int format_val;        /* format value to be set in the
 317                                          * controller and the codec
 318                                          */
 319         unsigned char stream_tag;       /* assigned stream */
 320         unsigned char index;            /* stream index */
 321
 322         unsigned int opened :1;
 323         unsigned int running :1;
 324         unsigned int irq_pending :1;
 325         unsigned int irq_ignore :1;
 326         /*
 327          * For VIA:
 328          *  A flag to ensure DMA position is 0
 329          *  when link position is not greater than FIFO size
 330          */
 331         unsigned int insufficient :1;
 332 };
 333
 334 /* CORB/RIRB */
 335 struct azx_rb {
 336         u32 *buf;               /* CORB/RIRB buffer
 337                                  * Each CORB entry is 4byte, RIRB is 8byte
 338                                  */
 339         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 340         /* for RIRB */
 341         unsigned short rp, wp;  /* read/write pointers */
 342         int cmds;               /* number of pending requests */
 343         u32 res;                /* last read value */
 344 };
 345
 346 struct azx {
 347         struct snd_card *card;
 348         struct pci_dev *pci;
 349         int dev_index;
 350
 351         /* chip type specific */
 352         int driver_type;
 353         int playback_streams;
 354         int playback_index_offset;
 355         int capture_streams;
 356         int capture_index_offset;
 357         int num_streams;
 358
 359         /* pci resources */
 360         unsigned long addr;
 361         void __iomem *remap_addr;
 362         int irq;
 363
 364         /* locks */
 365         spinlock_t reg_lock;
 366         struct mutex open_mutex;
 367
 368         /* streams (x num_streams) */
 369         struct azx_dev *azx_dev;
 370
 371         /* PCM */
 372         struct snd_pcm *pcm[AZX_MAX_PCMS];
 373
 374         /* HD codec */
 375         unsigned short codec_mask;
 376         struct hda_bus *bus;
 377
 378         /* CORB/RIRB */
 379         struct azx_rb corb;
 380         struct azx_rb rirb;
 381
 382         /* CORB/RIRB and position buffers */
 383         struct snd_dma_buffer rb;
 384         struct snd_dma_buffer posbuf;
 385
 386         /* flags */
 387         int position_fix;
 388         unsigned int running :1;
 389         unsigned int initialized :1;
 390         unsigned int single_cmd :1;
 391         unsigned int polling_mode :1;
 392         unsigned int msi :1;
 393         unsigned int irq_pending_warned :1;
 394         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 395         unsigned int probing :1; /* codec probing phase */
 396
 397         /* for debugging */
 398         unsigned int last_cmd;  /* last issued command (to sync) */
 399
 400         /* for pending irqs */
 401         struct work_struct irq_pending_work;
 402
 403         /* reboot notifier (for mysterious hangup problem at power-down) */
 404         struct notifier_block reboot_notifier;
 405 };
 406
 407 /* driver types */
 408 enum {
 409         AZX_DRIVER_ICH,
 410         AZX_DRIVER_SCH,
 411         AZX_DRIVER_ATI,
 412         AZX_DRIVER_ATIHDMI,
 413         AZX_DRIVER_VIA,
 414         AZX_DRIVER_SIS,
 415         AZX_DRIVER_ULI,
 416         AZX_DRIVER_NVIDIA,
 417         AZX_DRIVER_TERA,
 418         AZX_NUM_DRIVERS, /* keep this as last entry */
 419 };
 420
 421 static char *driver_short_names[] __devinitdata = {
 422         [AZX_DRIVER_ICH] = "HDA Intel",
 423         [AZX_DRIVER_SCH] = "HDA Intel MID",
 424         [AZX_DRIVER_ATI] = "HDA ATI SB",
 425         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 426         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 427         [AZX_DRIVER_SIS] = "HDA SIS966",
 428         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 429         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 430         [AZX_DRIVER_TERA] = "HDA Teradici",
 431 };
 432
 433 /*
 434  * macros for easy use
 435  */
 436 #define azx_writel(chip,reg,value) \
 437         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 438 #define azx_readl(chip,reg) \
 439         readl((chip)->remap_addr + ICH6_REG_##reg)
 440 #define azx_writew(chip,reg,value) \
 441         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 442 #define azx_readw(chip,reg) \
 443         readw((chip)->remap_addr + ICH6_REG_##reg)
 444 #define azx_writeb(chip,reg,value) \
 445         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 446 #define azx_readb(chip,reg) \
 447         readb((chip)->remap_addr + ICH6_REG_##reg)
 448
 449 #define azx_sd_writel(dev,reg,value) \
 450         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 451 #define azx_sd_readl(dev,reg) \
 452         readl((dev)->sd_addr + ICH6_REG_##reg)
 453 #define azx_sd_writew(dev,reg,value) \
 454         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 455 #define azx_sd_readw(dev,reg) \
 456         readw((dev)->sd_addr + ICH6_REG_##reg)
 457 #define azx_sd_writeb(dev,reg,value) \
 458         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 459 #define azx_sd_readb(dev,reg) \
 460         readb((dev)->sd_addr + ICH6_REG_##reg)
 461
 462 /* for pcm support */
 463 #define get_azx_dev(substream) (substream->runtime->private_data)
 464
 465 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 466
 467 /*
 468  * Interface for HD codec
 469  */
 470
 471 /*
 472  * CORB / RIRB interface
 473  */
 474 static int azx_alloc_cmd_io(struct azx *chip)
 475 {
 476         int err;
 477
 478         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 479         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 480                                   snd_dma_pci_data(chip->pci),
 481                                   PAGE_SIZE, &chip->rb);
 482         if (err < 0) {
 483                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 484                 return err;
 485         }
 486         return 0;
 487 }
 488
 489 static void azx_init_cmd_io(struct azx *chip)
 490 {
 491         /* CORB set up */
 492         chip->corb.addr = chip->rb.addr;
 493         chip->corb.buf = (u32 *)chip->rb.area;
 494         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 495         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 496
 497         /* set the corb size to 256 entries (ULI requires explicitly) */
 498         azx_writeb(chip, CORBSIZE, 0x02);
 499         /* set the corb write pointer to 0 */
 500         azx_writew(chip, CORBWP, 0);
 501         /* reset the corb hw read pointer */
 502         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 503         /* enable corb dma */
 504         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 505
 506         /* RIRB set up */
 507         chip->rirb.addr = chip->rb.addr + 2048;
 508         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 509         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 510         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 511
 512         /* set the rirb size to 256 entries (ULI requires explicitly) */
 513         azx_writeb(chip, RIRBSIZE, 0x02);
 514         /* reset the rirb hw write pointer */
 515         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 516         /* set N=1, get RIRB response interrupt for new entry */
 517         azx_writew(chip, RINTCNT, 1);
 518         /* enable rirb dma and response irq */
 519         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 520         chip->rirb.rp = chip->rirb.cmds = 0;
 521 }
 522
 523 static void azx_free_cmd_io(struct azx *chip)
 524 {
 525         /* disable ringbuffer DMAs */
 526         azx_writeb(chip, RIRBCTL, 0);
 527         azx_writeb(chip, CORBCTL, 0);
 528 }
 529
 530 /* send a command */
 531 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 532 {
 533         struct azx *chip = bus->private_data;
 534         unsigned int wp;
 535
 536         /* add command to corb */
 537         wp = azx_readb(chip, CORBWP);
 538         wp++;
 539         wp %= ICH6_MAX_CORB_ENTRIES;
 540
 541         spin_lock_irq(&chip->reg_lock);
 542         chip->rirb.cmds++;
 543         chip->corb.buf[wp] = cpu_to_le32(val);
 544         azx_writel(chip, CORBWP, wp);
 545         spin_unlock_irq(&chip->reg_lock);
 546
 547         return 0;
 548 }
 549
 550 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 551
 552 /* retrieve RIRB entry - called from interrupt handler */
 553 static void azx_update_rirb(struct azx *chip)
 554 {
 555         unsigned int rp, wp;
 556         u32 res, res_ex;
 557
 558         wp = azx_readb(chip, RIRBWP);
 559         if (wp == chip->rirb.wp)
 560                 return;
 561         chip->rirb.wp = wp;
 562
 563         while (chip->rirb.rp != wp) {
 564                 chip->rirb.rp++;
 565                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 566
 567                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 568                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 569                 res = le32_to_cpu(chip->rirb.buf[rp]);
 570                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 571                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 572                 else if (chip->rirb.cmds) {
 573                         chip->rirb.res = res;
 574                         smp_wmb();
 575                         chip->rirb.cmds--;
 576                 }
 577         }
 578 }
 579
 580 /* receive a response */
 581 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
 582 {
 583         struct azx *chip = bus->private_data;
 584         unsigned long timeout;
 585
 586  again:
 587         timeout = jiffies + msecs_to_jiffies(1000);
 588         for (;;) {
 589                 if (chip->polling_mode) {
 590                         spin_lock_irq(&chip->reg_lock);
 591                         azx_update_rirb(chip);
 592                         spin_unlock_irq(&chip->reg_lock);
 593                 }
 594                 if (!chip->rirb.cmds) {
 595                         smp_rmb();
 596                         return chip->rirb.res; /* the last value */
 597                 }
 598                 if (time_after(jiffies, timeout))
 599                         break;
 600                 if (bus->needs_damn_long_delay)
 601                         msleep(2); /* temporary workaround */
 602                 else {
 603                         udelay(10);
 604                         cond_resched();
 605                 }
 606         }
 607
 608         if (chip->msi) {
 609                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 610                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 611                 free_irq(chip->irq, chip);
 612                 chip->irq = -1;
 613                 pci_disable_msi(chip->pci);
 614                 chip->msi = 0;
 615                 if (azx_acquire_irq(chip, 1) < 0)
 616                         return -1;
 617                 goto again;
 618         }
 619
 620         if (!chip->polling_mode) {
 621                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 622                            "switching to polling mode: last cmd=0x%08x\n",
 623                            chip->last_cmd);
 624                 chip->polling_mode = 1;
 625                 goto again;
 626         }
 627
 628         if (chip->probing) {
 629                 /* If this critical timeout happens during the codec probing
 630                  * phase, this is likely an access to a non-existing codec
 631                  * slot.  Better to return an error and reset the system.
 632                  */
 633                 return -1;
 634         }
 635
 636         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 637                    "switching to single_cmd mode: last cmd=0x%08x\n",
 638                    chip->last_cmd);
 639         chip->rirb.rp = azx_readb(chip, RIRBWP);
 640         chip->rirb.cmds = 0;
 641         /* switch to single_cmd mode */
 642         chip->single_cmd = 1;
 643         azx_free_cmd_io(chip);
 644         return -1;
 645 }
 646
 647 /*
 648  * Use the single immediate command instead of CORB/RIRB for simplicity
 649  *
 650  * Note: according to Intel, this is not preferred use.  The command was
 651  *       intended for the BIOS only, and may get confused with unsolicited
 652  *       responses.  So, we shouldn't use it for normal operation from the
 653  *       driver.
 654  *       I left the codes, however, for debugging/testing purposes.
 655  */
 656
 657 /* send a command */
 658 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 659 {
 660         struct azx *chip = bus->private_data;
 661         int timeout = 50;
 662
 663         while (timeout--) {
 664                 /* check ICB busy bit */
 665                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 666                         /* Clear IRV valid bit */
 667                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 668                                    ICH6_IRS_VALID);
 669                         azx_writel(chip, IC, val);
 670                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 671                                    ICH6_IRS_BUSY);
 672                         return 0;
 673                 }
 674                 udelay(1);
 675         }
 676         if (printk_ratelimit())
 677                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 678                            azx_readw(chip, IRS), val);
 679         return -EIO;
 680 }
 681
 682 /* receive a response */
 683 static unsigned int azx_single_get_response(struct hda_bus *bus)
 684 {
 685         struct azx *chip = bus->private_data;
 686         int timeout = 50;
 687
 688         while (timeout--) {
 689                 /* check IRV busy bit */
 690                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 691                         return azx_readl(chip, IR);
 692                 udelay(1);
 693         }
 694         if (printk_ratelimit())
 695                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 696                            azx_readw(chip, IRS));
 697         return (unsigned int)-1;
 698 }
 699
 700 /*
 701  * The below are the main callbacks from hda_codec.
 702  *
 703  * They are just the skeleton to call sub-callbacks according to the
 704  * current setting of chip->single_cmd.
 705  */
 706
 707 /* send a command */
 708 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 709 {
 710         struct azx *chip = bus->private_data;
 711
 712         chip->last_cmd = val;
 713         if (chip->single_cmd)
 714                 return azx_single_send_cmd(bus, val);
 715         else
 716                 return azx_corb_send_cmd(bus, val);
 717 }
 718
 719 /* get a response */
 720 static unsigned int azx_get_response(struct hda_bus *bus)
 721 {
 722         struct azx *chip = bus->private_data;
 723         if (chip->single_cmd)
 724                 return azx_single_get_response(bus);
 725         else
 726                 return azx_rirb_get_response(bus);
 727 }
 728
 729 #ifdef CONFIG_SND_HDA_POWER_SAVE
 730 static void azx_power_notify(struct hda_bus *bus);
 731 #endif
 732
 733 /* reset codec link */
 734 static int azx_reset(struct azx *chip)
 735 {
 736         int count;
 737
 738         /* clear STATESTS */
 739         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 740
 741         /* reset controller */
 742         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 743
 744         count = 50;
 745         while (azx_readb(chip, GCTL) && --count)
 746                 msleep(1);
 747
 748         /* delay for >= 100us for codec PLL to settle per spec
 749          * Rev 0.9 section 5.5.1
 750          */
 751         msleep(1);
 752
 753         /* Bring controller out of reset */
 754         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 755
 756         count = 50;
 757         while (!azx_readb(chip, GCTL) && --count)
 758                 msleep(1);
 759
 760         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 761         msleep(1);
 762
 763         /* check to see if controller is ready */
 764         if (!azx_readb(chip, GCTL)) {
 765                 snd_printd("azx_reset: controller not ready!\n");
 766                 return -EBUSY;
 767         }
 768
 769         /* Accept unsolicited responses */
 770         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 771
 772         /* detect codecs */
 773         if (!chip->codec_mask) {
 774                 chip->codec_mask = azx_readw(chip, STATESTS);
 775                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 776         }
 777
 778         return 0;
 779 }
 780
 781
 782 /*
 783  * Lowlevel interface
 784  */
 785
 786 /* enable interrupts */
 787 static void azx_int_enable(struct azx *chip)
 788 {
 789         /* enable controller CIE and GIE */
 790         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 791                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 792 }
 793
 794 /* disable interrupts */
 795 static void azx_int_disable(struct azx *chip)
 796 {
 797         int i;
 798
 799         /* disable interrupts in stream descriptor */
 800         for (i = 0; i < chip->num_streams; i++) {
 801                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 802                 azx_sd_writeb(azx_dev, SD_CTL,
 803                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 804         }
 805
 806         /* disable SIE for all streams */
 807         azx_writeb(chip, INTCTL, 0);
 808
 809         /* disable controller CIE and GIE */
 810         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 811                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 812 }
 813
 814 /* clear interrupts */
 815 static void azx_int_clear(struct azx *chip)
 816 {
 817         int i;
 818
 819         /* clear stream status */
 820         for (i = 0; i < chip->num_streams; i++) {
 821                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 822                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 823         }
 824
 825         /* clear STATESTS */
 826         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 827
 828         /* clear rirb status */
 829         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 830
 831         /* clear int status */
 832         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 833 }
 834
 835 /* start a stream */
 836 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 837 {
 838         /*
 839          * Before stream start, initialize parameter
 840          */
 841         azx_dev->insufficient = 1;
 842
 843         /* enable SIE */
 844         azx_writeb(chip, INTCTL,
 845                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 846         /* set DMA start and interrupt mask */
 847         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 848                       SD_CTL_DMA_START | SD_INT_MASK);
 849 }
 850
 851 /* stop a stream */
 852 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 853 {
 854         /* stop DMA */
 855         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 856                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 857         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 858         /* disable SIE */
 859         azx_writeb(chip, INTCTL,
 860                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 861 }
 862
 863
 864 /*
 865  * reset and start the controller registers
 866  */
 867 static void azx_init_chip(struct azx *chip)
 868 {
 869         if (chip->initialized)
 870                 return;
 871
 872         /* reset controller */
 873         azx_reset(chip);
 874
 875         /* initialize interrupts */
 876         azx_int_clear(chip);
 877         azx_int_enable(chip);
 878
 879         /* initialize the codec command I/O */
 880         if (!chip->single_cmd)
 881                 azx_init_cmd_io(chip);
 882
 883         /* program the position buffer */
 884         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 885         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 886
 887         chip->initialized = 1;
 888 }
 889
 890 /*
 891  * initialize the PCI registers
 892  */
 893 /* update bits in a PCI register byte */
 894 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 895                             unsigned char mask, unsigned char val)
 896 {
 897         unsigned char data;
 898
 899         pci_read_config_byte(pci, reg, &data);
 900         data &= ~mask;
 901         data |= (val & mask);
 902         pci_write_config_byte(pci, reg, data);
 903 }
 904
 905 static void azx_init_pci(struct azx *chip)
 906 {
 907         unsigned short snoop;
 908
 909         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 910          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 911          * Ensuring these bits are 0 clears playback static on some HD Audio
 912          * codecs
 913          */
 914         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 915
 916         switch (chip->driver_type) {
 917         case AZX_DRIVER_ATI:
 918                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 919                 update_pci_byte(chip->pci,
 920                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 921                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 922                 break;
 923         case AZX_DRIVER_NVIDIA:
 924                 /* For NVIDIA HDA, enable snoop */
 925                 update_pci_byte(chip->pci,
 926                                 NVIDIA_HDA_TRANSREG_ADDR,
 927                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 928                 update_pci_byte(chip->pci,
 929                                 NVIDIA_HDA_ISTRM_COH,
 930                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 931                 update_pci_byte(chip->pci,
 932                                 NVIDIA_HDA_OSTRM_COH,
 933                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 934                 break;
 935         case AZX_DRIVER_SCH:
 936                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 937                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 938                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 939                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 940                         pci_read_config_word(chip->pci,
 941                                 INTEL_SCH_HDA_DEVC, &snoop);
 942                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 943                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 944                                 ? "Failed" : "OK");
 945                 }
 946                 break;
 947
 948         }
 949 }
 950
 951
 952 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 953
 954 /*
 955  * interrupt handler
 956  */
 957 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 958 {
 959         struct azx *chip = dev_id;
 960         struct azx_dev *azx_dev;
 961         u32 status;
 962         int i;
 963
 964         spin_lock(&chip->reg_lock);
 965
 966         status = azx_readl(chip, INTSTS);
 967         if (status == 0) {
 968                 spin_unlock(&chip->reg_lock);
 969                 return IRQ_NONE;
 970         }
 971
 972         for (i = 0; i < chip->num_streams; i++) {
 973                 azx_dev = &chip->azx_dev[i];
 974                 if (status & azx_dev->sd_int_sta_mask) {
 975                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 976                         if (!azx_dev->substream || !azx_dev->running)
 977                                 continue;
 978                         /* ignore the first dummy IRQ (due to pos_adj) */
 979                         if (azx_dev->irq_ignore) {
 980                                 azx_dev->irq_ignore = 0;
 981                                 continue;
 982                         }
 983                         /* check whether this IRQ is really acceptable */
 984                         if (azx_position_ok(chip, azx_dev)) {
 985                                 azx_dev->irq_pending = 0;
 986                                 spin_unlock(&chip->reg_lock);
 987                                 snd_pcm_period_elapsed(azx_dev->substream);
 988                                 spin_lock(&chip->reg_lock);
 989                         } else {
 990                                 /* bogus IRQ, process it later */
 991                                 azx_dev->irq_pending = 1;
 992                                 schedule_work(&chip->irq_pending_work);
 993                         }
 994                 }
 995         }
 996
 997         /* clear rirb int */
 998         status = azx_readb(chip, RIRBSTS);
 999         if (status & RIRB_INT_MASK) {
1000                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1001                         azx_update_rirb(chip);
1002                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1003         }
1004
1005 #if 0
1006         /* clear state status int */
1007         if (azx_readb(chip, STATESTS) & 0x04)
1008                 azx_writeb(chip, STATESTS, 0x04);
1009 #endif
1010         spin_unlock(&chip->reg_lock);
1011
1012         return IRQ_HANDLED;
1013 }
1014
1015
1016 /*
1017  * set up a BDL entry
1018  */
1019 static int setup_bdle(struct snd_pcm_substream *substream,
1020                       struct azx_dev *azx_dev, u32 **bdlp,
1021                       int ofs, int size, int with_ioc)
1022 {
1023         u32 *bdl = *bdlp;
1024
1025         while (size > 0) {
1026                 dma_addr_t addr;
1027                 int chunk;
1028
1029                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1030                         return -EINVAL;
1031
1032                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1033                 /* program the address field of the BDL entry */
1034                 bdl[0] = cpu_to_le32((u32)addr);
1035                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1036                 /* program the size field of the BDL entry */
1037                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1038                 bdl[2] = cpu_to_le32(chunk);
1039                 /* program the IOC to enable interrupt
1040                  * only when the whole fragment is processed
1041                  */
1042                 size -= chunk;
1043                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1044                 bdl += 4;
1045                 azx_dev->frags++;
1046                 ofs += chunk;
1047         }
1048         *bdlp = bdl;
1049         return ofs;
1050 }
1051
1052 /*
1053  * set up BDL entries
1054  */
1055 static int azx_setup_periods(struct azx *chip,
1056                              struct snd_pcm_substream *substream,
1057                              struct azx_dev *azx_dev)
1058 {
1059         u32 *bdl;
1060         int i, ofs, periods, period_bytes;
1061         int pos_adj;
1062
1063         /* reset BDL address */
1064         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1065         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1066
1067         period_bytes = snd_pcm_lib_period_bytes(substream);
1068         azx_dev->period_bytes = period_bytes;
1069         periods = azx_dev->bufsize / period_bytes;
1070
1071         /* program the initial BDL entries */
1072         bdl = (u32 *)azx_dev->bdl.area;
1073         ofs = 0;
1074         azx_dev->frags = 0;
1075         azx_dev->irq_ignore = 0;
1076         pos_adj = bdl_pos_adj[chip->dev_index];
1077         if (pos_adj > 0) {
1078                 struct snd_pcm_runtime *runtime = substream->runtime;
1079                 int pos_align = pos_adj;
1080                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1081                 if (!pos_adj)
1082                         pos_adj = pos_align;
1083                 else
1084                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1085                                 pos_align;
1086                 pos_adj = frames_to_bytes(runtime, pos_adj);
1087                 if (pos_adj >= period_bytes) {
1088                         snd_printk(KERN_WARNING "Too big adjustment %d\n",
1089                                    bdl_pos_adj[chip->dev_index]);
1090                         pos_adj = 0;
1091                 } else {
1092                         ofs = setup_bdle(substream, azx_dev,
1093                                          &bdl, ofs, pos_adj, 1);
1094                         if (ofs < 0)
1095                                 goto error;
1096                         azx_dev->irq_ignore = 1;
1097                 }
1098         } else
1099                 pos_adj = 0;
1100         for (i = 0; i < periods; i++) {
1101                 if (i == periods - 1 && pos_adj)
1102                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1103                                          period_bytes - pos_adj, 0);
1104                 else
1105                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1106                                          period_bytes, 1);
1107                 if (ofs < 0)
1108                         goto error;
1109         }
1110         return 0;
1111
1112  error:
1113         snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1114                    azx_dev->bufsize, period_bytes);
1115         /* reset */
1116         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1117         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1118         return -EINVAL;
1119 }
1120
1121 /*
1122  * set up the SD for streaming
1123  */
1124 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1125 {
1126         unsigned char val;
1127         int timeout;
1128
1129         /* make sure the run bit is zero for SD */
1130         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1131                       ~SD_CTL_DMA_START);
1132         /* reset stream */
1133         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1134                       SD_CTL_STREAM_RESET);
1135         udelay(3);
1136         timeout = 300;
1137         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1138                --timeout)
1139                 ;
1140         val &= ~SD_CTL_STREAM_RESET;
1141         azx_sd_writeb(azx_dev, SD_CTL, val);
1142         udelay(3);
1143
1144         timeout = 300;
1145         /* waiting for hardware to report that the stream is out of reset */
1146         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1147                --timeout)
1148                 ;
1149
1150         /* program the stream_tag */
1151         azx_sd_writel(azx_dev, SD_CTL,
1152                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1153                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1154
1155         /* program the length of samples in cyclic buffer */
1156         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1157
1158         /* program the stream format */
1159         /* this value needs to be the same as the one programmed */
1160         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1161
1162         /* program the stream LVI (last valid index) of the BDL */
1163         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1164
1165         /* program the BDL address */
1166         /* lower BDL address */
1167         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1168         /* upper BDL address */
1169         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1170
1171         /* enable the position buffer */
1172         if (chip->position_fix == POS_FIX_POSBUF ||
1173             chip->position_fix == POS_FIX_AUTO ||
1174             chip->via_dmapos_patch) {
1175                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1176                         azx_writel(chip, DPLBASE,
1177                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1178         }
1179
1180         /* set the interrupt enable bits in the descriptor control register */
1181         azx_sd_writel(azx_dev, SD_CTL,
1182                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1183
1184         return 0;
1185 }
1186
1187 /*
1188  * Probe the given codec address
1189  */
1190 static int probe_codec(struct azx *chip, int addr)
1191 {
1192         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1193                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1194         unsigned int res;
1195
1196         chip->probing = 1;
1197         azx_send_cmd(chip->bus, cmd);
1198         res = azx_get_response(chip->bus);
1199         chip->probing = 0;
1200         if (res == -1)
1201                 return -EIO;
1202         snd_printdd("hda_intel: codec #%d probed OK\n", addr);
1203         return 0;
1204 }
1205
1206 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1207                                  struct hda_pcm *cpcm);
1208 static void azx_stop_chip(struct azx *chip);
1209
1210 /*
1211  * Codec initialization
1212  */
1213
1214 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1215 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1216         [AZX_DRIVER_TERA] = 1,
1217 };
1218
1219 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1220                                       unsigned int codec_probe_mask)
1221 {
1222         struct hda_bus_template bus_temp;
1223         int c, codecs, err;
1224         int max_slots;
1225
1226         memset(&bus_temp, 0, sizeof(bus_temp));
1227         bus_temp.private_data = chip;
1228         bus_temp.modelname = model;
1229         bus_temp.pci = chip->pci;
1230         bus_temp.ops.command = azx_send_cmd;
1231         bus_temp.ops.get_response = azx_get_response;
1232         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1233 #ifdef CONFIG_SND_HDA_POWER_SAVE
1234         bus_temp.ops.pm_notify = azx_power_notify;
1235 #endif
1236
1237         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1238         if (err < 0)
1239                 return err;
1240
1241         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1242                 chip->bus->needs_damn_long_delay = 1;
1243
1244         codecs = 0;
1245         max_slots = azx_max_codecs[chip->driver_type];
1246         if (!max_slots)
1247                 max_slots = AZX_MAX_CODECS;
1248
1249         /* First try to probe all given codec slots */
1250         for (c = 0; c < max_slots; c++) {
1251                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1252                         if (probe_codec(chip, c) < 0) {
1253                                 /* Some BIOSen give you wrong codec addresses
1254                                  * that don't exist
1255                                  */
1256                                 snd_printk(KERN_WARNING
1257                                            "hda_intel: Codec #%d probe error; "
1258                                            "disabling it...\n", c);
1259                                 chip->codec_mask &= ~(1 << c);
1260                                 /* More badly, accessing to a non-existing
1261                                  * codec often screws up the controller chip,
1262                                  * and distrubs the further communications.
1263                                  * Thus if an error occurs during probing,
1264                                  * better to reset the controller chip to
1265                                  * get back to the sanity state.
1266                                  */
1267                                 azx_stop_chip(chip);
1268                                 azx_init_chip(chip);
1269                         }
1270                 }
1271         }
1272
1273         /* Then create codec instances */
1274         for (c = 0; c < max_slots; c++) {
1275                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1276                         struct hda_codec *codec;
1277                         err = snd_hda_codec_new(chip->bus, c, &codec);
1278                         if (err < 0)
1279                                 continue;
1280                         codecs++;
1281                 }
1282         }
1283         if (!codecs) {
1284                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1285                 return -ENXIO;
1286         }
1287
1288         return 0;
1289 }
1290
1291
1292 /*
1293  * PCM support
1294  */
1295
1296 /* assign a stream for the PCM */
1297 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1298 {
1299         int dev, i, nums;
1300         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1301                 dev = chip->playback_index_offset;
1302                 nums = chip->playback_streams;
1303         } else {
1304                 dev = chip->capture_index_offset;
1305                 nums = chip->capture_streams;
1306         }
1307         for (i = 0; i < nums; i++, dev++)
1308                 if (!chip->azx_dev[dev].opened) {
1309                         chip->azx_dev[dev].opened = 1;
1310                         return &chip->azx_dev[dev];
1311                 }
1312         return NULL;
1313 }
1314
1315 /* release the assigned stream */
1316 static inline void azx_release_device(struct azx_dev *azx_dev)
1317 {
1318         azx_dev->opened = 0;
1319 }
1320
1321 static struct snd_pcm_hardware azx_pcm_hw = {
1322         .info =                 (SNDRV_PCM_INFO_MMAP |
1323                                  SNDRV_PCM_INFO_INTERLEAVED |
1324                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1325                                  SNDRV_PCM_INFO_MMAP_VALID |
1326                                  /* No full-resume yet implemented */
1327                                  /* SNDRV_PCM_INFO_RESUME |*/
1328                                  SNDRV_PCM_INFO_PAUSE |
1329                                  SNDRV_PCM_INFO_SYNC_START),
1330         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1331         .rates =                SNDRV_PCM_RATE_48000,
1332         .rate_min =             48000,
1333         .rate_max =             48000,
1334         .channels_min =         2,
1335         .channels_max =         2,
1336         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1337         .period_bytes_min =     128,
1338         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1339         .periods_min =          2,
1340         .periods_max =          AZX_MAX_FRAG,
1341         .fifo_size =            0,
1342 };
1343
1344 struct azx_pcm {
1345         struct azx *chip;
1346         struct hda_codec *codec;
1347         struct hda_pcm_stream *hinfo[2];
1348 };
1349
1350 static int azx_pcm_open(struct snd_pcm_substream *substream)
1351 {
1352         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1353         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1354         struct azx *chip = apcm->chip;
1355         struct azx_dev *azx_dev;
1356         struct snd_pcm_runtime *runtime = substream->runtime;
1357         unsigned long flags;
1358         int err;
1359
1360         mutex_lock(&chip->open_mutex);
1361         azx_dev = azx_assign_device(chip, substream->stream);
1362         if (azx_dev == NULL) {
1363                 mutex_unlock(&chip->open_mutex);
1364                 return -EBUSY;
1365         }
1366         runtime->hw = azx_pcm_hw;
1367         runtime->hw.channels_min = hinfo->channels_min;
1368         runtime->hw.channels_max = hinfo->channels_max;
1369         runtime->hw.formats = hinfo->formats;
1370         runtime->hw.rates = hinfo->rates;
1371         snd_pcm_limit_hw_rates(runtime);
1372         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1373         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1374                                    128);
1375         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1376                                    128);
1377         snd_hda_power_up(apcm->codec);
1378         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1379         if (err < 0) {
1380                 azx_release_device(azx_dev);
1381                 snd_hda_power_down(apcm->codec);
1382                 mutex_unlock(&chip->open_mutex);
1383                 return err;
1384         }
1385         spin_lock_irqsave(&chip->reg_lock, flags);
1386         azx_dev->substream = substream;
1387         azx_dev->running = 0;
1388         spin_unlock_irqrestore(&chip->reg_lock, flags);
1389
1390         runtime->private_data = azx_dev;
1391         snd_pcm_set_sync(substream);
1392         mutex_unlock(&chip->open_mutex);
1393         return 0;
1394 }
1395
1396 static int azx_pcm_close(struct snd_pcm_substream *substream)
1397 {
1398         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1399         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1400         struct azx *chip = apcm->chip;
1401         struct azx_dev *azx_dev = get_azx_dev(substream);
1402         unsigned long flags;
1403
1404         mutex_lock(&chip->open_mutex);
1405         spin_lock_irqsave(&chip->reg_lock, flags);
1406         azx_dev->substream = NULL;
1407         azx_dev->running = 0;
1408         spin_unlock_irqrestore(&chip->reg_lock, flags);
1409         azx_release_device(azx_dev);
1410         hinfo->ops.close(hinfo, apcm->codec, substream);
1411         snd_hda_power_down(apcm->codec);
1412         mutex_unlock(&chip->open_mutex);
1413         return 0;
1414 }
1415
1416 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1417                              struct snd_pcm_hw_params *hw_params)
1418 {
1419         return snd_pcm_lib_malloc_pages(substream,
1420                                         params_buffer_bytes(hw_params));
1421 }
1422
1423 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1424 {
1425         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1426         struct azx_dev *azx_dev = get_azx_dev(substream);
1427         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1428
1429         /* reset BDL address */
1430         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1431         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1432         azx_sd_writel(azx_dev, SD_CTL, 0);
1433
1434         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1435
1436         return snd_pcm_lib_free_pages(substream);
1437 }
1438
1439 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1440 {
1441         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1442         struct azx *chip = apcm->chip;
1443         struct azx_dev *azx_dev = get_azx_dev(substream);
1444         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1445         struct snd_pcm_runtime *runtime = substream->runtime;
1446
1447         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1448         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1449                                                          runtime->channels,
1450                                                          runtime->format,
1451                                                          hinfo->maxbps);
1452         if (!azx_dev->format_val) {
1453                 snd_printk(KERN_ERR SFX
1454                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1455                            runtime->rate, runtime->channels, runtime->format);
1456                 return -EINVAL;
1457         }
1458
1459         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1460                     azx_dev->bufsize, azx_dev->format_val);
1461         if (azx_setup_periods(chip, substream, azx_dev) < 0)
1462                 return -EINVAL;
1463         azx_setup_controller(chip, azx_dev);
1464         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1465                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1466         else
1467                 azx_dev->fifo_size = 0;
1468
1469         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1470                                   azx_dev->format_val, substream);
1471 }
1472
1473 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1474 {
1475         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1476         struct azx *chip = apcm->chip;
1477         struct azx_dev *azx_dev;
1478         struct snd_pcm_substream *s;
1479         int start, nsync = 0, sbits = 0;
1480         int nwait, timeout;
1481
1482         switch (cmd) {
1483         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1484         case SNDRV_PCM_TRIGGER_RESUME:
1485         case SNDRV_PCM_TRIGGER_START:
1486                 start = 1;
1487                 break;
1488         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1489         case SNDRV_PCM_TRIGGER_SUSPEND:
1490         case SNDRV_PCM_TRIGGER_STOP:
1491                 start = 0;
1492                 break;
1493         default:
1494                 return -EINVAL;
1495         }
1496
1497         snd_pcm_group_for_each_entry(s, substream) {
1498                 if (s->pcm->card != substream->pcm->card)
1499                         continue;
1500                 azx_dev = get_azx_dev(s);
1501                 sbits |= 1 << azx_dev->index;
1502                 nsync++;
1503                 snd_pcm_trigger_done(s, substream);
1504         }
1505
1506         spin_lock(&chip->reg_lock);
1507         if (nsync > 1) {
1508                 /* first, set SYNC bits of corresponding streams */
1509                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1510         }
1511         snd_pcm_group_for_each_entry(s, substream) {
1512                 if (s->pcm->card != substream->pcm->card)
1513                         continue;
1514                 azx_dev = get_azx_dev(s);
1515                 if (start)
1516                         azx_stream_start(chip, azx_dev);
1517                 else
1518                         azx_stream_stop(chip, azx_dev);
1519                 azx_dev->running = start;
1520         }
1521         spin_unlock(&chip->reg_lock);
1522         if (start) {
1523                 if (nsync == 1)
1524                         return 0;
1525                 /* wait until all FIFOs get ready */
1526                 for (timeout = 5000; timeout; timeout--) {
1527                         nwait = 0;
1528                         snd_pcm_group_for_each_entry(s, substream) {
1529                                 if (s->pcm->card != substream->pcm->card)
1530                                         continue;
1531                                 azx_dev = get_azx_dev(s);
1532                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1533                                       SD_STS_FIFO_READY))
1534                                         nwait++;
1535                         }
1536                         if (!nwait)
1537                                 break;
1538                         cpu_relax();
1539                 }
1540         } else {
1541                 /* wait until all RUN bits are cleared */
1542                 for (timeout = 5000; timeout; timeout--) {
1543                         nwait = 0;
1544                         snd_pcm_group_for_each_entry(s, substream) {
1545                                 if (s->pcm->card != substream->pcm->card)
1546                                         continue;
1547                                 azx_dev = get_azx_dev(s);
1548                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1549                                     SD_CTL_DMA_START)
1550                                         nwait++;
1551                         }
1552                         if (!nwait)
1553                                 break;
1554                         cpu_relax();
1555                 }
1556         }
1557         if (nsync > 1) {
1558                 spin_lock(&chip->reg_lock);
1559                 /* reset SYNC bits */
1560                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1561                 spin_unlock(&chip->reg_lock);
1562         }
1563         return 0;
1564 }
1565
1566 /* get the current DMA position with correction on VIA chips */
1567 static unsigned int azx_via_get_position(struct azx *chip,
1568                                          struct azx_dev *azx_dev)
1569 {
1570         unsigned int link_pos, mini_pos, bound_pos;
1571         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1572         unsigned int fifo_size;
1573
1574         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1575         if (azx_dev->index >= 4) {
1576                 /* Playback, no problem using link position */
1577                 return link_pos;
1578         }
1579
1580         /* Capture */
1581         /* For new chipset,
1582          * use mod to get the DMA position just like old chipset
1583          */
1584         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1585         mod_dma_pos %= azx_dev->period_bytes;
1586
1587         /* azx_dev->fifo_size can't get FIFO size of in stream.
1588          * Get from base address + offset.
1589          */
1590         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1591
1592         if (azx_dev->insufficient) {
1593                 /* Link position never gather than FIFO size */
1594                 if (link_pos <= fifo_size)
1595                         return 0;
1596
1597                 azx_dev->insufficient = 0;
1598         }
1599
1600         if (link_pos <= fifo_size)
1601                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1602         else
1603                 mini_pos = link_pos - fifo_size;
1604
1605         /* Find nearest previous boudary */
1606         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1607         mod_link_pos = link_pos % azx_dev->period_bytes;
1608         if (mod_link_pos >= fifo_size)
1609                 bound_pos = link_pos - mod_link_pos;
1610         else if (mod_dma_pos >= mod_mini_pos)
1611                 bound_pos = mini_pos - mod_mini_pos;
1612         else {
1613                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1614                 if (bound_pos >= azx_dev->bufsize)
1615                         bound_pos = 0;
1616         }
1617
1618         /* Calculate real DMA position we want */
1619         return bound_pos + mod_dma_pos;
1620 }
1621
1622 static unsigned int azx_get_position(struct azx *chip,
1623                                      struct azx_dev *azx_dev)
1624 {
1625         unsigned int pos;
1626
1627         if (chip->via_dmapos_patch)
1628                 pos = azx_via_get_position(chip, azx_dev);
1629         else if (chip->position_fix == POS_FIX_POSBUF ||
1630                  chip->position_fix == POS_FIX_AUTO) {
1631                 /* use the position buffer */
1632                 pos = le32_to_cpu(*azx_dev->posbuf);
1633         } else {
1634                 /* read LPIB */
1635                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1636         }
1637         if (pos >= azx_dev->bufsize)
1638                 pos = 0;
1639         return pos;
1640 }
1641
1642 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1643 {
1644         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1645         struct azx *chip = apcm->chip;
1646         struct azx_dev *azx_dev = get_azx_dev(substream);
1647         return bytes_to_frames(substream->runtime,
1648                                azx_get_position(chip, azx_dev));
1649 }
1650
1651 /*
1652  * Check whether the current DMA position is acceptable for updating
1653  * periods.  Returns non-zero if it's OK.
1654  *
1655  * Many HD-audio controllers appear pretty inaccurate about
1656  * the update-IRQ timing.  The IRQ is issued before actually the
1657  * data is processed.  So, we need to process it afterwords in a
1658  * workqueue.
1659  */
1660 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1661 {
1662         unsigned int pos;
1663
1664         pos = azx_get_position(chip, azx_dev);
1665         if (chip->position_fix == POS_FIX_AUTO) {
1666                 if (!pos) {
1667                         printk(KERN_WARNING
1668                                "hda-intel: Invalid position buffer, "
1669                                "using LPIB read method instead.\n");
1670                         chip->position_fix = POS_FIX_LPIB;
1671                         pos = azx_get_position(chip, azx_dev);
1672                 } else
1673                         chip->position_fix = POS_FIX_POSBUF;
1674         }
1675
1676         if (!bdl_pos_adj[chip->dev_index])
1677                 return 1; /* no delayed ack */
1678         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1679                 return 0; /* NG - it's below the period boundary */
1680         return 1; /* OK, it's fine */
1681 }
1682
1683 /*
1684  * The work for pending PCM period updates.
1685  */
1686 static void azx_irq_pending_work(struct work_struct *work)
1687 {
1688         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1689         int i, pending;
1690
1691         if (!chip->irq_pending_warned) {
1692                 printk(KERN_WARNING
1693                        "hda-intel: IRQ timing workaround is activated "
1694                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1695                        chip->card->number);
1696                 chip->irq_pending_warned = 1;
1697         }
1698
1699         for (;;) {
1700                 pending = 0;
1701                 spin_lock_irq(&chip->reg_lock);
1702                 for (i = 0; i < chip->num_streams; i++) {
1703                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1704                         if (!azx_dev->irq_pending ||
1705                             !azx_dev->substream ||
1706                             !azx_dev->running)
1707                                 continue;
1708                         if (azx_position_ok(chip, azx_dev)) {
1709                                 azx_dev->irq_pending = 0;
1710                                 spin_unlock(&chip->reg_lock);
1711                                 snd_pcm_period_elapsed(azx_dev->substream);
1712                                 spin_lock(&chip->reg_lock);
1713                         } else
1714                                 pending++;
1715                 }
1716                 spin_unlock_irq(&chip->reg_lock);
1717                 if (!pending)
1718                         return;
1719                 cond_resched();
1720         }
1721 }
1722
1723 /* clear irq_pending flags and assure no on-going workq */
1724 static void azx_clear_irq_pending(struct azx *chip)
1725 {
1726         int i;
1727
1728         spin_lock_irq(&chip->reg_lock);
1729         for (i = 0; i < chip->num_streams; i++)
1730                 chip->azx_dev[i].irq_pending = 0;
1731         spin_unlock_irq(&chip->reg_lock);
1732         flush_scheduled_work();
1733 }
1734
1735 static struct snd_pcm_ops azx_pcm_ops = {
1736         .open = azx_pcm_open,
1737         .close = azx_pcm_close,
1738         .ioctl = snd_pcm_lib_ioctl,
1739         .hw_params = azx_pcm_hw_params,
1740         .hw_free = azx_pcm_hw_free,
1741         .prepare = azx_pcm_prepare,
1742         .trigger = azx_pcm_trigger,
1743         .pointer = azx_pcm_pointer,
1744         .page = snd_pcm_sgbuf_ops_page,
1745 };
1746
1747 static void azx_pcm_free(struct snd_pcm *pcm)
1748 {
1749         struct azx_pcm *apcm = pcm->private_data;
1750         if (apcm) {
1751                 apcm->chip->pcm[pcm->device] = NULL;
1752                 kfree(apcm);
1753         }
1754 }
1755
1756 static int
1757 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1758                       struct hda_pcm *cpcm)
1759 {
1760         struct azx *chip = bus->private_data;
1761         struct snd_pcm *pcm;
1762         struct azx_pcm *apcm;
1763         int pcm_dev = cpcm->device;
1764         int s, err;
1765
1766         if (pcm_dev >= AZX_MAX_PCMS) {
1767                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1768                            pcm_dev);
1769                 return -EINVAL;
1770         }
1771         if (chip->pcm[pcm_dev]) {
1772                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1773                 return -EBUSY;
1774         }
1775         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1776                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1777                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1778                           &pcm);
1779         if (err < 0)
1780                 return err;
1781         strcpy(pcm->name, cpcm->name);
1782         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1783         if (apcm == NULL)
1784                 return -ENOMEM;
1785         apcm->chip = chip;
1786         apcm->codec = codec;
1787         pcm->private_data = apcm;
1788         pcm->private_free = azx_pcm_free;
1789         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1790                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1791         chip->pcm[pcm_dev] = pcm;
1792         cpcm->pcm = pcm;
1793         for (s = 0; s < 2; s++) {
1794                 apcm->hinfo[s] = &cpcm->stream[s];
1795                 if (cpcm->stream[s].substreams)
1796                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1797         }
1798         /* buffer pre-allocation */
1799         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1800                                               snd_dma_pci_data(chip->pci),
1801                                               1024 * 64, 32 * 1024 * 1024);
1802         return 0;
1803 }
1804
1805 /*
1806  * mixer creation - all stuff is implemented in hda module
1807  */
1808 static int __devinit azx_mixer_create(struct azx *chip)
1809 {
1810         return snd_hda_build_controls(chip->bus);
1811 }
1812
1813
1814 /*
1815  * initialize SD streams
1816  */
1817 static int __devinit azx_init_stream(struct azx *chip)
1818 {
1819         int i;
1820
1821         /* initialize each stream (aka device)
1822          * assign the starting bdl address to each stream (device)
1823          * and initialize
1824          */
1825         for (i = 0; i < chip->num_streams; i++) {
1826                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1827                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1828                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1829                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1830                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1831                 azx_dev->sd_int_sta_mask = 1 << i;
1832                 /* stream tag: must be non-zero and unique */
1833                 azx_dev->index = i;
1834                 azx_dev->stream_tag = i + 1;
1835         }
1836
1837         return 0;
1838 }
1839
1840 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1841 {
1842         if (request_irq(chip->pci->irq, azx_interrupt,
1843                         chip->msi ? 0 : IRQF_SHARED,
1844                         "HDA Intel", chip)) {
1845                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1846                        "disabling device\n", chip->pci->irq);
1847                 if (do_disconnect)
1848                         snd_card_disconnect(chip->card);
1849                 return -1;
1850         }
1851         chip->irq = chip->pci->irq;
1852         pci_intx(chip->pci, !chip->msi);
1853         return 0;
1854 }
1855
1856
1857 static void azx_stop_chip(struct azx *chip)
1858 {
1859         if (!chip->initialized)
1860                 return;
1861
1862         /* disable interrupts */
1863         azx_int_disable(chip);
1864         azx_int_clear(chip);
1865
1866         /* disable CORB/RIRB */
1867         azx_free_cmd_io(chip);
1868
1869         /* disable position buffer */
1870         azx_writel(chip, DPLBASE, 0);
1871         azx_writel(chip, DPUBASE, 0);
1872
1873         chip->initialized = 0;
1874 }
1875
1876 #ifdef CONFIG_SND_HDA_POWER_SAVE
1877 /* power-up/down the controller */
1878 static void azx_power_notify(struct hda_bus *bus)
1879 {
1880         struct azx *chip = bus->private_data;
1881         struct hda_codec *c;
1882         int power_on = 0;
1883
1884         list_for_each_entry(c, &bus->codec_list, list) {
1885                 if (c->power_on) {
1886                         power_on = 1;
1887                         break;
1888                 }
1889         }
1890         if (power_on)
1891                 azx_init_chip(chip);
1892         else if (chip->running && power_save_controller)
1893                 azx_stop_chip(chip);
1894 }
1895 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1896
1897 #ifdef CONFIG_PM
1898 /*
1899  * power management
1900  */
1901 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1902 {
1903         struct snd_card *card = pci_get_drvdata(pci);
1904         struct azx *chip = card->private_data;
1905         int i;
1906
1907         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1908         azx_clear_irq_pending(chip);
1909         for (i = 0; i < AZX_MAX_PCMS; i++)
1910                 snd_pcm_suspend_all(chip->pcm[i]);
1911         if (chip->initialized)
1912                 snd_hda_suspend(chip->bus, state);
1913         azx_stop_chip(chip);
1914         if (chip->irq >= 0) {
1915                 free_irq(chip->irq, chip);
1916                 chip->irq = -1;
1917         }
1918         if (chip->msi)
1919                 pci_disable_msi(chip->pci);
1920         pci_disable_device(pci);
1921         pci_save_state(pci);
1922         pci_set_power_state(pci, pci_choose_state(pci, state));
1923         return 0;
1924 }
1925
1926 static int azx_resume(struct pci_dev *pci)
1927 {
1928         struct snd_card *card = pci_get_drvdata(pci);
1929         struct azx *chip = card->private_data;
1930
1931         pci_set_power_state(pci, PCI_D0);
1932         pci_restore_state(pci);
1933         if (pci_enable_device(pci) < 0) {
1934                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1935                        "disabling device\n");
1936                 snd_card_disconnect(card);
1937                 return -EIO;
1938         }
1939         pci_set_master(pci);
1940         if (chip->msi)
1941                 if (pci_enable_msi(pci) < 0)
1942                         chip->msi = 0;
1943         if (azx_acquire_irq(chip, 1) < 0)
1944                 return -EIO;
1945         azx_init_pci(chip);
1946
1947         if (snd_hda_codecs_inuse(chip->bus))
1948                 azx_init_chip(chip);
1949
1950         snd_hda_resume(chip->bus);
1951         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1952         return 0;
1953 }
1954 #endif /* CONFIG_PM */
1955
1956
1957 /*
1958  * reboot notifier for hang-up problem at power-down
1959  */
1960 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1961 {
1962         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1963         azx_stop_chip(chip);
1964         return NOTIFY_OK;
1965 }
1966
1967 static void azx_notifier_register(struct azx *chip)
1968 {
1969         chip->reboot_notifier.notifier_call = azx_halt;
1970         register_reboot_notifier(&chip->reboot_notifier);
1971 }
1972
1973 static void azx_notifier_unregister(struct azx *chip)
1974 {
1975         if (chip->reboot_notifier.notifier_call)
1976                 unregister_reboot_notifier(&chip->reboot_notifier);
1977 }
1978
1979 /*
1980  * destructor
1981  */
1982 static int azx_free(struct azx *chip)
1983 {
1984         int i;
1985
1986         azx_notifier_unregister(chip);
1987
1988         if (chip->initialized) {
1989                 azx_clear_irq_pending(chip);
1990                 for (i = 0; i < chip->num_streams; i++)
1991                         azx_stream_stop(chip, &chip->azx_dev[i]);
1992                 azx_stop_chip(chip);
1993         }
1994
1995         if (chip->irq >= 0)
1996                 free_irq(chip->irq, (void*)chip);
1997         if (chip->msi)
1998                 pci_disable_msi(chip->pci);
1999         if (chip->remap_addr)
2000                 iounmap(chip->remap_addr);
2001
2002         if (chip->azx_dev) {
2003                 for (i = 0; i < chip->num_streams; i++)
2004                         if (chip->azx_dev[i].bdl.area)
2005                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2006         }
2007         if (chip->rb.area)
2008                 snd_dma_free_pages(&chip->rb);
2009         if (chip->posbuf.area)
2010                 snd_dma_free_pages(&chip->posbuf);
2011         pci_release_regions(chip->pci);
2012         pci_disable_device(chip->pci);
2013         kfree(chip->azx_dev);
2014         kfree(chip);
2015
2016         return 0;
2017 }
2018
2019 static int azx_dev_free(struct snd_device *device)
2020 {
2021         return azx_free(device->device_data);
2022 }
2023
2024 /*
2025  * white/black-listing for position_fix
2026  */
2027 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2028         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2029         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2030         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2031         {}
2032 };
2033
2034 static int __devinit check_position_fix(struct azx *chip, int fix)
2035 {
2036         const struct snd_pci_quirk *q;
2037
2038         /* Check VIA HD Audio Controller exist */
2039         if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
2040             chip->pci->device == VIA_HDAC_DEVICE_ID) {
2041                 chip->via_dmapos_patch = 1;
2042                 /* Use link position directly, avoid any transfer problem. */
2043                 return POS_FIX_LPIB;
2044         }
2045         chip->via_dmapos_patch = 0;
2046
2047         if (fix == POS_FIX_AUTO) {
2048                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2049                 if (q) {
2050                         printk(KERN_INFO
2051                                     "hda_intel: position_fix set to %d "
2052                                     "for device %04x:%04x\n",
2053                                     q->value, q->subvendor, q->subdevice);
2054                         return q->value;
2055                 }
2056         }
2057         return fix;
2058 }
2059
2060 /*
2061  * black-lists for probe_mask
2062  */
2063 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2064         /* Thinkpad often breaks the controller communication when accessing
2065          * to the non-working (or non-existing) modem codec slot.
2066          */
2067         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2068         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2069         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2070         /* broken BIOS */
2071         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2072         {}
2073 };
2074
2075 static void __devinit check_probe_mask(struct azx *chip, int dev)
2076 {
2077         const struct snd_pci_quirk *q;
2078
2079         if (probe_mask[dev] == -1) {
2080                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2081                 if (q) {
2082                         printk(KERN_INFO
2083                                "hda_intel: probe_mask set to 0x%x "
2084                                "for device %04x:%04x\n",
2085                                q->value, q->subvendor, q->subdevice);
2086                         probe_mask[dev] = q->value;
2087                 }
2088         }
2089 }
2090
2091
2092 /*
2093  * constructor
2094  */
2095 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2096                                 int dev, int driver_type,
2097                                 struct azx **rchip)
2098 {
2099         struct azx *chip;
2100         int i, err;
2101         unsigned short gcap;
2102         static struct snd_device_ops ops = {
2103                 .dev_free = azx_dev_free,
2104         };
2105
2106         *rchip = NULL;
2107
2108         err = pci_enable_device(pci);
2109         if (err < 0)
2110                 return err;
2111
2112         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2113         if (!chip) {
2114                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2115                 pci_disable_device(pci);
2116                 return -ENOMEM;
2117         }
2118
2119         spin_lock_init(&chip->reg_lock);
2120         mutex_init(&chip->open_mutex);
2121         chip->card = card;
2122         chip->pci = pci;
2123         chip->irq = -1;
2124         chip->driver_type = driver_type;
2125         chip->msi = enable_msi;
2126         chip->dev_index = dev;
2127         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2128
2129         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2130         check_probe_mask(chip, dev);
2131
2132         chip->single_cmd = single_cmd;
2133
2134         if (bdl_pos_adj[dev] < 0) {
2135                 switch (chip->driver_type) {
2136                 case AZX_DRIVER_ICH:
2137                         bdl_pos_adj[dev] = 1;
2138                         break;
2139                 default:
2140                         bdl_pos_adj[dev] = 32;
2141                         break;
2142                 }
2143         }
2144
2145 #if BITS_PER_LONG != 64
2146         /* Fix up base address on ULI M5461 */
2147         if (chip->driver_type == AZX_DRIVER_ULI) {
2148                 u16 tmp3;
2149                 pci_read_config_word(pci, 0x40, &tmp3);
2150                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2151                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2152         }
2153 #endif
2154
2155         err = pci_request_regions(pci, "ICH HD audio");
2156         if (err < 0) {
2157                 kfree(chip);
2158                 pci_disable_device(pci);
2159                 return err;
2160         }
2161
2162         chip->addr = pci_resource_start(pci, 0);
2163         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2164         if (chip->remap_addr == NULL) {
2165                 snd_printk(KERN_ERR SFX "ioremap error\n");
2166                 err = -ENXIO;
2167                 goto errout;
2168         }
2169
2170         if (chip->msi)
2171                 if (pci_enable_msi(pci) < 0)
2172                         chip->msi = 0;
2173
2174         if (azx_acquire_irq(chip, 0) < 0) {
2175                 err = -EBUSY;
2176                 goto errout;
2177         }
2178
2179         pci_set_master(pci);
2180         synchronize_irq(chip->irq);
2181
2182         gcap = azx_readw(chip, GCAP);
2183         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2184
2185         /* allow 64bit DMA address if supported by H/W */
2186         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2187                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2188
2189         /* read number of streams from GCAP register instead of using
2190          * hardcoded value
2191          */
2192         chip->capture_streams = (gcap >> 8) & 0x0f;
2193         chip->playback_streams = (gcap >> 12) & 0x0f;
2194         if (!chip->playback_streams && !chip->capture_streams) {
2195                 /* gcap didn't give any info, switching to old method */
2196
2197                 switch (chip->driver_type) {
2198                 case AZX_DRIVER_ULI:
2199                         chip->playback_streams = ULI_NUM_PLAYBACK;
2200                         chip->capture_streams = ULI_NUM_CAPTURE;
2201                         break;
2202                 case AZX_DRIVER_ATIHDMI:
2203                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2204                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2205                         break;
2206                 default:
2207                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2208                         chip->capture_streams = ICH6_NUM_CAPTURE;
2209                         break;
2210                 }
2211         }
2212         chip->capture_index_offset = 0;
2213         chip->playback_index_offset = chip->capture_streams;
2214         chip->num_streams = chip->playback_streams + chip->capture_streams;
2215         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2216                                 GFP_KERNEL);
2217         if (!chip->azx_dev) {
2218                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2219                 goto errout;
2220         }
2221
2222         for (i = 0; i < chip->num_streams; i++) {
2223                 /* allocate memory for the BDL for each stream */
2224                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2225                                           snd_dma_pci_data(chip->pci),
2226                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2227                 if (err < 0) {
2228                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2229                         goto errout;
2230                 }
2231         }
2232         /* allocate memory for the position buffer */
2233         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2234                                   snd_dma_pci_data(chip->pci),
2235                                   chip->num_streams * 8, &chip->posbuf);
2236         if (err < 0) {
2237                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2238                 goto errout;
2239         }
2240         /* allocate CORB/RIRB */
2241         if (!chip->single_cmd) {
2242                 err = azx_alloc_cmd_io(chip);
2243                 if (err < 0)
2244                         goto errout;
2245         }
2246
2247         /* initialize streams */
2248         azx_init_stream(chip);
2249
2250         /* initialize chip */
2251         azx_init_pci(chip);
2252         azx_init_chip(chip);
2253
2254         /* codec detection */
2255         if (!chip->codec_mask) {
2256                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2257                 err = -ENODEV;
2258                 goto errout;
2259         }
2260
2261         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2262         if (err <0) {
2263                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2264                 goto errout;
2265         }
2266
2267         strcpy(card->driver, "HDA-Intel");
2268         strcpy(card->shortname, driver_short_names[chip->driver_type]);
2269         sprintf(card->longname, "%s at 0x%lx irq %i",
2270                 card->shortname, chip->addr, chip->irq);
2271
2272         *rchip = chip;
2273         return 0;
2274
2275  errout:
2276         azx_free(chip);
2277         return err;
2278 }
2279
2280 static void power_down_all_codecs(struct azx *chip)
2281 {
2282 #ifdef CONFIG_SND_HDA_POWER_SAVE
2283         /* The codecs were powered up in snd_hda_codec_new().
2284          * Now all initialization done, so turn them down if possible
2285          */
2286         struct hda_codec *codec;
2287         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2288                 snd_hda_power_down(codec);
2289         }
2290 #endif
2291 }
2292
2293 static int __devinit azx_probe(struct pci_dev *pci,
2294                                const struct pci_device_id *pci_id)
2295 {
2296         static int dev;
2297         struct snd_card *card;
2298         struct azx *chip;
2299         int err;
2300
2301         if (dev >= SNDRV_CARDS)
2302                 return -ENODEV;
2303         if (!enable[dev]) {
2304                 dev++;
2305                 return -ENOENT;
2306         }
2307
2308         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2309         if (!card) {
2310                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2311                 return -ENOMEM;
2312         }
2313
2314         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2315         if (err < 0) {
2316                 snd_card_free(card);
2317                 return err;
2318         }
2319         card->private_data = chip;
2320
2321         /* create codec instances */
2322         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2323         if (err < 0) {
2324                 snd_card_free(card);
2325                 return err;
2326         }
2327
2328         /* create PCM streams */
2329         err = snd_hda_build_pcms(chip->bus);
2330         if (err < 0) {
2331                 snd_card_free(card);
2332                 return err;
2333         }
2334
2335         /* create mixer controls */
2336         err = azx_mixer_create(chip);
2337         if (err < 0) {
2338                 snd_card_free(card);
2339                 return err;
2340         }
2341
2342         snd_card_set_dev(card, &pci->dev);
2343
2344         err = snd_card_register(card);
2345         if (err < 0) {
2346                 snd_card_free(card);
2347                 return err;
2348         }
2349
2350         pci_set_drvdata(pci, card);
2351         chip->running = 1;
2352         power_down_all_codecs(chip);
2353         azx_notifier_register(chip);
2354
2355         dev++;
2356         return err;
2357 }
2358
2359 static void __devexit azx_remove(struct pci_dev *pci)
2360 {
2361         snd_card_free(pci_get_drvdata(pci));
2362         pci_set_drvdata(pci, NULL);
2363 }
2364
2365 /* PCI IDs */
2366 static struct pci_device_id azx_ids[] = {
2367         /* ICH 6..10 */
2368         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2369         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2370         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2371         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2372         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2373         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2374         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2375         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2376         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2377         /* PCH */
2378         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2379         /* SCH */
2380         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2381         /* ATI SB 450/600 */
2382         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2383         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2384         /* ATI HDMI */
2385         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2386         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2387         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2388         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2389         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2390         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2391         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2392         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2393         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2394         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2395         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2396         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2397         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2398         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2399         /* VIA VT8251/VT8237A */
2400         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2401         /* SIS966 */
2402         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2403         /* ULI M5461 */
2404         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2405         /* NVIDIA MCP */
2406         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2407         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2408         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2409         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2410         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2411         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2412         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2413         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2414         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2415         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2416         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2417         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2418         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2419         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2420         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2421         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2422         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2423         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2424         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2425         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2426         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2427         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2428         /* Teradici */
2429         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2430         { 0, }
2431 };
2432 MODULE_DEVICE_TABLE(pci, azx_ids);
2433
2434 /* pci_driver definition */
2435 static struct pci_driver driver = {
2436         .name = "HDA Intel",
2437         .id_table = azx_ids,
2438         .probe = azx_probe,
2439         .remove = __devexit_p(azx_remove),
2440 #ifdef CONFIG_PM
2441         .suspend = azx_suspend,
2442         .resume = azx_resume,
2443 #endif
2444 };
2445
2446 static int __init alsa_card_azx_init(void)
2447 {
2448         return pci_register_driver(&driver);
2449 }
2450
2451 static void __exit alsa_card_azx_exit(void)
2452 {
2453         pci_unregister_driver(&driver);
2454 }
2455
2456 module_init(alsa_card_azx_init)
2457 module_exit(alsa_card_azx_exit)