sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <sound/core.h>
  49 #include <sound/initval.h>
  50 #include "hda_codec.h"
  51
  52
  53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  56 static char *model[SNDRV_CARDS];
  57 static int position_fix[SNDRV_CARDS];
  58 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  59 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int single_cmd;
  61 static int enable_msi;
  62
  63 module_param_array(index, int, NULL, 0444);
  64 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  65 module_param_array(id, charp, NULL, 0444);
  66 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  67 module_param_array(enable, bool, NULL, 0444);
  68 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  69 module_param_array(model, charp, NULL, 0444);
  70 MODULE_PARM_DESC(model, "Use the given board model.");
  71 module_param_array(position_fix, int, NULL, 0444);
  72 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  73                  "(0 = auto, 1 = none, 2 = POSBUF).");
  74 module_param_array(bdl_pos_adj, int, NULL, 0644);
  75 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  76 module_param_array(probe_mask, int, NULL, 0444);
  77 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  78 module_param(single_cmd, bool, 0444);
  79 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  80                  "(for debugging only).");
  81 module_param(enable_msi, int, 0444);
  82 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  83
  84 #ifdef CONFIG_SND_HDA_POWER_SAVE
  85 /* power_save option is defined in hda_codec.c */
  86
  87 /* reset the HD-audio controller in power save mode.
  88  * this may give more power-saving, but will take longer time to
  89  * wake up.
  90  */
  91 static int power_save_controller = 1;
  92 module_param(power_save_controller, bool, 0644);
  93 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  94 #endif
  95
  96 MODULE_LICENSE("GPL");
  97 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  98                          "{Intel, ICH6M},"
  99                          "{Intel, ICH7},"
 100                          "{Intel, ESB2},"
 101                          "{Intel, ICH8},"
 102                          "{Intel, ICH9},"
 103                          "{Intel, ICH10},"
 104                          "{Intel, PCH},"
 105                          "{Intel, SCH},"
 106                          "{ATI, SB450},"
 107                          "{ATI, SB600},"
 108                          "{ATI, RS600},"
 109                          "{ATI, RS690},"
 110                          "{ATI, RS780},"
 111                          "{ATI, R600},"
 112                          "{ATI, RV630},"
 113                          "{ATI, RV610},"
 114                          "{ATI, RV670},"
 115                          "{ATI, RV635},"
 116                          "{ATI, RV620},"
 117                          "{ATI, RV770},"
 118                          "{VIA, VT8251},"
 119                          "{VIA, VT8237A},"
 120                          "{SiS, SIS966},"
 121                          "{ULI, M5461}}");
 122 MODULE_DESCRIPTION("Intel HDA driver");
 123
 124 #define SFX     "hda-intel: "
 125
 126
 127 /*
 128  * registers
 129  */
 130 #define ICH6_REG_GCAP                   0x00
 131 #define ICH6_REG_VMIN                   0x02
 132 #define ICH6_REG_VMAJ                   0x03
 133 #define ICH6_REG_OUTPAY                 0x04
 134 #define ICH6_REG_INPAY                  0x06
 135 #define ICH6_REG_GCTL                   0x08
 136 #define ICH6_REG_WAKEEN                 0x0c
 137 #define ICH6_REG_STATESTS               0x0e
 138 #define ICH6_REG_GSTS                   0x10
 139 #define ICH6_REG_INTCTL                 0x20
 140 #define ICH6_REG_INTSTS                 0x24
 141 #define ICH6_REG_WALCLK                 0x30
 142 #define ICH6_REG_SYNC                   0x34
 143 #define ICH6_REG_CORBLBASE              0x40
 144 #define ICH6_REG_CORBUBASE              0x44
 145 #define ICH6_REG_CORBWP                 0x48
 146 #define ICH6_REG_CORBRP                 0x4A
 147 #define ICH6_REG_CORBCTL                0x4c
 148 #define ICH6_REG_CORBSTS                0x4d
 149 #define ICH6_REG_CORBSIZE               0x4e
 150
 151 #define ICH6_REG_RIRBLBASE              0x50
 152 #define ICH6_REG_RIRBUBASE              0x54
 153 #define ICH6_REG_RIRBWP                 0x58
 154 #define ICH6_REG_RINTCNT                0x5a
 155 #define ICH6_REG_RIRBCTL                0x5c
 156 #define ICH6_REG_RIRBSTS                0x5d
 157 #define ICH6_REG_RIRBSIZE               0x5e
 158
 159 #define ICH6_REG_IC                     0x60
 160 #define ICH6_REG_IR                     0x64
 161 #define ICH6_REG_IRS                    0x68
 162 #define   ICH6_IRS_VALID        (1<<1)
 163 #define   ICH6_IRS_BUSY         (1<<0)
 164
 165 #define ICH6_REG_DPLBASE                0x70
 166 #define ICH6_REG_DPUBASE                0x74
 167 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 168
 169 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 170 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 171
 172 /* stream register offsets from stream base */
 173 #define ICH6_REG_SD_CTL                 0x00
 174 #define ICH6_REG_SD_STS                 0x03
 175 #define ICH6_REG_SD_LPIB                0x04
 176 #define ICH6_REG_SD_CBL                 0x08
 177 #define ICH6_REG_SD_LVI                 0x0c
 178 #define ICH6_REG_SD_FIFOW               0x0e
 179 #define ICH6_REG_SD_FIFOSIZE            0x10
 180 #define ICH6_REG_SD_FORMAT              0x12
 181 #define ICH6_REG_SD_BDLPL               0x18
 182 #define ICH6_REG_SD_BDLPU               0x1c
 183
 184 /* PCI space */
 185 #define ICH6_PCIREG_TCSEL       0x44
 186
 187 /*
 188  * other constants
 189  */
 190
 191 /* max number of SDs */
 192 /* ICH, ATI and VIA have 4 playback and 4 capture */
 193 #define ICH6_NUM_CAPTURE        4
 194 #define ICH6_NUM_PLAYBACK       4
 195
 196 /* ULI has 6 playback and 5 capture */
 197 #define ULI_NUM_CAPTURE         5
 198 #define ULI_NUM_PLAYBACK        6
 199
 200 /* ATI HDMI has 1 playback and 0 capture */
 201 #define ATIHDMI_NUM_CAPTURE     0
 202 #define ATIHDMI_NUM_PLAYBACK    1
 203
 204 /* TERA has 4 playback and 3 capture */
 205 #define TERA_NUM_CAPTURE        3
 206 #define TERA_NUM_PLAYBACK       4
 207
 208 /* this number is statically defined for simplicity */
 209 #define MAX_AZX_DEV             16
 210
 211 /* max number of fragments - we may use more if allocating more pages for BDL */
 212 #define BDL_SIZE                4096
 213 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 214 #define AZX_MAX_FRAG            32
 215 /* max buffer size - no h/w limit, you can increase as you like */
 216 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 217 /* max number of PCM devics per card */
 218 #define AZX_MAX_PCMS            8
 219
 220 /* RIRB int mask: overrun[2], response[0] */
 221 #define RIRB_INT_RESPONSE       0x01
 222 #define RIRB_INT_OVERRUN        0x04
 223 #define RIRB_INT_MASK           0x05
 224
 225 /* STATESTS int mask: SD2,SD1,SD0 */
 226 #define AZX_MAX_CODECS          3
 227 #define STATESTS_INT_MASK       0x07
 228
 229 /* SD_CTL bits */
 230 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 231 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 232 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 233 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 234 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 235 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 236 #define SD_CTL_STREAM_TAG_SHIFT 20
 237
 238 /* SD_CTL and SD_STS */
 239 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 240 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 241 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 242 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 243                                  SD_INT_COMPLETE)
 244
 245 /* SD_STS */
 246 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 247
 248 /* INTCTL and INTSTS */
 249 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 250 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 251 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 252
 253 /* GCTL unsolicited response enable bit */
 254 #define ICH6_GCTL_UREN          (1<<8)
 255
 256 /* GCTL reset bit */
 257 #define ICH6_GCTL_RESET         (1<<0)
 258
 259 /* CORB/RIRB control, read/write pointer */
 260 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 261 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 262 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 263 /* below are so far hardcoded - should read registers in future */
 264 #define ICH6_MAX_CORB_ENTRIES   256
 265 #define ICH6_MAX_RIRB_ENTRIES   256
 266
 267 /* position fix mode */
 268 enum {
 269         POS_FIX_AUTO,
 270         POS_FIX_LPIB,
 271         POS_FIX_POSBUF,
 272 };
 273
 274 /* Defines for ATI HD Audio support in SB450 south bridge */
 275 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 276 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 277
 278 /* Defines for Nvidia HDA support */
 279 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 280 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 281 #define NVIDIA_HDA_ISTRM_COH          0x4d
 282 #define NVIDIA_HDA_OSTRM_COH          0x4c
 283 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 284
 285 /* Defines for Intel SCH HDA snoop control */
 286 #define INTEL_SCH_HDA_DEVC      0x78
 287 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 288
 289 /* Define IN stream 0 FIFO size offset in VIA controller */
 290 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 291 /* Define VIA HD Audio Device ID*/
 292 #define VIA_HDAC_DEVICE_ID              0x3288
 293
 294
 295 /*
 296  */
 297
 298 struct azx_dev {
 299         struct snd_dma_buffer bdl; /* BDL buffer */
 300         u32 *posbuf;            /* position buffer pointer */
 301
 302         unsigned int bufsize;   /* size of the play buffer in bytes */
 303         unsigned int period_bytes; /* size of the period in bytes */
 304         unsigned int frags;     /* number for period in the play buffer */
 305         unsigned int fifo_size; /* FIFO size */
 306
 307         void __iomem *sd_addr;  /* stream descriptor pointer */
 308
 309         u32 sd_int_sta_mask;    /* stream int status mask */
 310
 311         /* pcm support */
 312         struct snd_pcm_substream *substream;    /* assigned substream,
 313                                                  * set in PCM open
 314                                                  */
 315         unsigned int format_val;        /* format value to be set in the
 316                                          * controller and the codec
 317                                          */
 318         unsigned char stream_tag;       /* assigned stream */
 319         unsigned char index;            /* stream index */
 320
 321         unsigned int opened :1;
 322         unsigned int running :1;
 323         unsigned int irq_pending :1;
 324         unsigned int irq_ignore :1;
 325         /*
 326          * For VIA:
 327          *  A flag to ensure DMA position is 0
 328          *  when link position is not greater than FIFO size
 329          */
 330         unsigned int insufficient :1;
 331 };
 332
 333 /* CORB/RIRB */
 334 struct azx_rb {
 335         u32 *buf;               /* CORB/RIRB buffer
 336                                  * Each CORB entry is 4byte, RIRB is 8byte
 337                                  */
 338         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 339         /* for RIRB */
 340         unsigned short rp, wp;  /* read/write pointers */
 341         int cmds;               /* number of pending requests */
 342         u32 res;                /* last read value */
 343 };
 344
 345 struct azx {
 346         struct snd_card *card;
 347         struct pci_dev *pci;
 348         int dev_index;
 349
 350         /* chip type specific */
 351         int driver_type;
 352         int playback_streams;
 353         int playback_index_offset;
 354         int capture_streams;
 355         int capture_index_offset;
 356         int num_streams;
 357
 358         /* pci resources */
 359         unsigned long addr;
 360         void __iomem *remap_addr;
 361         int irq;
 362
 363         /* locks */
 364         spinlock_t reg_lock;
 365         struct mutex open_mutex;
 366
 367         /* streams (x num_streams) */
 368         struct azx_dev *azx_dev;
 369
 370         /* PCM */
 371         struct snd_pcm *pcm[AZX_MAX_PCMS];
 372
 373         /* HD codec */
 374         unsigned short codec_mask;
 375         struct hda_bus *bus;
 376
 377         /* CORB/RIRB */
 378         struct azx_rb corb;
 379         struct azx_rb rirb;
 380
 381         /* CORB/RIRB and position buffers */
 382         struct snd_dma_buffer rb;
 383         struct snd_dma_buffer posbuf;
 384
 385         /* flags */
 386         int position_fix;
 387         unsigned int running :1;
 388         unsigned int initialized :1;
 389         unsigned int single_cmd :1;
 390         unsigned int polling_mode :1;
 391         unsigned int msi :1;
 392         unsigned int irq_pending_warned :1;
 393         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 394
 395         /* for debugging */
 396         unsigned int last_cmd;  /* last issued command (to sync) */
 397
 398         /* for pending irqs */
 399         struct work_struct irq_pending_work;
 400 };
 401
 402 /* driver types */
 403 enum {
 404         AZX_DRIVER_ICH,
 405         AZX_DRIVER_SCH,
 406         AZX_DRIVER_ATI,
 407         AZX_DRIVER_ATIHDMI,
 408         AZX_DRIVER_VIA,
 409         AZX_DRIVER_SIS,
 410         AZX_DRIVER_ULI,
 411         AZX_DRIVER_NVIDIA,
 412         AZX_DRIVER_TERA,
 413 };
 414
 415 static char *driver_short_names[] __devinitdata = {
 416         [AZX_DRIVER_ICH] = "HDA Intel",
 417         [AZX_DRIVER_SCH] = "HDA Intel MID",
 418         [AZX_DRIVER_ATI] = "HDA ATI SB",
 419         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 420         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 421         [AZX_DRIVER_SIS] = "HDA SIS966",
 422         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 423         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 424         [AZX_DRIVER_TERA] = "HDA Teradici",
 425 };
 426
 427 /*
 428  * macros for easy use
 429  */
 430 #define azx_writel(chip,reg,value) \
 431         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 432 #define azx_readl(chip,reg) \
 433         readl((chip)->remap_addr + ICH6_REG_##reg)
 434 #define azx_writew(chip,reg,value) \
 435         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 436 #define azx_readw(chip,reg) \
 437         readw((chip)->remap_addr + ICH6_REG_##reg)
 438 #define azx_writeb(chip,reg,value) \
 439         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 440 #define azx_readb(chip,reg) \
 441         readb((chip)->remap_addr + ICH6_REG_##reg)
 442
 443 #define azx_sd_writel(dev,reg,value) \
 444         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 445 #define azx_sd_readl(dev,reg) \
 446         readl((dev)->sd_addr + ICH6_REG_##reg)
 447 #define azx_sd_writew(dev,reg,value) \
 448         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 449 #define azx_sd_readw(dev,reg) \
 450         readw((dev)->sd_addr + ICH6_REG_##reg)
 451 #define azx_sd_writeb(dev,reg,value) \
 452         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 453 #define azx_sd_readb(dev,reg) \
 454         readb((dev)->sd_addr + ICH6_REG_##reg)
 455
 456 /* for pcm support */
 457 #define get_azx_dev(substream) (substream->runtime->private_data)
 458
 459 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 460
 461 /*
 462  * Interface for HD codec
 463  */
 464
 465 /*
 466  * CORB / RIRB interface
 467  */
 468 static int azx_alloc_cmd_io(struct azx *chip)
 469 {
 470         int err;
 471
 472         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 473         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 474                                   snd_dma_pci_data(chip->pci),
 475                                   PAGE_SIZE, &chip->rb);
 476         if (err < 0) {
 477                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 478                 return err;
 479         }
 480         return 0;
 481 }
 482
 483 static void azx_init_cmd_io(struct azx *chip)
 484 {
 485         /* CORB set up */
 486         chip->corb.addr = chip->rb.addr;
 487         chip->corb.buf = (u32 *)chip->rb.area;
 488         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 489         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 490
 491         /* set the corb size to 256 entries (ULI requires explicitly) */
 492         azx_writeb(chip, CORBSIZE, 0x02);
 493         /* set the corb write pointer to 0 */
 494         azx_writew(chip, CORBWP, 0);
 495         /* reset the corb hw read pointer */
 496         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 497         /* enable corb dma */
 498         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 499
 500         /* RIRB set up */
 501         chip->rirb.addr = chip->rb.addr + 2048;
 502         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 503         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 504         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 505
 506         /* set the rirb size to 256 entries (ULI requires explicitly) */
 507         azx_writeb(chip, RIRBSIZE, 0x02);
 508         /* reset the rirb hw write pointer */
 509         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 510         /* set N=1, get RIRB response interrupt for new entry */
 511         azx_writew(chip, RINTCNT, 1);
 512         /* enable rirb dma and response irq */
 513         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 514         chip->rirb.rp = chip->rirb.cmds = 0;
 515 }
 516
 517 static void azx_free_cmd_io(struct azx *chip)
 518 {
 519         /* disable ringbuffer DMAs */
 520         azx_writeb(chip, RIRBCTL, 0);
 521         azx_writeb(chip, CORBCTL, 0);
 522 }
 523
 524 /* send a command */
 525 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
 526 {
 527         struct azx *chip = codec->bus->private_data;
 528         unsigned int wp;
 529
 530         /* add command to corb */
 531         wp = azx_readb(chip, CORBWP);
 532         wp++;
 533         wp %= ICH6_MAX_CORB_ENTRIES;
 534
 535         spin_lock_irq(&chip->reg_lock);
 536         chip->rirb.cmds++;
 537         chip->corb.buf[wp] = cpu_to_le32(val);
 538         azx_writel(chip, CORBWP, wp);
 539         spin_unlock_irq(&chip->reg_lock);
 540
 541         return 0;
 542 }
 543
 544 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 545
 546 /* retrieve RIRB entry - called from interrupt handler */
 547 static void azx_update_rirb(struct azx *chip)
 548 {
 549         unsigned int rp, wp;
 550         u32 res, res_ex;
 551
 552         wp = azx_readb(chip, RIRBWP);
 553         if (wp == chip->rirb.wp)
 554                 return;
 555         chip->rirb.wp = wp;
 556
 557         while (chip->rirb.rp != wp) {
 558                 chip->rirb.rp++;
 559                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 560
 561                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 562                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 563                 res = le32_to_cpu(chip->rirb.buf[rp]);
 564                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 565                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 566                 else if (chip->rirb.cmds) {
 567                         chip->rirb.res = res;
 568                         smp_wmb();
 569                         chip->rirb.cmds--;
 570                 }
 571         }
 572 }
 573
 574 /* receive a response */
 575 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
 576 {
 577         struct azx *chip = codec->bus->private_data;
 578         unsigned long timeout;
 579
 580  again:
 581         timeout = jiffies + msecs_to_jiffies(1000);
 582         for (;;) {
 583                 if (chip->polling_mode) {
 584                         spin_lock_irq(&chip->reg_lock);
 585                         azx_update_rirb(chip);
 586                         spin_unlock_irq(&chip->reg_lock);
 587                 }
 588                 if (!chip->rirb.cmds) {
 589                         smp_rmb();
 590                         return chip->rirb.res; /* the last value */
 591                 }
 592                 if (time_after(jiffies, timeout))
 593                         break;
 594                 if (codec->bus->needs_damn_long_delay)
 595                         msleep(2); /* temporary workaround */
 596                 else {
 597                         udelay(10);
 598                         cond_resched();
 599                 }
 600         }
 601
 602         if (chip->msi) {
 603                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 604                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 605                 free_irq(chip->irq, chip);
 606                 chip->irq = -1;
 607                 pci_disable_msi(chip->pci);
 608                 chip->msi = 0;
 609                 if (azx_acquire_irq(chip, 1) < 0)
 610                         return -1;
 611                 goto again;
 612         }
 613
 614         if (!chip->polling_mode) {
 615                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 616                            "switching to polling mode: last cmd=0x%08x\n",
 617                            chip->last_cmd);
 618                 chip->polling_mode = 1;
 619                 goto again;
 620         }
 621
 622         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 623                    "switching to single_cmd mode: last cmd=0x%08x\n",
 624                    chip->last_cmd);
 625         chip->rirb.rp = azx_readb(chip, RIRBWP);
 626         chip->rirb.cmds = 0;
 627         /* switch to single_cmd mode */
 628         chip->single_cmd = 1;
 629         azx_free_cmd_io(chip);
 630         return -1;
 631 }
 632
 633 /*
 634  * Use the single immediate command instead of CORB/RIRB for simplicity
 635  *
 636  * Note: according to Intel, this is not preferred use.  The command was
 637  *       intended for the BIOS only, and may get confused with unsolicited
 638  *       responses.  So, we shouldn't use it for normal operation from the
 639  *       driver.
 640  *       I left the codes, however, for debugging/testing purposes.
 641  */
 642
 643 /* send a command */
 644 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
 645 {
 646         struct azx *chip = codec->bus->private_data;
 647         int timeout = 50;
 648
 649         while (timeout--) {
 650                 /* check ICB busy bit */
 651                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 652                         /* Clear IRV valid bit */
 653                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 654                                    ICH6_IRS_VALID);
 655                         azx_writel(chip, IC, val);
 656                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 657                                    ICH6_IRS_BUSY);
 658                         return 0;
 659                 }
 660                 udelay(1);
 661         }
 662         if (printk_ratelimit())
 663                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 664                            azx_readw(chip, IRS), val);
 665         return -EIO;
 666 }
 667
 668 /* receive a response */
 669 static unsigned int azx_single_get_response(struct hda_codec *codec)
 670 {
 671         struct azx *chip = codec->bus->private_data;
 672         int timeout = 50;
 673
 674         while (timeout--) {
 675                 /* check IRV busy bit */
 676                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 677                         return azx_readl(chip, IR);
 678                 udelay(1);
 679         }
 680         if (printk_ratelimit())
 681                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 682                            azx_readw(chip, IRS));
 683         return (unsigned int)-1;
 684 }
 685
 686 /*
 687  * The below are the main callbacks from hda_codec.
 688  *
 689  * They are just the skeleton to call sub-callbacks according to the
 690  * current setting of chip->single_cmd.
 691  */
 692
 693 /* send a command */
 694 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
 695                         int direct, unsigned int verb,
 696                         unsigned int para)
 697 {
 698         struct azx *chip = codec->bus->private_data;
 699         u32 val;
 700
 701         val = (u32)(codec->addr & 0x0f) << 28;
 702         val |= (u32)direct << 27;
 703         val |= (u32)nid << 20;
 704         val |= verb << 8;
 705         val |= para;
 706         chip->last_cmd = val;
 707
 708         if (chip->single_cmd)
 709                 return azx_single_send_cmd(codec, val);
 710         else
 711                 return azx_corb_send_cmd(codec, val);
 712 }
 713
 714 /* get a response */
 715 static unsigned int azx_get_response(struct hda_codec *codec)
 716 {
 717         struct azx *chip = codec->bus->private_data;
 718         if (chip->single_cmd)
 719                 return azx_single_get_response(codec);
 720         else
 721                 return azx_rirb_get_response(codec);
 722 }
 723
 724 #ifdef CONFIG_SND_HDA_POWER_SAVE
 725 static void azx_power_notify(struct hda_codec *codec);
 726 #endif
 727
 728 /* reset codec link */
 729 static int azx_reset(struct azx *chip)
 730 {
 731         int count;
 732
 733         /* clear STATESTS */
 734         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 735
 736         /* reset controller */
 737         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 738
 739         count = 50;
 740         while (azx_readb(chip, GCTL) && --count)
 741                 msleep(1);
 742
 743         /* delay for >= 100us for codec PLL to settle per spec
 744          * Rev 0.9 section 5.5.1
 745          */
 746         msleep(1);
 747
 748         /* Bring controller out of reset */
 749         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 750
 751         count = 50;
 752         while (!azx_readb(chip, GCTL) && --count)
 753                 msleep(1);
 754
 755         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 756         msleep(1);
 757
 758         /* check to see if controller is ready */
 759         if (!azx_readb(chip, GCTL)) {
 760                 snd_printd("azx_reset: controller not ready!\n");
 761                 return -EBUSY;
 762         }
 763
 764         /* Accept unsolicited responses */
 765         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 766
 767         /* detect codecs */
 768         if (!chip->codec_mask) {
 769                 chip->codec_mask = azx_readw(chip, STATESTS);
 770                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 771         }
 772
 773         return 0;
 774 }
 775
 776
 777 /*
 778  * Lowlevel interface
 779  */
 780
 781 /* enable interrupts */
 782 static void azx_int_enable(struct azx *chip)
 783 {
 784         /* enable controller CIE and GIE */
 785         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 786                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 787 }
 788
 789 /* disable interrupts */
 790 static void azx_int_disable(struct azx *chip)
 791 {
 792         int i;
 793
 794         /* disable interrupts in stream descriptor */
 795         for (i = 0; i < chip->num_streams; i++) {
 796                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 797                 azx_sd_writeb(azx_dev, SD_CTL,
 798                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 799         }
 800
 801         /* disable SIE for all streams */
 802         azx_writeb(chip, INTCTL, 0);
 803
 804         /* disable controller CIE and GIE */
 805         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 806                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 807 }
 808
 809 /* clear interrupts */
 810 static void azx_int_clear(struct azx *chip)
 811 {
 812         int i;
 813
 814         /* clear stream status */
 815         for (i = 0; i < chip->num_streams; i++) {
 816                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 817                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 818         }
 819
 820         /* clear STATESTS */
 821         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 822
 823         /* clear rirb status */
 824         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 825
 826         /* clear int status */
 827         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 828 }
 829
 830 /* start a stream */
 831 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 832 {
 833         /*
 834          * Before stream start, initialize parameter
 835          */
 836         azx_dev->insufficient = 1;
 837
 838         /* enable SIE */
 839         azx_writeb(chip, INTCTL,
 840                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 841         /* set DMA start and interrupt mask */
 842         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 843                       SD_CTL_DMA_START | SD_INT_MASK);
 844 }
 845
 846 /* stop a stream */
 847 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 848 {
 849         /* stop DMA */
 850         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 851                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 852         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 853         /* disable SIE */
 854         azx_writeb(chip, INTCTL,
 855                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 856 }
 857
 858
 859 /*
 860  * reset and start the controller registers
 861  */
 862 static void azx_init_chip(struct azx *chip)
 863 {
 864         if (chip->initialized)
 865                 return;
 866
 867         /* reset controller */
 868         azx_reset(chip);
 869
 870         /* initialize interrupts */
 871         azx_int_clear(chip);
 872         azx_int_enable(chip);
 873
 874         /* initialize the codec command I/O */
 875         if (!chip->single_cmd)
 876                 azx_init_cmd_io(chip);
 877
 878         /* program the position buffer */
 879         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 880         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 881
 882         chip->initialized = 1;
 883 }
 884
 885 /*
 886  * initialize the PCI registers
 887  */
 888 /* update bits in a PCI register byte */
 889 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 890                             unsigned char mask, unsigned char val)
 891 {
 892         unsigned char data;
 893
 894         pci_read_config_byte(pci, reg, &data);
 895         data &= ~mask;
 896         data |= (val & mask);
 897         pci_write_config_byte(pci, reg, data);
 898 }
 899
 900 static void azx_init_pci(struct azx *chip)
 901 {
 902         unsigned short snoop;
 903
 904         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 905          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 906          * Ensuring these bits are 0 clears playback static on some HD Audio
 907          * codecs
 908          */
 909         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 910
 911         switch (chip->driver_type) {
 912         case AZX_DRIVER_ATI:
 913                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 914                 update_pci_byte(chip->pci,
 915                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 916                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 917                 break;
 918         case AZX_DRIVER_NVIDIA:
 919                 /* For NVIDIA HDA, enable snoop */
 920                 update_pci_byte(chip->pci,
 921                                 NVIDIA_HDA_TRANSREG_ADDR,
 922                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 923                 update_pci_byte(chip->pci,
 924                                 NVIDIA_HDA_ISTRM_COH,
 925                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 926                 update_pci_byte(chip->pci,
 927                                 NVIDIA_HDA_OSTRM_COH,
 928                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 929                 break;
 930         case AZX_DRIVER_SCH:
 931                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 932                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 933                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 934                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 935                         pci_read_config_word(chip->pci,
 936                                 INTEL_SCH_HDA_DEVC, &snoop);
 937                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 938                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 939                                 ? "Failed" : "OK");
 940                 }
 941                 break;
 942
 943         }
 944 }
 945
 946
 947 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 948
 949 /*
 950  * interrupt handler
 951  */
 952 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 953 {
 954         struct azx *chip = dev_id;
 955         struct azx_dev *azx_dev;
 956         u32 status;
 957         int i;
 958
 959         spin_lock(&chip->reg_lock);
 960
 961         status = azx_readl(chip, INTSTS);
 962         if (status == 0) {
 963                 spin_unlock(&chip->reg_lock);
 964                 return IRQ_NONE;
 965         }
 966
 967         for (i = 0; i < chip->num_streams; i++) {
 968                 azx_dev = &chip->azx_dev[i];
 969                 if (status & azx_dev->sd_int_sta_mask) {
 970                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 971                         if (!azx_dev->substream || !azx_dev->running)
 972                                 continue;
 973                         /* ignore the first dummy IRQ (due to pos_adj) */
 974                         if (azx_dev->irq_ignore) {
 975                                 azx_dev->irq_ignore = 0;
 976                                 continue;
 977                         }
 978                         /* check whether this IRQ is really acceptable */
 979                         if (azx_position_ok(chip, azx_dev)) {
 980                                 azx_dev->irq_pending = 0;
 981                                 spin_unlock(&chip->reg_lock);
 982                                 snd_pcm_period_elapsed(azx_dev->substream);
 983                                 spin_lock(&chip->reg_lock);
 984                         } else {
 985                                 /* bogus IRQ, process it later */
 986                                 azx_dev->irq_pending = 1;
 987                                 schedule_work(&chip->irq_pending_work);
 988                         }
 989                 }
 990         }
 991
 992         /* clear rirb int */
 993         status = azx_readb(chip, RIRBSTS);
 994         if (status & RIRB_INT_MASK) {
 995                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
 996                         azx_update_rirb(chip);
 997                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 998         }
 999
1000 #if 0
1001         /* clear state status int */
1002         if (azx_readb(chip, STATESTS) & 0x04)
1003                 azx_writeb(chip, STATESTS, 0x04);
1004 #endif
1005         spin_unlock(&chip->reg_lock);
1006
1007         return IRQ_HANDLED;
1008 }
1009
1010
1011 /*
1012  * set up a BDL entry
1013  */
1014 static int setup_bdle(struct snd_pcm_substream *substream,
1015                       struct azx_dev *azx_dev, u32 **bdlp,
1016                       int ofs, int size, int with_ioc)
1017 {
1018         u32 *bdl = *bdlp;
1019
1020         while (size > 0) {
1021                 dma_addr_t addr;
1022                 int chunk;
1023
1024                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1025                         return -EINVAL;
1026
1027                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1028                 /* program the address field of the BDL entry */
1029                 bdl[0] = cpu_to_le32((u32)addr);
1030                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1031                 /* program the size field of the BDL entry */
1032                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1033                 bdl[2] = cpu_to_le32(chunk);
1034                 /* program the IOC to enable interrupt
1035                  * only when the whole fragment is processed
1036                  */
1037                 size -= chunk;
1038                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1039                 bdl += 4;
1040                 azx_dev->frags++;
1041                 ofs += chunk;
1042         }
1043         *bdlp = bdl;
1044         return ofs;
1045 }
1046
1047 /*
1048  * set up BDL entries
1049  */
1050 static int azx_setup_periods(struct azx *chip,
1051                              struct snd_pcm_substream *substream,
1052                              struct azx_dev *azx_dev)
1053 {
1054         u32 *bdl;
1055         int i, ofs, periods, period_bytes;
1056         int pos_adj;
1057
1058         /* reset BDL address */
1059         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1060         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1061
1062         period_bytes = snd_pcm_lib_period_bytes(substream);
1063         azx_dev->period_bytes = period_bytes;
1064         periods = azx_dev->bufsize / period_bytes;
1065
1066         /* program the initial BDL entries */
1067         bdl = (u32 *)azx_dev->bdl.area;
1068         ofs = 0;
1069         azx_dev->frags = 0;
1070         azx_dev->irq_ignore = 0;
1071         pos_adj = bdl_pos_adj[chip->dev_index];
1072         if (pos_adj > 0) {
1073                 struct snd_pcm_runtime *runtime = substream->runtime;
1074                 int pos_align = pos_adj;
1075                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1076                 if (!pos_adj)
1077                         pos_adj = pos_align;
1078                 else
1079                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1080                                 pos_align;
1081                 pos_adj = frames_to_bytes(runtime, pos_adj);
1082                 if (pos_adj >= period_bytes) {
1083                         snd_printk(KERN_WARNING "Too big adjustment %d\n",
1084                                    bdl_pos_adj[chip->dev_index]);
1085                         pos_adj = 0;
1086                 } else {
1087                         ofs = setup_bdle(substream, azx_dev,
1088                                          &bdl, ofs, pos_adj, 1);
1089                         if (ofs < 0)
1090                                 goto error;
1091                         azx_dev->irq_ignore = 1;
1092                 }
1093         } else
1094                 pos_adj = 0;
1095         for (i = 0; i < periods; i++) {
1096                 if (i == periods - 1 && pos_adj)
1097                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1098                                          period_bytes - pos_adj, 0);
1099                 else
1100                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1101                                          period_bytes, 1);
1102                 if (ofs < 0)
1103                         goto error;
1104         }
1105         return 0;
1106
1107  error:
1108         snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1109                    azx_dev->bufsize, period_bytes);
1110         /* reset */
1111         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1112         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1113         return -EINVAL;
1114 }
1115
1116 /*
1117  * set up the SD for streaming
1118  */
1119 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1120 {
1121         unsigned char val;
1122         int timeout;
1123
1124         /* make sure the run bit is zero for SD */
1125         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1126                       ~SD_CTL_DMA_START);
1127         /* reset stream */
1128         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1129                       SD_CTL_STREAM_RESET);
1130         udelay(3);
1131         timeout = 300;
1132         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1133                --timeout)
1134                 ;
1135         val &= ~SD_CTL_STREAM_RESET;
1136         azx_sd_writeb(azx_dev, SD_CTL, val);
1137         udelay(3);
1138
1139         timeout = 300;
1140         /* waiting for hardware to report that the stream is out of reset */
1141         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1142                --timeout)
1143                 ;
1144
1145         /* program the stream_tag */
1146         azx_sd_writel(azx_dev, SD_CTL,
1147                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1148                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1149
1150         /* program the length of samples in cyclic buffer */
1151         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1152
1153         /* program the stream format */
1154         /* this value needs to be the same as the one programmed */
1155         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1156
1157         /* program the stream LVI (last valid index) of the BDL */
1158         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1159
1160         /* program the BDL address */
1161         /* lower BDL address */
1162         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1163         /* upper BDL address */
1164         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1165
1166         /* enable the position buffer */
1167         if (chip->position_fix == POS_FIX_POSBUF ||
1168             chip->position_fix == POS_FIX_AUTO ||
1169             chip->via_dmapos_patch) {
1170                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1171                         azx_writel(chip, DPLBASE,
1172                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1173         }
1174
1175         /* set the interrupt enable bits in the descriptor control register */
1176         azx_sd_writel(azx_dev, SD_CTL,
1177                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1178
1179         return 0;
1180 }
1181
1182
1183 /*
1184  * Codec initialization
1185  */
1186
1187 static unsigned int azx_max_codecs[] __devinitdata = {
1188         [AZX_DRIVER_ICH] = 4,           /* Some ICH9 boards use SD3 */
1189         [AZX_DRIVER_SCH] = 3,
1190         [AZX_DRIVER_ATI] = 4,
1191         [AZX_DRIVER_ATIHDMI] = 4,
1192         [AZX_DRIVER_VIA] = 3,           /* FIXME: correct? */
1193         [AZX_DRIVER_SIS] = 3,           /* FIXME: correct? */
1194         [AZX_DRIVER_ULI] = 3,           /* FIXME: correct? */
1195         [AZX_DRIVER_NVIDIA] = 3,        /* FIXME: correct? */
1196         [AZX_DRIVER_TERA] = 1,
1197 };
1198
1199 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1200                                       unsigned int codec_probe_mask)
1201 {
1202         struct hda_bus_template bus_temp;
1203         int c, codecs, audio_codecs, err;
1204
1205         memset(&bus_temp, 0, sizeof(bus_temp));
1206         bus_temp.private_data = chip;
1207         bus_temp.modelname = model;
1208         bus_temp.pci = chip->pci;
1209         bus_temp.ops.command = azx_send_cmd;
1210         bus_temp.ops.get_response = azx_get_response;
1211 #ifdef CONFIG_SND_HDA_POWER_SAVE
1212         bus_temp.ops.pm_notify = azx_power_notify;
1213 #endif
1214
1215         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1216         if (err < 0)
1217                 return err;
1218
1219         codecs = audio_codecs = 0;
1220         for (c = 0; c < AZX_MAX_CODECS; c++) {
1221                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1222                         struct hda_codec *codec;
1223                         err = snd_hda_codec_new(chip->bus, c, &codec);
1224                         if (err < 0)
1225                                 continue;
1226                         codecs++;
1227                         if (codec->afg)
1228                                 audio_codecs++;
1229                 }
1230         }
1231         if (!audio_codecs) {
1232                 /* probe additional slots if no codec is found */
1233                 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1234                         if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1235                                 err = snd_hda_codec_new(chip->bus, c, NULL);
1236                                 if (err < 0)
1237                                         continue;
1238                                 codecs++;
1239                         }
1240                 }
1241         }
1242         if (!codecs) {
1243                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1244                 return -ENXIO;
1245         }
1246
1247         return 0;
1248 }
1249
1250
1251 /*
1252  * PCM support
1253  */
1254
1255 /* assign a stream for the PCM */
1256 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1257 {
1258         int dev, i, nums;
1259         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1260                 dev = chip->playback_index_offset;
1261                 nums = chip->playback_streams;
1262         } else {
1263                 dev = chip->capture_index_offset;
1264                 nums = chip->capture_streams;
1265         }
1266         for (i = 0; i < nums; i++, dev++)
1267                 if (!chip->azx_dev[dev].opened) {
1268                         chip->azx_dev[dev].opened = 1;
1269                         return &chip->azx_dev[dev];
1270                 }
1271         return NULL;
1272 }
1273
1274 /* release the assigned stream */
1275 static inline void azx_release_device(struct azx_dev *azx_dev)
1276 {
1277         azx_dev->opened = 0;
1278 }
1279
1280 static struct snd_pcm_hardware azx_pcm_hw = {
1281         .info =                 (SNDRV_PCM_INFO_MMAP |
1282                                  SNDRV_PCM_INFO_INTERLEAVED |
1283                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1284                                  SNDRV_PCM_INFO_MMAP_VALID |
1285                                  /* No full-resume yet implemented */
1286                                  /* SNDRV_PCM_INFO_RESUME |*/
1287                                  SNDRV_PCM_INFO_PAUSE |
1288                                  SNDRV_PCM_INFO_SYNC_START),
1289         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1290         .rates =                SNDRV_PCM_RATE_48000,
1291         .rate_min =             48000,
1292         .rate_max =             48000,
1293         .channels_min =         2,
1294         .channels_max =         2,
1295         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1296         .period_bytes_min =     128,
1297         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1298         .periods_min =          2,
1299         .periods_max =          AZX_MAX_FRAG,
1300         .fifo_size =            0,
1301 };
1302
1303 struct azx_pcm {
1304         struct azx *chip;
1305         struct hda_codec *codec;
1306         struct hda_pcm_stream *hinfo[2];
1307 };
1308
1309 static int azx_pcm_open(struct snd_pcm_substream *substream)
1310 {
1311         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1312         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1313         struct azx *chip = apcm->chip;
1314         struct azx_dev *azx_dev;
1315         struct snd_pcm_runtime *runtime = substream->runtime;
1316         unsigned long flags;
1317         int err;
1318
1319         mutex_lock(&chip->open_mutex);
1320         azx_dev = azx_assign_device(chip, substream->stream);
1321         if (azx_dev == NULL) {
1322                 mutex_unlock(&chip->open_mutex);
1323                 return -EBUSY;
1324         }
1325         runtime->hw = azx_pcm_hw;
1326         runtime->hw.channels_min = hinfo->channels_min;
1327         runtime->hw.channels_max = hinfo->channels_max;
1328         runtime->hw.formats = hinfo->formats;
1329         runtime->hw.rates = hinfo->rates;
1330         snd_pcm_limit_hw_rates(runtime);
1331         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1332         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1333                                    128);
1334         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1335                                    128);
1336         snd_hda_power_up(apcm->codec);
1337         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1338         if (err < 0) {
1339                 azx_release_device(azx_dev);
1340                 snd_hda_power_down(apcm->codec);
1341                 mutex_unlock(&chip->open_mutex);
1342                 return err;
1343         }
1344         spin_lock_irqsave(&chip->reg_lock, flags);
1345         azx_dev->substream = substream;
1346         azx_dev->running = 0;
1347         spin_unlock_irqrestore(&chip->reg_lock, flags);
1348
1349         runtime->private_data = azx_dev;
1350         snd_pcm_set_sync(substream);
1351         mutex_unlock(&chip->open_mutex);
1352         return 0;
1353 }
1354
1355 static int azx_pcm_close(struct snd_pcm_substream *substream)
1356 {
1357         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1358         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1359         struct azx *chip = apcm->chip;
1360         struct azx_dev *azx_dev = get_azx_dev(substream);
1361         unsigned long flags;
1362
1363         mutex_lock(&chip->open_mutex);
1364         spin_lock_irqsave(&chip->reg_lock, flags);
1365         azx_dev->substream = NULL;
1366         azx_dev->running = 0;
1367         spin_unlock_irqrestore(&chip->reg_lock, flags);
1368         azx_release_device(azx_dev);
1369         hinfo->ops.close(hinfo, apcm->codec, substream);
1370         snd_hda_power_down(apcm->codec);
1371         mutex_unlock(&chip->open_mutex);
1372         return 0;
1373 }
1374
1375 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1376                              struct snd_pcm_hw_params *hw_params)
1377 {
1378         return snd_pcm_lib_malloc_pages(substream,
1379                                         params_buffer_bytes(hw_params));
1380 }
1381
1382 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1383 {
1384         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1385         struct azx_dev *azx_dev = get_azx_dev(substream);
1386         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1387
1388         /* reset BDL address */
1389         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1390         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1391         azx_sd_writel(azx_dev, SD_CTL, 0);
1392
1393         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1394
1395         return snd_pcm_lib_free_pages(substream);
1396 }
1397
1398 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1399 {
1400         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1401         struct azx *chip = apcm->chip;
1402         struct azx_dev *azx_dev = get_azx_dev(substream);
1403         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1404         struct snd_pcm_runtime *runtime = substream->runtime;
1405
1406         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1407         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1408                                                          runtime->channels,
1409                                                          runtime->format,
1410                                                          hinfo->maxbps);
1411         if (!azx_dev->format_val) {
1412                 snd_printk(KERN_ERR SFX
1413                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1414                            runtime->rate, runtime->channels, runtime->format);
1415                 return -EINVAL;
1416         }
1417
1418         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1419                     azx_dev->bufsize, azx_dev->format_val);
1420         if (azx_setup_periods(chip, substream, azx_dev) < 0)
1421                 return -EINVAL;
1422         azx_setup_controller(chip, azx_dev);
1423         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1424                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1425         else
1426                 azx_dev->fifo_size = 0;
1427
1428         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1429                                   azx_dev->format_val, substream);
1430 }
1431
1432 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1433 {
1434         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1435         struct azx *chip = apcm->chip;
1436         struct azx_dev *azx_dev;
1437         struct snd_pcm_substream *s;
1438         int start, nsync = 0, sbits = 0;
1439         int nwait, timeout;
1440
1441         switch (cmd) {
1442         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1443         case SNDRV_PCM_TRIGGER_RESUME:
1444         case SNDRV_PCM_TRIGGER_START:
1445                 start = 1;
1446                 break;
1447         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1448         case SNDRV_PCM_TRIGGER_SUSPEND:
1449         case SNDRV_PCM_TRIGGER_STOP:
1450                 start = 0;
1451                 break;
1452         default:
1453                 return -EINVAL;
1454         }
1455
1456         snd_pcm_group_for_each_entry(s, substream) {
1457                 if (s->pcm->card != substream->pcm->card)
1458                         continue;
1459                 azx_dev = get_azx_dev(s);
1460                 sbits |= 1 << azx_dev->index;
1461                 nsync++;
1462                 snd_pcm_trigger_done(s, substream);
1463         }
1464
1465         spin_lock(&chip->reg_lock);
1466         if (nsync > 1) {
1467                 /* first, set SYNC bits of corresponding streams */
1468                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1469         }
1470         snd_pcm_group_for_each_entry(s, substream) {
1471                 if (s->pcm->card != substream->pcm->card)
1472                         continue;
1473                 azx_dev = get_azx_dev(s);
1474                 if (start)
1475                         azx_stream_start(chip, azx_dev);
1476                 else
1477                         azx_stream_stop(chip, azx_dev);
1478                 azx_dev->running = start;
1479         }
1480         spin_unlock(&chip->reg_lock);
1481         if (start) {
1482                 if (nsync == 1)
1483                         return 0;
1484                 /* wait until all FIFOs get ready */
1485                 for (timeout = 5000; timeout; timeout--) {
1486                         nwait = 0;
1487                         snd_pcm_group_for_each_entry(s, substream) {
1488                                 if (s->pcm->card != substream->pcm->card)
1489                                         continue;
1490                                 azx_dev = get_azx_dev(s);
1491                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1492                                       SD_STS_FIFO_READY))
1493                                         nwait++;
1494                         }
1495                         if (!nwait)
1496                                 break;
1497                         cpu_relax();
1498                 }
1499         } else {
1500                 /* wait until all RUN bits are cleared */
1501                 for (timeout = 5000; timeout; timeout--) {
1502                         nwait = 0;
1503                         snd_pcm_group_for_each_entry(s, substream) {
1504                                 if (s->pcm->card != substream->pcm->card)
1505                                         continue;
1506                                 azx_dev = get_azx_dev(s);
1507                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1508                                     SD_CTL_DMA_START)
1509                                         nwait++;
1510                         }
1511                         if (!nwait)
1512                                 break;
1513                         cpu_relax();
1514                 }
1515         }
1516         if (nsync > 1) {
1517                 spin_lock(&chip->reg_lock);
1518                 /* reset SYNC bits */
1519                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1520                 spin_unlock(&chip->reg_lock);
1521         }
1522         return 0;
1523 }
1524
1525 /* get the current DMA position with correction on VIA chips */
1526 static unsigned int azx_via_get_position(struct azx *chip,
1527                                          struct azx_dev *azx_dev)
1528 {
1529         unsigned int link_pos, mini_pos, bound_pos;
1530         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1531         unsigned int fifo_size;
1532
1533         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1534         if (azx_dev->index >= 4) {
1535                 /* Playback, no problem using link position */
1536                 return link_pos;
1537         }
1538
1539         /* Capture */
1540         /* For new chipset,
1541          * use mod to get the DMA position just like old chipset
1542          */
1543         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1544         mod_dma_pos %= azx_dev->period_bytes;
1545
1546         /* azx_dev->fifo_size can't get FIFO size of in stream.
1547          * Get from base address + offset.
1548          */
1549         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1550
1551         if (azx_dev->insufficient) {
1552                 /* Link position never gather than FIFO size */
1553                 if (link_pos <= fifo_size)
1554                         return 0;
1555
1556                 azx_dev->insufficient = 0;
1557         }
1558
1559         if (link_pos <= fifo_size)
1560                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1561         else
1562                 mini_pos = link_pos - fifo_size;
1563
1564         /* Find nearest previous boudary */
1565         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1566         mod_link_pos = link_pos % azx_dev->period_bytes;
1567         if (mod_link_pos >= fifo_size)
1568                 bound_pos = link_pos - mod_link_pos;
1569         else if (mod_dma_pos >= mod_mini_pos)
1570                 bound_pos = mini_pos - mod_mini_pos;
1571         else {
1572                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1573                 if (bound_pos >= azx_dev->bufsize)
1574                         bound_pos = 0;
1575         }
1576
1577         /* Calculate real DMA position we want */
1578         return bound_pos + mod_dma_pos;
1579 }
1580
1581 static unsigned int azx_get_position(struct azx *chip,
1582                                      struct azx_dev *azx_dev)
1583 {
1584         unsigned int pos;
1585
1586         if (chip->via_dmapos_patch)
1587                 pos = azx_via_get_position(chip, azx_dev);
1588         else if (chip->position_fix == POS_FIX_POSBUF ||
1589                  chip->position_fix == POS_FIX_AUTO) {
1590                 /* use the position buffer */
1591                 pos = le32_to_cpu(*azx_dev->posbuf);
1592         } else {
1593                 /* read LPIB */
1594                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1595         }
1596         if (pos >= azx_dev->bufsize)
1597                 pos = 0;
1598         return pos;
1599 }
1600
1601 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1602 {
1603         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1604         struct azx *chip = apcm->chip;
1605         struct azx_dev *azx_dev = get_azx_dev(substream);
1606         return bytes_to_frames(substream->runtime,
1607                                azx_get_position(chip, azx_dev));
1608 }
1609
1610 /*
1611  * Check whether the current DMA position is acceptable for updating
1612  * periods.  Returns non-zero if it's OK.
1613  *
1614  * Many HD-audio controllers appear pretty inaccurate about
1615  * the update-IRQ timing.  The IRQ is issued before actually the
1616  * data is processed.  So, we need to process it afterwords in a
1617  * workqueue.
1618  */
1619 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1620 {
1621         unsigned int pos;
1622
1623         pos = azx_get_position(chip, azx_dev);
1624         if (chip->position_fix == POS_FIX_AUTO) {
1625                 if (!pos) {
1626                         printk(KERN_WARNING
1627                                "hda-intel: Invalid position buffer, "
1628                                "using LPIB read method instead.\n");
1629                         chip->position_fix = POS_FIX_LPIB;
1630                         pos = azx_get_position(chip, azx_dev);
1631                 } else
1632                         chip->position_fix = POS_FIX_POSBUF;
1633         }
1634
1635         if (!bdl_pos_adj[chip->dev_index])
1636                 return 1; /* no delayed ack */
1637         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1638                 return 0; /* NG - it's below the period boundary */
1639         return 1; /* OK, it's fine */
1640 }
1641
1642 /*
1643  * The work for pending PCM period updates.
1644  */
1645 static void azx_irq_pending_work(struct work_struct *work)
1646 {
1647         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1648         int i, pending;
1649
1650         if (!chip->irq_pending_warned) {
1651                 printk(KERN_WARNING
1652                        "hda-intel: IRQ timing workaround is activated "
1653                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1654                        chip->card->number);
1655                 chip->irq_pending_warned = 1;
1656         }
1657
1658         for (;;) {
1659                 pending = 0;
1660                 spin_lock_irq(&chip->reg_lock);
1661                 for (i = 0; i < chip->num_streams; i++) {
1662                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1663                         if (!azx_dev->irq_pending ||
1664                             !azx_dev->substream ||
1665                             !azx_dev->running)
1666                                 continue;
1667                         if (azx_position_ok(chip, azx_dev)) {
1668                                 azx_dev->irq_pending = 0;
1669                                 spin_unlock(&chip->reg_lock);
1670                                 snd_pcm_period_elapsed(azx_dev->substream);
1671                                 spin_lock(&chip->reg_lock);
1672                         } else
1673                                 pending++;
1674                 }
1675                 spin_unlock_irq(&chip->reg_lock);
1676                 if (!pending)
1677                         return;
1678                 cond_resched();
1679         }
1680 }
1681
1682 /* clear irq_pending flags and assure no on-going workq */
1683 static void azx_clear_irq_pending(struct azx *chip)
1684 {
1685         int i;
1686
1687         spin_lock_irq(&chip->reg_lock);
1688         for (i = 0; i < chip->num_streams; i++)
1689                 chip->azx_dev[i].irq_pending = 0;
1690         spin_unlock_irq(&chip->reg_lock);
1691         flush_scheduled_work();
1692 }
1693
1694 static struct snd_pcm_ops azx_pcm_ops = {
1695         .open = azx_pcm_open,
1696         .close = azx_pcm_close,
1697         .ioctl = snd_pcm_lib_ioctl,
1698         .hw_params = azx_pcm_hw_params,
1699         .hw_free = azx_pcm_hw_free,
1700         .prepare = azx_pcm_prepare,
1701         .trigger = azx_pcm_trigger,
1702         .pointer = azx_pcm_pointer,
1703         .page = snd_pcm_sgbuf_ops_page,
1704 };
1705
1706 static void azx_pcm_free(struct snd_pcm *pcm)
1707 {
1708         kfree(pcm->private_data);
1709 }
1710
1711 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1712                                       struct hda_pcm *cpcm)
1713 {
1714         int err;
1715         struct snd_pcm *pcm;
1716         struct azx_pcm *apcm;
1717
1718         /* if no substreams are defined for both playback and capture,
1719          * it's just a placeholder.  ignore it.
1720          */
1721         if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1722                 return 0;
1723
1724         if (snd_BUG_ON(!cpcm->name))
1725                 return -EINVAL;
1726
1727         err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1728                           cpcm->stream[0].substreams,
1729                           cpcm->stream[1].substreams,
1730                           &pcm);
1731         if (err < 0)
1732                 return err;
1733         strcpy(pcm->name, cpcm->name);
1734         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1735         if (apcm == NULL)
1736                 return -ENOMEM;
1737         apcm->chip = chip;
1738         apcm->codec = codec;
1739         apcm->hinfo[0] = &cpcm->stream[0];
1740         apcm->hinfo[1] = &cpcm->stream[1];
1741         pcm->private_data = apcm;
1742         pcm->private_free = azx_pcm_free;
1743         if (cpcm->stream[0].substreams)
1744                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1745         if (cpcm->stream[1].substreams)
1746                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1747         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1748                                               snd_dma_pci_data(chip->pci),
1749                                               1024 * 64, 32 * 1024 * 1024);
1750         chip->pcm[cpcm->device] = pcm;
1751         return 0;
1752 }
1753
1754 static int __devinit azx_pcm_create(struct azx *chip)
1755 {
1756         static const char *dev_name[HDA_PCM_NTYPES] = {
1757                 "Audio", "SPDIF", "HDMI", "Modem"
1758         };
1759         /* starting device index for each PCM type */
1760         static int dev_idx[HDA_PCM_NTYPES] = {
1761                 [HDA_PCM_TYPE_AUDIO] = 0,
1762                 [HDA_PCM_TYPE_SPDIF] = 1,
1763                 [HDA_PCM_TYPE_HDMI] = 3,
1764                 [HDA_PCM_TYPE_MODEM] = 6
1765         };
1766         /* normal audio device indices; not linear to keep compatibility */
1767         static int audio_idx[4] = { 0, 2, 4, 5 };
1768         struct hda_codec *codec;
1769         int c, err;
1770         int num_devs[HDA_PCM_NTYPES];
1771
1772         err = snd_hda_build_pcms(chip->bus);
1773         if (err < 0)
1774                 return err;
1775
1776         /* create audio PCMs */
1777         memset(num_devs, 0, sizeof(num_devs));
1778         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1779                 for (c = 0; c < codec->num_pcms; c++) {
1780                         struct hda_pcm *cpcm = &codec->pcm_info[c];
1781                         int type = cpcm->pcm_type;
1782                         switch (type) {
1783                         case HDA_PCM_TYPE_AUDIO:
1784                                 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1785                                         snd_printk(KERN_WARNING
1786                                                    "Too many audio devices\n");
1787                                         continue;
1788                                 }
1789                                 cpcm->device = audio_idx[num_devs[type]];
1790                                 break;
1791                         case HDA_PCM_TYPE_SPDIF:
1792                         case HDA_PCM_TYPE_HDMI:
1793                         case HDA_PCM_TYPE_MODEM:
1794                                 if (num_devs[type]) {
1795                                         snd_printk(KERN_WARNING
1796                                                    "%s already defined\n",
1797                                                    dev_name[type]);
1798                                         continue;
1799                                 }
1800                                 cpcm->device = dev_idx[type];
1801                                 break;
1802                         default:
1803                                 snd_printk(KERN_WARNING
1804                                            "Invalid PCM type %d\n", type);
1805                                 continue;
1806                         }
1807                         num_devs[type]++;
1808                         err = create_codec_pcm(chip, codec, cpcm);
1809                         if (err < 0)
1810                                 return err;
1811                 }
1812         }
1813         return 0;
1814 }
1815
1816 /*
1817  * mixer creation - all stuff is implemented in hda module
1818  */
1819 static int __devinit azx_mixer_create(struct azx *chip)
1820 {
1821         return snd_hda_build_controls(chip->bus);
1822 }
1823
1824
1825 /*
1826  * initialize SD streams
1827  */
1828 static int __devinit azx_init_stream(struct azx *chip)
1829 {
1830         int i;
1831
1832         /* initialize each stream (aka device)
1833          * assign the starting bdl address to each stream (device)
1834          * and initialize
1835          */
1836         for (i = 0; i < chip->num_streams; i++) {
1837                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1838                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1839                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1840                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1841                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1842                 azx_dev->sd_int_sta_mask = 1 << i;
1843                 /* stream tag: must be non-zero and unique */
1844                 azx_dev->index = i;
1845                 azx_dev->stream_tag = i + 1;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1852 {
1853         if (request_irq(chip->pci->irq, azx_interrupt,
1854                         chip->msi ? 0 : IRQF_SHARED,
1855                         "HDA Intel", chip)) {
1856                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1857                        "disabling device\n", chip->pci->irq);
1858                 if (do_disconnect)
1859                         snd_card_disconnect(chip->card);
1860                 return -1;
1861         }
1862         chip->irq = chip->pci->irq;
1863         pci_intx(chip->pci, !chip->msi);
1864         return 0;
1865 }
1866
1867
1868 static void azx_stop_chip(struct azx *chip)
1869 {
1870         if (!chip->initialized)
1871                 return;
1872
1873         /* disable interrupts */
1874         azx_int_disable(chip);
1875         azx_int_clear(chip);
1876
1877         /* disable CORB/RIRB */
1878         azx_free_cmd_io(chip);
1879
1880         /* disable position buffer */
1881         azx_writel(chip, DPLBASE, 0);
1882         azx_writel(chip, DPUBASE, 0);
1883
1884         chip->initialized = 0;
1885 }
1886
1887 #ifdef CONFIG_SND_HDA_POWER_SAVE
1888 /* power-up/down the controller */
1889 static void azx_power_notify(struct hda_codec *codec)
1890 {
1891         struct azx *chip = codec->bus->private_data;
1892         struct hda_codec *c;
1893         int power_on = 0;
1894
1895         list_for_each_entry(c, &codec->bus->codec_list, list) {
1896                 if (c->power_on) {
1897                         power_on = 1;
1898                         break;
1899                 }
1900         }
1901         if (power_on)
1902                 azx_init_chip(chip);
1903         else if (chip->running && power_save_controller)
1904                 azx_stop_chip(chip);
1905 }
1906 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1907
1908 #ifdef CONFIG_PM
1909 /*
1910  * power management
1911  */
1912 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1913 {
1914         struct snd_card *card = pci_get_drvdata(pci);
1915         struct azx *chip = card->private_data;
1916         int i;
1917
1918         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1919         azx_clear_irq_pending(chip);
1920         for (i = 0; i < AZX_MAX_PCMS; i++)
1921                 snd_pcm_suspend_all(chip->pcm[i]);
1922         if (chip->initialized)
1923                 snd_hda_suspend(chip->bus, state);
1924         azx_stop_chip(chip);
1925         if (chip->irq >= 0) {
1926                 free_irq(chip->irq, chip);
1927                 chip->irq = -1;
1928         }
1929         if (chip->msi)
1930                 pci_disable_msi(chip->pci);
1931         pci_disable_device(pci);
1932         pci_save_state(pci);
1933         pci_set_power_state(pci, pci_choose_state(pci, state));
1934         return 0;
1935 }
1936
1937 static int azx_resume(struct pci_dev *pci)
1938 {
1939         struct snd_card *card = pci_get_drvdata(pci);
1940         struct azx *chip = card->private_data;
1941
1942         pci_set_power_state(pci, PCI_D0);
1943         pci_restore_state(pci);
1944         if (pci_enable_device(pci) < 0) {
1945                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1946                        "disabling device\n");
1947                 snd_card_disconnect(card);
1948                 return -EIO;
1949         }
1950         pci_set_master(pci);
1951         if (chip->msi)
1952                 if (pci_enable_msi(pci) < 0)
1953                         chip->msi = 0;
1954         if (azx_acquire_irq(chip, 1) < 0)
1955                 return -EIO;
1956         azx_init_pci(chip);
1957
1958         if (snd_hda_codecs_inuse(chip->bus))
1959                 azx_init_chip(chip);
1960
1961         snd_hda_resume(chip->bus);
1962         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1963         return 0;
1964 }
1965 #endif /* CONFIG_PM */
1966
1967
1968 /*
1969  * destructor
1970  */
1971 static int azx_free(struct azx *chip)
1972 {
1973         int i;
1974
1975         if (chip->initialized) {
1976                 azx_clear_irq_pending(chip);
1977                 for (i = 0; i < chip->num_streams; i++)
1978                         azx_stream_stop(chip, &chip->azx_dev[i]);
1979                 azx_stop_chip(chip);
1980         }
1981
1982         if (chip->irq >= 0)
1983                 free_irq(chip->irq, (void*)chip);
1984         if (chip->msi)
1985                 pci_disable_msi(chip->pci);
1986         if (chip->remap_addr)
1987                 iounmap(chip->remap_addr);
1988
1989         if (chip->azx_dev) {
1990                 for (i = 0; i < chip->num_streams; i++)
1991                         if (chip->azx_dev[i].bdl.area)
1992                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1993         }
1994         if (chip->rb.area)
1995                 snd_dma_free_pages(&chip->rb);
1996         if (chip->posbuf.area)
1997                 snd_dma_free_pages(&chip->posbuf);
1998         pci_release_regions(chip->pci);
1999         pci_disable_device(chip->pci);
2000         kfree(chip->azx_dev);
2001         kfree(chip);
2002
2003         return 0;
2004 }
2005
2006 static int azx_dev_free(struct snd_device *device)
2007 {
2008         return azx_free(device->device_data);
2009 }
2010
2011 /*
2012  * white/black-listing for position_fix
2013  */
2014 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2015         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2016         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2017         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2018         {}
2019 };
2020
2021 static int __devinit check_position_fix(struct azx *chip, int fix)
2022 {
2023         const struct snd_pci_quirk *q;
2024
2025         /* Check VIA HD Audio Controller exist */
2026         if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
2027             chip->pci->device == VIA_HDAC_DEVICE_ID) {
2028                 chip->via_dmapos_patch = 1;
2029                 /* Use link position directly, avoid any transfer problem. */
2030                 return POS_FIX_LPIB;
2031         }
2032         chip->via_dmapos_patch = 0;
2033
2034         if (fix == POS_FIX_AUTO) {
2035                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2036                 if (q) {
2037                         printk(KERN_INFO
2038                                     "hda_intel: position_fix set to %d "
2039                                     "for device %04x:%04x\n",
2040                                     q->value, q->subvendor, q->subdevice);
2041                         return q->value;
2042                 }
2043         }
2044         return fix;
2045 }
2046
2047 /*
2048  * black-lists for probe_mask
2049  */
2050 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2051         /* Thinkpad often breaks the controller communication when accessing
2052          * to the non-working (or non-existing) modem codec slot.
2053          */
2054         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2055         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2056         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2057         {}
2058 };
2059
2060 static void __devinit check_probe_mask(struct azx *chip, int dev)
2061 {
2062         const struct snd_pci_quirk *q;
2063
2064         if (probe_mask[dev] == -1) {
2065                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2066                 if (q) {
2067                         printk(KERN_INFO
2068                                "hda_intel: probe_mask set to 0x%x "
2069                                "for device %04x:%04x\n",
2070                                q->value, q->subvendor, q->subdevice);
2071                         probe_mask[dev] = q->value;
2072                 }
2073         }
2074 }
2075
2076
2077 /*
2078  * constructor
2079  */
2080 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2081                                 int dev, int driver_type,
2082                                 struct azx **rchip)
2083 {
2084         struct azx *chip;
2085         int i, err;
2086         unsigned short gcap;
2087         static struct snd_device_ops ops = {
2088                 .dev_free = azx_dev_free,
2089         };
2090
2091         *rchip = NULL;
2092
2093         err = pci_enable_device(pci);
2094         if (err < 0)
2095                 return err;
2096
2097         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2098         if (!chip) {
2099                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2100                 pci_disable_device(pci);
2101                 return -ENOMEM;
2102         }
2103
2104         spin_lock_init(&chip->reg_lock);
2105         mutex_init(&chip->open_mutex);
2106         chip->card = card;
2107         chip->pci = pci;
2108         chip->irq = -1;
2109         chip->driver_type = driver_type;
2110         chip->msi = enable_msi;
2111         chip->dev_index = dev;
2112         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2113
2114         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2115         check_probe_mask(chip, dev);
2116
2117         chip->single_cmd = single_cmd;
2118
2119         if (bdl_pos_adj[dev] < 0) {
2120                 switch (chip->driver_type) {
2121                 case AZX_DRIVER_ICH:
2122                         bdl_pos_adj[dev] = 1;
2123                         break;
2124                 default:
2125                         bdl_pos_adj[dev] = 32;
2126                         break;
2127                 }
2128         }
2129
2130 #if BITS_PER_LONG != 64
2131         /* Fix up base address on ULI M5461 */
2132         if (chip->driver_type == AZX_DRIVER_ULI) {
2133                 u16 tmp3;
2134                 pci_read_config_word(pci, 0x40, &tmp3);
2135                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2136                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2137         }
2138 #endif
2139
2140         err = pci_request_regions(pci, "ICH HD audio");
2141         if (err < 0) {
2142                 kfree(chip);
2143                 pci_disable_device(pci);
2144                 return err;
2145         }
2146
2147         chip->addr = pci_resource_start(pci, 0);
2148         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2149         if (chip->remap_addr == NULL) {
2150                 snd_printk(KERN_ERR SFX "ioremap error\n");
2151                 err = -ENXIO;
2152                 goto errout;
2153         }
2154
2155         if (chip->msi)
2156                 if (pci_enable_msi(pci) < 0)
2157                         chip->msi = 0;
2158
2159         if (azx_acquire_irq(chip, 0) < 0) {
2160                 err = -EBUSY;
2161                 goto errout;
2162         }
2163
2164         pci_set_master(pci);
2165         synchronize_irq(chip->irq);
2166
2167         gcap = azx_readw(chip, GCAP);
2168         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2169
2170         /* allow 64bit DMA address if supported by H/W */
2171         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2172                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2173
2174         /* read number of streams from GCAP register instead of using
2175          * hardcoded value
2176          */
2177         chip->capture_streams = (gcap >> 8) & 0x0f;
2178         chip->playback_streams = (gcap >> 12) & 0x0f;
2179         if (!chip->playback_streams && !chip->capture_streams) {
2180                 /* gcap didn't give any info, switching to old method */
2181
2182                 switch (chip->driver_type) {
2183                 case AZX_DRIVER_ULI:
2184                         chip->playback_streams = ULI_NUM_PLAYBACK;
2185                         chip->capture_streams = ULI_NUM_CAPTURE;
2186                         break;
2187                 case AZX_DRIVER_ATIHDMI:
2188                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2189                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2190                         break;
2191                 default:
2192                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2193                         chip->capture_streams = ICH6_NUM_CAPTURE;
2194                         break;
2195                 }
2196         }
2197         chip->capture_index_offset = 0;
2198         chip->playback_index_offset = chip->capture_streams;
2199         chip->num_streams = chip->playback_streams + chip->capture_streams;
2200         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2201                                 GFP_KERNEL);
2202         if (!chip->azx_dev) {
2203                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2204                 goto errout;
2205         }
2206
2207         for (i = 0; i < chip->num_streams; i++) {
2208                 /* allocate memory for the BDL for each stream */
2209                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2210                                           snd_dma_pci_data(chip->pci),
2211                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2212                 if (err < 0) {
2213                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2214                         goto errout;
2215                 }
2216         }
2217         /* allocate memory for the position buffer */
2218         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2219                                   snd_dma_pci_data(chip->pci),
2220                                   chip->num_streams * 8, &chip->posbuf);
2221         if (err < 0) {
2222                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2223                 goto errout;
2224         }
2225         /* allocate CORB/RIRB */
2226         if (!chip->single_cmd) {
2227                 err = azx_alloc_cmd_io(chip);
2228                 if (err < 0)
2229                         goto errout;
2230         }
2231
2232         /* initialize streams */
2233         azx_init_stream(chip);
2234
2235         /* initialize chip */
2236         azx_init_pci(chip);
2237         azx_init_chip(chip);
2238
2239         /* codec detection */
2240         if (!chip->codec_mask) {
2241                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2242                 err = -ENODEV;
2243                 goto errout;
2244         }
2245
2246         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2247         if (err <0) {
2248                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2249                 goto errout;
2250         }
2251
2252         strcpy(card->driver, "HDA-Intel");
2253         strcpy(card->shortname, driver_short_names[chip->driver_type]);
2254         sprintf(card->longname, "%s at 0x%lx irq %i",
2255                 card->shortname, chip->addr, chip->irq);
2256
2257         *rchip = chip;
2258         return 0;
2259
2260  errout:
2261         azx_free(chip);
2262         return err;
2263 }
2264
2265 static void power_down_all_codecs(struct azx *chip)
2266 {
2267 #ifdef CONFIG_SND_HDA_POWER_SAVE
2268         /* The codecs were powered up in snd_hda_codec_new().
2269          * Now all initialization done, so turn them down if possible
2270          */
2271         struct hda_codec *codec;
2272         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2273                 snd_hda_power_down(codec);
2274         }
2275 #endif
2276 }
2277
2278 static int __devinit azx_probe(struct pci_dev *pci,
2279                                const struct pci_device_id *pci_id)
2280 {
2281         static int dev;
2282         struct snd_card *card;
2283         struct azx *chip;
2284         int err;
2285
2286         if (dev >= SNDRV_CARDS)
2287                 return -ENODEV;
2288         if (!enable[dev]) {
2289                 dev++;
2290                 return -ENOENT;
2291         }
2292
2293         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2294         if (!card) {
2295                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2296                 return -ENOMEM;
2297         }
2298
2299         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2300         if (err < 0) {
2301                 snd_card_free(card);
2302                 return err;
2303         }
2304         card->private_data = chip;
2305
2306         /* create codec instances */
2307         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2308         if (err < 0) {
2309                 snd_card_free(card);
2310                 return err;
2311         }
2312
2313         /* create PCM streams */
2314         err = azx_pcm_create(chip);
2315         if (err < 0) {
2316                 snd_card_free(card);
2317                 return err;
2318         }
2319
2320         /* create mixer controls */
2321         err = azx_mixer_create(chip);
2322         if (err < 0) {
2323                 snd_card_free(card);
2324                 return err;
2325         }
2326
2327         snd_card_set_dev(card, &pci->dev);
2328
2329         err = snd_card_register(card);
2330         if (err < 0) {
2331                 snd_card_free(card);
2332                 return err;
2333         }
2334
2335         pci_set_drvdata(pci, card);
2336         chip->running = 1;
2337         power_down_all_codecs(chip);
2338
2339         dev++;
2340         return err;
2341 }
2342
2343 static void __devexit azx_remove(struct pci_dev *pci)
2344 {
2345         snd_card_free(pci_get_drvdata(pci));
2346         pci_set_drvdata(pci, NULL);
2347 }
2348
2349 /* PCI IDs */
2350 static struct pci_device_id azx_ids[] = {
2351         /* ICH 6..10 */
2352         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2353         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2354         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2355         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2356         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2357         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2358         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2359         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2360         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2361         /* PCH */
2362         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2363         /* SCH */
2364         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2365         /* ATI SB 450/600 */
2366         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2367         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2368         /* ATI HDMI */
2369         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2370         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2371         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2372         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2373         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2374         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2375         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2376         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2377         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2378         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2379         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2380         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2381         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2382         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2383         /* VIA VT8251/VT8237A */
2384         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2385         /* SIS966 */
2386         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2387         /* ULI M5461 */
2388         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2389         /* NVIDIA MCP */
2390         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2391         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2392         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2393         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2394         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2395         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2396         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2397         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2398         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2399         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2400         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2401         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2402         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2403         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2404         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2405         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2406         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2407         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2408         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2409         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2410         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2411         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2412         /* Teradici */
2413         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2414         { 0, }
2415 };
2416 MODULE_DEVICE_TABLE(pci, azx_ids);
2417
2418 /* pci_driver definition */
2419 static struct pci_driver driver = {
2420         .name = "HDA Intel",
2421         .id_table = azx_ids,
2422         .probe = azx_probe,
2423         .remove = __devexit_p(azx_remove),
2424 #ifdef CONFIG_PM
2425         .suspend = azx_suspend,
2426         .resume = azx_resume,
2427 #endif
2428 };
2429
2430 static int __init alsa_card_azx_init(void)
2431 {
2432         return pci_register_driver(&driver);
2433 }
2434
2435 static void __exit alsa_card_azx_exit(void)
2436 {
2437         pci_unregister_driver(&driver);
2438 }
2439
2440 module_init(alsa_card_azx_init)
2441 module_exit(alsa_card_azx_exit)