2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
6 * - sometimes record brokes playback with WSS portion of
8 * - CS4231 (GUS MAX) - still trouble with occasional noises
9 * - broken initialization?
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/delay.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/slab.h>
32 #include <linux/ioport.h>
33 #include <sound/core.h>
34 #include <sound/wss.h>
35 #include <sound/pcm_params.h>
36 #include <sound/tlv.h>
42 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
43 MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
44 MODULE_LICENSE("GPL");
47 #define SNDRV_DEBUG_MCE
54 static unsigned char freq_bits[14] = {
55 /* 5510 */ 0x00 | CS4231_XTAL2,
56 /* 6620 */ 0x0E | CS4231_XTAL2,
57 /* 8000 */ 0x00 | CS4231_XTAL1,
58 /* 9600 */ 0x0E | CS4231_XTAL1,
59 /* 11025 */ 0x02 | CS4231_XTAL2,
60 /* 16000 */ 0x02 | CS4231_XTAL1,
61 /* 18900 */ 0x04 | CS4231_XTAL2,
62 /* 22050 */ 0x06 | CS4231_XTAL2,
63 /* 27042 */ 0x04 | CS4231_XTAL1,
64 /* 32000 */ 0x06 | CS4231_XTAL1,
65 /* 33075 */ 0x0C | CS4231_XTAL2,
66 /* 37800 */ 0x08 | CS4231_XTAL2,
67 /* 44100 */ 0x0A | CS4231_XTAL2,
68 /* 48000 */ 0x0C | CS4231_XTAL1
71 static unsigned int rates[14] = {
72 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
73 27042, 32000, 33075, 37800, 44100, 48000
76 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
77 .count = ARRAY_SIZE(rates),
82 static int snd_wss_xrate(struct snd_pcm_runtime *runtime)
84 return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
85 &hw_constraints_rates);
88 static unsigned char snd_wss_original_image[32] =
90 0x00, /* 00/00 - lic */
91 0x00, /* 01/01 - ric */
92 0x9f, /* 02/02 - la1ic */
93 0x9f, /* 03/03 - ra1ic */
94 0x9f, /* 04/04 - la2ic */
95 0x9f, /* 05/05 - ra2ic */
96 0xbf, /* 06/06 - loc */
97 0xbf, /* 07/07 - roc */
98 0x20, /* 08/08 - pdfr */
99 CS4231_AUTOCALIB, /* 09/09 - ic */
100 0x00, /* 0a/10 - pc */
101 0x00, /* 0b/11 - ti */
102 CS4231_MODE2, /* 0c/12 - mi */
103 0xfc, /* 0d/13 - lbc */
104 0x00, /* 0e/14 - pbru */
105 0x00, /* 0f/15 - pbrl */
106 0x80, /* 10/16 - afei */
107 0x01, /* 11/17 - afeii */
108 0x9f, /* 12/18 - llic */
109 0x9f, /* 13/19 - rlic */
110 0x00, /* 14/20 - tlb */
111 0x00, /* 15/21 - thb */
112 0x00, /* 16/22 - la3mic/reserved */
113 0x00, /* 17/23 - ra3mic/reserved */
114 0x00, /* 18/24 - afs */
115 0x00, /* 19/25 - lamoc/version */
116 0xcf, /* 1a/26 - mioc */
117 0x00, /* 1b/27 - ramoc/reserved */
118 0x20, /* 1c/28 - cdfr */
119 0x00, /* 1d/29 - res4 */
120 0x00, /* 1e/30 - cbru */
121 0x00, /* 1f/31 - cbrl */
124 static unsigned char snd_opti93x_original_image[32] =
126 0x00, /* 00/00 - l_mixout_outctrl */
127 0x00, /* 01/01 - r_mixout_outctrl */
128 0x88, /* 02/02 - l_cd_inctrl */
129 0x88, /* 03/03 - r_cd_inctrl */
130 0x88, /* 04/04 - l_a1/fm_inctrl */
131 0x88, /* 05/05 - r_a1/fm_inctrl */
132 0x80, /* 06/06 - l_dac_inctrl */
133 0x80, /* 07/07 - r_dac_inctrl */
134 0x00, /* 08/08 - ply_dataform_reg */
135 0x00, /* 09/09 - if_conf */
136 0x00, /* 0a/10 - pin_ctrl */
137 0x00, /* 0b/11 - err_init_reg */
138 0x0a, /* 0c/12 - id_reg */
139 0x00, /* 0d/13 - reserved */
140 0x00, /* 0e/14 - ply_upcount_reg */
141 0x00, /* 0f/15 - ply_lowcount_reg */
142 0x88, /* 10/16 - reserved/l_a1_inctrl */
143 0x88, /* 11/17 - reserved/r_a1_inctrl */
144 0x88, /* 12/18 - l_line_inctrl */
145 0x88, /* 13/19 - r_line_inctrl */
146 0x88, /* 14/20 - l_mic_inctrl */
147 0x88, /* 15/21 - r_mic_inctrl */
148 0x80, /* 16/22 - l_out_outctrl */
149 0x80, /* 17/23 - r_out_outctrl */
150 0x00, /* 18/24 - reserved */
151 0x00, /* 19/25 - reserved */
152 0x00, /* 1a/26 - reserved */
153 0x00, /* 1b/27 - reserved */
154 0x00, /* 1c/28 - cap_dataform_reg */
155 0x00, /* 1d/29 - reserved */
156 0x00, /* 1e/30 - cap_upcount_reg */
157 0x00 /* 1f/31 - cap_lowcount_reg */
161 * Basic I/O functions
164 static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)
166 outb(val, chip->port + offset);
169 static inline u8 wss_inb(struct snd_wss *chip, u8 offset)
171 return inb(chip->port + offset);
174 static void snd_wss_wait(struct snd_wss *chip)
179 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
184 static void snd_wss_outm(struct snd_wss *chip, unsigned char reg,
185 unsigned char mask, unsigned char value)
187 unsigned char tmp = (chip->image[reg] & mask) | value;
190 #ifdef CONFIG_SND_DEBUG
191 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
192 snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
194 chip->image[reg] = tmp;
195 if (!chip->calibrate_mute) {
196 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
198 wss_outb(chip, CS4231P(REG), tmp);
203 static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,
209 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
212 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
213 wss_outb(chip, CS4231P(REG), value);
217 void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)
220 #ifdef CONFIG_SND_DEBUG
221 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
222 snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
224 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
225 wss_outb(chip, CS4231P(REG), value);
226 chip->image[reg] = value;
228 snd_printdd("codec out - reg 0x%x = 0x%x\n",
229 chip->mce_bit | reg, value);
231 EXPORT_SYMBOL(snd_wss_out);
233 unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)
236 #ifdef CONFIG_SND_DEBUG
237 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
238 snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
240 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
242 return wss_inb(chip, CS4231P(REG));
244 EXPORT_SYMBOL(snd_wss_in);
246 void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,
249 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
250 wss_outb(chip, CS4231P(REG),
251 reg | (chip->image[CS4236_EXT_REG] & 0x01));
252 wss_outb(chip, CS4231P(REG), val);
253 chip->eimage[CS4236_REG(reg)] = val;
255 printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
258 EXPORT_SYMBOL(snd_cs4236_ext_out);
260 unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)
262 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
263 wss_outb(chip, CS4231P(REG),
264 reg | (chip->image[CS4236_EXT_REG] & 0x01));
266 return wss_inb(chip, CS4231P(REG));
270 res = wss_inb(chip, CS4231P(REG));
271 printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
276 EXPORT_SYMBOL(snd_cs4236_ext_in);
280 static void snd_wss_debug(struct snd_wss *chip)
283 "CS4231 REGS: INDEX = 0x%02x "
284 " STATUS = 0x%02x\n",
285 wss_inb(chip, CS4231P(REGSEL),
286 wss_inb(chip, CS4231P(STATUS)));
288 " 0x00: left input = 0x%02x "
289 " 0x10: alt 1 (CFIG 2) = 0x%02x\n",
290 snd_wss_in(chip, 0x00),
291 snd_wss_in(chip, 0x10));
293 " 0x01: right input = 0x%02x "
294 " 0x11: alt 2 (CFIG 3) = 0x%02x\n",
295 snd_wss_in(chip, 0x01),
296 snd_wss_in(chip, 0x11));
298 " 0x02: GF1 left input = 0x%02x "
299 " 0x12: left line in = 0x%02x\n",
300 snd_wss_in(chip, 0x02),
301 snd_wss_in(chip, 0x12));
303 " 0x03: GF1 right input = 0x%02x "
304 " 0x13: right line in = 0x%02x\n",
305 snd_wss_in(chip, 0x03),
306 snd_wss_in(chip, 0x13));
308 " 0x04: CD left input = 0x%02x "
309 " 0x14: timer low = 0x%02x\n",
310 snd_wss_in(chip, 0x04),
311 snd_wss_in(chip, 0x14));
313 " 0x05: CD right input = 0x%02x "
314 " 0x15: timer high = 0x%02x\n",
315 snd_wss_in(chip, 0x05),
316 snd_wss_in(chip, 0x15));
318 " 0x06: left output = 0x%02x "
319 " 0x16: left MIC (PnP) = 0x%02x\n",
320 snd_wss_in(chip, 0x06),
321 snd_wss_in(chip, 0x16));
323 " 0x07: right output = 0x%02x "
324 " 0x17: right MIC (PnP) = 0x%02x\n",
325 snd_wss_in(chip, 0x07),
326 snd_wss_in(chip, 0x17));
328 " 0x08: playback format = 0x%02x "
329 " 0x18: IRQ status = 0x%02x\n",
330 snd_wss_in(chip, 0x08),
331 snd_wss_in(chip, 0x18));
333 " 0x09: iface (CFIG 1) = 0x%02x "
334 " 0x19: left line out = 0x%02x\n",
335 snd_wss_in(chip, 0x09),
336 snd_wss_in(chip, 0x19));
338 " 0x0a: pin control = 0x%02x "
339 " 0x1a: mono control = 0x%02x\n",
340 snd_wss_in(chip, 0x0a),
341 snd_wss_in(chip, 0x1a));
343 " 0x0b: init & status = 0x%02x "
344 " 0x1b: right line out = 0x%02x\n",
345 snd_wss_in(chip, 0x0b),
346 snd_wss_in(chip, 0x1b));
348 " 0x0c: revision & mode = 0x%02x "
349 " 0x1c: record format = 0x%02x\n",
350 snd_wss_in(chip, 0x0c),
351 snd_wss_in(chip, 0x1c));
353 " 0x0d: loopback = 0x%02x "
354 " 0x1d: var freq (PnP) = 0x%02x\n",
355 snd_wss_in(chip, 0x0d),
356 snd_wss_in(chip, 0x1d));
358 " 0x0e: ply upr count = 0x%02x "
359 " 0x1e: ply lwr count = 0x%02x\n",
360 snd_wss_in(chip, 0x0e),
361 snd_wss_in(chip, 0x1e));
363 " 0x0f: rec upr count = 0x%02x "
364 " 0x1f: rec lwr count = 0x%02x\n",
365 snd_wss_in(chip, 0x0f),
366 snd_wss_in(chip, 0x1f));
372 * CS4231 detection / MCE routines
375 static void snd_wss_busy_wait(struct snd_wss *chip)
379 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
380 for (timeout = 5; timeout > 0; timeout--)
381 wss_inb(chip, CS4231P(REGSEL));
382 /* end of cleanup sequence */
383 for (timeout = 25000;
384 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
389 void snd_wss_mce_up(struct snd_wss *chip)
395 #ifdef CONFIG_SND_DEBUG
396 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
397 snd_printk("mce_up - auto calibration time out (0)\n");
399 spin_lock_irqsave(&chip->reg_lock, flags);
400 chip->mce_bit |= CS4231_MCE;
401 timeout = wss_inb(chip, CS4231P(REGSEL));
403 snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
404 if (!(timeout & CS4231_MCE))
405 wss_outb(chip, CS4231P(REGSEL),
406 chip->mce_bit | (timeout & 0x1f));
407 spin_unlock_irqrestore(&chip->reg_lock, flags);
409 EXPORT_SYMBOL(snd_wss_mce_up);
411 void snd_wss_mce_down(struct snd_wss *chip)
414 unsigned long end_time;
416 int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;
418 snd_wss_busy_wait(chip);
420 #ifdef CONFIG_SND_DEBUG
421 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
422 snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
424 spin_lock_irqsave(&chip->reg_lock, flags);
425 chip->mce_bit &= ~CS4231_MCE;
426 timeout = wss_inb(chip, CS4231P(REGSEL));
427 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
428 spin_unlock_irqrestore(&chip->reg_lock, flags);
430 snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
431 if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))
435 * Wait for (possible -- during init auto-calibration may not be set)
436 * calibration process to start. Needs upto 5 sample periods on AD1848
437 * which at the slowest possible rate of 5.5125 kHz means 907 us.
441 snd_printdd("(1) jiffies = %lu\n", jiffies);
443 /* check condition up to 250 ms */
444 end_time = jiffies + msecs_to_jiffies(250);
445 while (snd_wss_in(chip, CS4231_TEST_INIT) &
446 CS4231_CALIB_IN_PROGRESS) {
448 if (time_after(jiffies, end_time)) {
449 snd_printk(KERN_ERR "mce_down - "
450 "auto calibration time out (2)\n");
456 snd_printdd("(2) jiffies = %lu\n", jiffies);
458 /* check condition up to 100 ms */
459 end_time = jiffies + msecs_to_jiffies(100);
460 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
461 if (time_after(jiffies, end_time)) {
462 snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
468 snd_printdd("(3) jiffies = %lu\n", jiffies);
469 snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));
471 EXPORT_SYMBOL(snd_wss_mce_down);
473 static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)
475 switch (format & 0xe0) {
476 case CS4231_LINEAR_16:
477 case CS4231_LINEAR_16_BIG:
480 case CS4231_ADPCM_16:
483 if (format & CS4231_STEREO)
488 static int snd_wss_trigger(struct snd_pcm_substream *substream,
491 struct snd_wss *chip = snd_pcm_substream_chip(substream);
494 struct snd_pcm_substream *s;
498 case SNDRV_PCM_TRIGGER_START:
499 case SNDRV_PCM_TRIGGER_RESUME:
501 case SNDRV_PCM_TRIGGER_STOP:
502 case SNDRV_PCM_TRIGGER_SUSPEND:
509 snd_pcm_group_for_each_entry(s, substream) {
510 if (s == chip->playback_substream) {
511 what |= CS4231_PLAYBACK_ENABLE;
512 snd_pcm_trigger_done(s, substream);
513 } else if (s == chip->capture_substream) {
514 what |= CS4231_RECORD_ENABLE;
515 snd_pcm_trigger_done(s, substream);
518 spin_lock(&chip->reg_lock);
520 chip->image[CS4231_IFACE_CTRL] |= what;
522 chip->trigger(chip, what, 1);
524 chip->image[CS4231_IFACE_CTRL] &= ~what;
526 chip->trigger(chip, what, 0);
528 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
529 spin_unlock(&chip->reg_lock);
540 static unsigned char snd_wss_get_rate(unsigned int rate)
544 for (i = 0; i < ARRAY_SIZE(rates); i++)
545 if (rate == rates[i])
548 return freq_bits[ARRAY_SIZE(rates) - 1];
551 static unsigned char snd_wss_get_format(struct snd_wss *chip,
555 unsigned char rformat;
557 rformat = CS4231_LINEAR_8;
559 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
560 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
561 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
562 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
563 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
566 rformat |= CS4231_STEREO;
568 snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
573 static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)
578 spin_lock_irqsave(&chip->reg_lock, flags);
579 if (chip->calibrate_mute == mute) {
580 spin_unlock_irqrestore(&chip->reg_lock, flags);
584 snd_wss_dout(chip, CS4231_LEFT_INPUT,
585 chip->image[CS4231_LEFT_INPUT]);
586 snd_wss_dout(chip, CS4231_RIGHT_INPUT,
587 chip->image[CS4231_RIGHT_INPUT]);
588 snd_wss_dout(chip, CS4231_LOOPBACK,
589 chip->image[CS4231_LOOPBACK]);
591 snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,
592 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
593 snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,
594 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
595 snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,
596 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
597 snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,
598 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
599 snd_wss_dout(chip, CS4231_LEFT_OUTPUT,
600 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
601 snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,
602 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
603 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
604 snd_wss_dout(chip, CS4231_LEFT_LINE_IN,
605 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
606 snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,
607 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
608 snd_wss_dout(chip, CS4231_MONO_CTRL,
609 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
611 if (chip->hardware == WSS_HW_INTERWAVE) {
612 snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,
613 mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]);
614 snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,
615 mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]);
616 snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,
617 mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]);
618 snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,
619 mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]);
621 chip->calibrate_mute = mute;
622 spin_unlock_irqrestore(&chip->reg_lock, flags);
625 static void snd_wss_playback_format(struct snd_wss *chip,
626 struct snd_pcm_hw_params *params,
632 mutex_lock(&chip->mce_mutex);
633 snd_wss_calibrate_mute(chip, 1);
634 if (chip->hardware == WSS_HW_CS4231A ||
635 (chip->hardware & WSS_HW_CS4232_MASK)) {
636 spin_lock_irqsave(&chip->reg_lock, flags);
637 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
638 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
639 chip->image[CS4231_ALT_FEATURE_1] | 0x10);
640 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
641 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
642 chip->image[CS4231_PLAYBK_FORMAT]);
643 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
644 chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
645 udelay(100); /* Fixes audible clicks at least on GUS MAX */
648 spin_unlock_irqrestore(&chip->reg_lock, flags);
651 snd_wss_mce_up(chip);
652 spin_lock_irqsave(&chip->reg_lock, flags);
653 if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {
654 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)
655 pdfr = (pdfr & 0xf0) |
656 (chip->image[CS4231_REC_FORMAT] & 0x0f);
658 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
660 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);
661 spin_unlock_irqrestore(&chip->reg_lock, flags);
662 if (chip->hardware == WSS_HW_OPL3SA2)
663 udelay(100); /* this seems to help */
664 snd_wss_mce_down(chip);
666 snd_wss_calibrate_mute(chip, 0);
667 mutex_unlock(&chip->mce_mutex);
670 static void snd_wss_capture_format(struct snd_wss *chip,
671 struct snd_pcm_hw_params *params,
677 mutex_lock(&chip->mce_mutex);
678 snd_wss_calibrate_mute(chip, 1);
679 if (chip->hardware == WSS_HW_CS4231A ||
680 (chip->hardware & WSS_HW_CS4232_MASK)) {
681 spin_lock_irqsave(&chip->reg_lock, flags);
682 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
683 (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
684 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
685 chip->image[CS4231_ALT_FEATURE_1] | 0x20);
686 snd_wss_out(chip, CS4231_REC_FORMAT,
687 chip->image[CS4231_REC_FORMAT] = cdfr);
688 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
689 chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
692 spin_unlock_irqrestore(&chip->reg_lock, flags);
695 snd_wss_mce_up(chip);
696 spin_lock_irqsave(&chip->reg_lock, flags);
697 if (chip->hardware != WSS_HW_INTERWAVE &&
698 !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
699 if (chip->single_dma)
700 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
702 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
703 (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |
705 spin_unlock_irqrestore(&chip->reg_lock, flags);
706 snd_wss_mce_down(chip);
707 snd_wss_mce_up(chip);
708 spin_lock_irqsave(&chip->reg_lock, flags);
710 if (chip->hardware & WSS_HW_AD1848_MASK)
711 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
713 snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);
714 spin_unlock_irqrestore(&chip->reg_lock, flags);
715 snd_wss_mce_down(chip);
717 snd_wss_calibrate_mute(chip, 0);
718 mutex_unlock(&chip->mce_mutex);
725 static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)
727 struct snd_wss *chip = snd_timer_chip(timer);
728 if (chip->hardware & WSS_HW_CS4236B_MASK)
731 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
734 static int snd_wss_timer_start(struct snd_timer *timer)
738 struct snd_wss *chip = snd_timer_chip(timer);
739 spin_lock_irqsave(&chip->reg_lock, flags);
740 ticks = timer->sticks;
741 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
742 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
743 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
744 chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);
745 snd_wss_out(chip, CS4231_TIMER_HIGH,
746 chip->image[CS4231_TIMER_HIGH]);
747 chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;
748 snd_wss_out(chip, CS4231_TIMER_LOW,
749 chip->image[CS4231_TIMER_LOW]);
750 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
751 chip->image[CS4231_ALT_FEATURE_1] |
752 CS4231_TIMER_ENABLE);
754 spin_unlock_irqrestore(&chip->reg_lock, flags);
758 static int snd_wss_timer_stop(struct snd_timer *timer)
761 struct snd_wss *chip = snd_timer_chip(timer);
762 spin_lock_irqsave(&chip->reg_lock, flags);
763 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
764 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
765 chip->image[CS4231_ALT_FEATURE_1]);
766 spin_unlock_irqrestore(&chip->reg_lock, flags);
770 static void snd_wss_init(struct snd_wss *chip)
774 snd_wss_mce_down(chip);
776 #ifdef SNDRV_DEBUG_MCE
777 snd_printk("init: (1)\n");
779 snd_wss_mce_up(chip);
780 spin_lock_irqsave(&chip->reg_lock, flags);
781 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
782 CS4231_PLAYBACK_PIO |
783 CS4231_RECORD_ENABLE |
786 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
787 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
788 spin_unlock_irqrestore(&chip->reg_lock, flags);
789 snd_wss_mce_down(chip);
791 #ifdef SNDRV_DEBUG_MCE
792 snd_printk("init: (2)\n");
795 snd_wss_mce_up(chip);
796 spin_lock_irqsave(&chip->reg_lock, flags);
798 CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
799 spin_unlock_irqrestore(&chip->reg_lock, flags);
800 snd_wss_mce_down(chip);
802 #ifdef SNDRV_DEBUG_MCE
803 snd_printk("init: (3) - afei = 0x%x\n",
804 chip->image[CS4231_ALT_FEATURE_1]);
807 spin_lock_irqsave(&chip->reg_lock, flags);
808 snd_wss_out(chip, CS4231_ALT_FEATURE_2,
809 chip->image[CS4231_ALT_FEATURE_2]);
810 spin_unlock_irqrestore(&chip->reg_lock, flags);
812 snd_wss_mce_up(chip);
813 spin_lock_irqsave(&chip->reg_lock, flags);
814 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
815 chip->image[CS4231_PLAYBK_FORMAT]);
816 spin_unlock_irqrestore(&chip->reg_lock, flags);
817 snd_wss_mce_down(chip);
819 #ifdef SNDRV_DEBUG_MCE
820 snd_printk("init: (4)\n");
823 snd_wss_mce_up(chip);
824 spin_lock_irqsave(&chip->reg_lock, flags);
825 if (!(chip->hardware & WSS_HW_AD1848_MASK))
826 snd_wss_out(chip, CS4231_REC_FORMAT,
827 chip->image[CS4231_REC_FORMAT]);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
829 snd_wss_mce_down(chip);
831 #ifdef SNDRV_DEBUG_MCE
832 snd_printk("init: (5)\n");
836 static int snd_wss_open(struct snd_wss *chip, unsigned int mode)
840 mutex_lock(&chip->open_mutex);
841 if ((chip->mode & mode) ||
842 ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {
843 mutex_unlock(&chip->open_mutex);
846 if (chip->mode & WSS_MODE_OPEN) {
848 mutex_unlock(&chip->open_mutex);
851 /* ok. now enable and ack CODEC IRQ */
852 spin_lock_irqsave(&chip->reg_lock, flags);
853 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
854 snd_wss_out(chip, CS4231_IRQ_STATUS,
855 CS4231_PLAYBACK_IRQ |
858 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
860 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
861 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
862 chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
863 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
864 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
865 snd_wss_out(chip, CS4231_IRQ_STATUS,
866 CS4231_PLAYBACK_IRQ |
869 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
871 spin_unlock_irqrestore(&chip->reg_lock, flags);
874 mutex_unlock(&chip->open_mutex);
878 static void snd_wss_close(struct snd_wss *chip, unsigned int mode)
882 mutex_lock(&chip->open_mutex);
884 if (chip->mode & WSS_MODE_OPEN) {
885 mutex_unlock(&chip->open_mutex);
888 snd_wss_calibrate_mute(chip, 1);
891 spin_lock_irqsave(&chip->reg_lock, flags);
892 if (!(chip->hardware & WSS_HW_AD1848_MASK))
893 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
894 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
895 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
896 chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
897 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
899 /* now disable record & playback */
901 if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
902 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
903 spin_unlock_irqrestore(&chip->reg_lock, flags);
904 snd_wss_mce_up(chip);
905 spin_lock_irqsave(&chip->reg_lock, flags);
906 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
907 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
908 snd_wss_out(chip, CS4231_IFACE_CTRL,
909 chip->image[CS4231_IFACE_CTRL]);
910 spin_unlock_irqrestore(&chip->reg_lock, flags);
911 snd_wss_mce_down(chip);
912 spin_lock_irqsave(&chip->reg_lock, flags);
915 /* clear IRQ again */
916 if (!(chip->hardware & WSS_HW_AD1848_MASK))
917 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
918 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
919 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
920 spin_unlock_irqrestore(&chip->reg_lock, flags);
922 snd_wss_calibrate_mute(chip, 0);
925 mutex_unlock(&chip->open_mutex);
932 static int snd_wss_timer_open(struct snd_timer *timer)
934 struct snd_wss *chip = snd_timer_chip(timer);
935 snd_wss_open(chip, WSS_MODE_TIMER);
939 static int snd_wss_timer_close(struct snd_timer *timer)
941 struct snd_wss *chip = snd_timer_chip(timer);
942 snd_wss_close(chip, WSS_MODE_TIMER);
946 static struct snd_timer_hardware snd_wss_timer_table =
948 .flags = SNDRV_TIMER_HW_AUTO,
951 .open = snd_wss_timer_open,
952 .close = snd_wss_timer_close,
953 .c_resolution = snd_wss_timer_resolution,
954 .start = snd_wss_timer_start,
955 .stop = snd_wss_timer_stop,
959 * ok.. exported functions..
962 static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,
963 struct snd_pcm_hw_params *hw_params)
965 struct snd_wss *chip = snd_pcm_substream_chip(substream);
966 unsigned char new_pdfr;
969 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
971 new_pdfr = snd_wss_get_format(chip, params_format(hw_params),
972 params_channels(hw_params)) |
973 snd_wss_get_rate(params_rate(hw_params));
974 chip->set_playback_format(chip, hw_params, new_pdfr);
978 static int snd_wss_playback_hw_free(struct snd_pcm_substream *substream)
980 return snd_pcm_lib_free_pages(substream);
983 static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)
985 struct snd_wss *chip = snd_pcm_substream_chip(substream);
986 struct snd_pcm_runtime *runtime = substream->runtime;
988 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
989 unsigned int count = snd_pcm_lib_period_bytes(substream);
991 spin_lock_irqsave(&chip->reg_lock, flags);
992 chip->p_dma_size = size;
993 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
994 snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
995 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
996 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
997 snd_wss_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
998 spin_unlock_irqrestore(&chip->reg_lock, flags);
1000 snd_wss_debug(chip);
1005 static int snd_wss_capture_hw_params(struct snd_pcm_substream *substream,
1006 struct snd_pcm_hw_params *hw_params)
1008 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1009 unsigned char new_cdfr;
1012 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1014 new_cdfr = snd_wss_get_format(chip, params_format(hw_params),
1015 params_channels(hw_params)) |
1016 snd_wss_get_rate(params_rate(hw_params));
1017 chip->set_capture_format(chip, hw_params, new_cdfr);
1021 static int snd_wss_capture_hw_free(struct snd_pcm_substream *substream)
1023 return snd_pcm_lib_free_pages(substream);
1026 static int snd_wss_capture_prepare(struct snd_pcm_substream *substream)
1028 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1029 struct snd_pcm_runtime *runtime = substream->runtime;
1030 unsigned long flags;
1031 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1032 unsigned int count = snd_pcm_lib_period_bytes(substream);
1034 spin_lock_irqsave(&chip->reg_lock, flags);
1035 chip->c_dma_size = size;
1036 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
1037 snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
1038 if (chip->hardware & WSS_HW_AD1848_MASK)
1039 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT],
1042 count = snd_wss_get_count(chip->image[CS4231_REC_FORMAT],
1045 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1046 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
1047 snd_wss_out(chip, CS4231_PLY_UPR_CNT,
1048 (unsigned char) (count >> 8));
1050 snd_wss_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
1051 snd_wss_out(chip, CS4231_REC_UPR_CNT,
1052 (unsigned char) (count >> 8));
1054 spin_unlock_irqrestore(&chip->reg_lock, flags);
1058 void snd_wss_overrange(struct snd_wss *chip)
1060 unsigned long flags;
1063 spin_lock_irqsave(&chip->reg_lock, flags);
1064 res = snd_wss_in(chip, CS4231_TEST_INIT);
1065 spin_unlock_irqrestore(&chip->reg_lock, flags);
1066 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
1067 chip->capture_substream->runtime->overrange++;
1069 EXPORT_SYMBOL(snd_wss_overrange);
1071 irqreturn_t snd_wss_interrupt(int irq, void *dev_id)
1073 struct snd_wss *chip = dev_id;
1074 unsigned char status;
1076 if (chip->hardware & WSS_HW_AD1848_MASK)
1077 /* pretend it was the only possible irq for AD1848 */
1078 status = CS4231_PLAYBACK_IRQ;
1080 status = snd_wss_in(chip, CS4231_IRQ_STATUS);
1081 if (status & CS4231_TIMER_IRQ) {
1083 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1085 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1086 if (status & CS4231_PLAYBACK_IRQ) {
1087 if (chip->mode & WSS_MODE_PLAY) {
1088 if (chip->playback_substream)
1089 snd_pcm_period_elapsed(chip->playback_substream);
1091 if (chip->mode & WSS_MODE_RECORD) {
1092 if (chip->capture_substream) {
1093 snd_wss_overrange(chip);
1094 snd_pcm_period_elapsed(chip->capture_substream);
1099 if (status & CS4231_PLAYBACK_IRQ) {
1100 if (chip->playback_substream)
1101 snd_pcm_period_elapsed(chip->playback_substream);
1103 if (status & CS4231_RECORD_IRQ) {
1104 if (chip->capture_substream) {
1105 snd_wss_overrange(chip);
1106 snd_pcm_period_elapsed(chip->capture_substream);
1111 spin_lock(&chip->reg_lock);
1112 status = ~CS4231_ALL_IRQS | ~status;
1113 if (chip->hardware & WSS_HW_AD1848_MASK)
1114 wss_outb(chip, CS4231P(STATUS), 0);
1116 snd_wss_outm(chip, CS4231_IRQ_STATUS, status, 0);
1117 spin_unlock(&chip->reg_lock);
1120 EXPORT_SYMBOL(snd_wss_interrupt);
1122 static snd_pcm_uframes_t snd_wss_playback_pointer(struct snd_pcm_substream *substream)
1124 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1127 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1129 ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
1130 return bytes_to_frames(substream->runtime, ptr);
1133 static snd_pcm_uframes_t snd_wss_capture_pointer(struct snd_pcm_substream *substream)
1135 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1138 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1140 ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
1141 return bytes_to_frames(substream->runtime, ptr);
1148 static int snd_ad1848_probe(struct snd_wss *chip)
1150 unsigned long flags;
1151 int i, id, rev, ad1847;
1155 for (i = 0; i < 1000; i++) {
1157 if (inb(chip->port + CS4231P(REGSEL)) & CS4231_INIT)
1160 spin_lock_irqsave(&chip->reg_lock, flags);
1161 snd_wss_out(chip, CS4231_MISC_INFO, 0x00);
1162 snd_wss_out(chip, CS4231_LEFT_INPUT, 0xaa);
1163 snd_wss_out(chip, CS4231_RIGHT_INPUT, 0x45);
1164 rev = snd_wss_in(chip, CS4231_RIGHT_INPUT);
1166 spin_unlock_irqrestore(&chip->reg_lock, flags);
1171 if (snd_wss_in(chip, CS4231_LEFT_INPUT) == 0xaa &&
1173 spin_unlock_irqrestore(&chip->reg_lock, flags);
1177 spin_unlock_irqrestore(&chip->reg_lock, flags);
1181 return -ENODEV; /* no valid device found */
1183 if (chip->hardware == WSS_HW_DETECT)
1184 id = ad1847 ? WSS_HW_AD1847 : WSS_HW_AD1848;
1186 spin_lock_irqsave(&chip->reg_lock, flags);
1187 inb(chip->port + CS4231P(STATUS)); /* clear any pendings IRQ */
1188 outb(0, chip->port + CS4231P(STATUS));
1190 if (id == WSS_HW_AD1848) {
1191 /* check if there are more than 16 registers */
1192 rev = snd_wss_in(chip, CS4231_MISC_INFO);
1193 snd_wss_out(chip, CS4231_MISC_INFO, 0x40);
1194 for (i = 0; i < 16; ++i) {
1195 if (snd_wss_in(chip, i) != snd_wss_in(chip, i + 16)) {
1196 id = WSS_HW_CMI8330;
1200 snd_wss_out(chip, CS4231_MISC_INFO, 0x00);
1201 if (id != WSS_HW_CMI8330 && (rev & 0x80))
1203 if (id == WSS_HW_CMI8330 && (rev & 0x0f) != 0x0a)
1206 if (id == WSS_HW_CMI8330) {
1207 /* verify it is not CS4231 by changing the version register */
1208 /* on CMI8330 it is volume control register and can be set 0 */
1209 snd_wss_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1210 snd_wss_dout(chip, CS4231_VERSION, 0x00);
1211 rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1214 snd_wss_out(chip, CS4231_MISC_INFO, 0);
1217 chip->hardware = id;
1219 spin_unlock_irqrestore(&chip->reg_lock, flags);
1220 return 0; /* all things are ok.. */
1223 static int snd_wss_probe(struct snd_wss *chip)
1225 unsigned long flags;
1226 int i, id, rev, regnum;
1230 id = snd_ad1848_probe(chip);
1234 hw = chip->hardware;
1235 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1236 for (i = 0; i < 50; i++) {
1238 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
1241 spin_lock_irqsave(&chip->reg_lock, flags);
1242 snd_wss_out(chip, CS4231_MISC_INFO,
1244 id = snd_wss_in(chip, CS4231_MISC_INFO) & 0x0f;
1245 spin_unlock_irqrestore(&chip->reg_lock, flags);
1247 break; /* this is valid value */
1250 snd_printdd("wss: port = 0x%lx, id = 0x%x\n", chip->port, id);
1252 return -ENODEV; /* no valid device found */
1254 rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1255 snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
1257 unsigned char tmp = snd_wss_in(chip, 23);
1258 snd_wss_out(chip, 23, ~tmp);
1259 if (snd_wss_in(chip, 23) != tmp)
1260 chip->hardware = WSS_HW_AD1845;
1262 chip->hardware = WSS_HW_CS4231;
1263 } else if (rev == 0xa0) {
1264 chip->hardware = WSS_HW_CS4231A;
1265 } else if (rev == 0xa2) {
1266 chip->hardware = WSS_HW_CS4232;
1267 } else if (rev == 0xb2) {
1268 chip->hardware = WSS_HW_CS4232A;
1269 } else if (rev == 0x83) {
1270 chip->hardware = WSS_HW_CS4236;
1271 } else if (rev == 0x03) {
1272 chip->hardware = WSS_HW_CS4236B;
1274 snd_printk("unknown CS chip with version 0x%x\n", rev);
1275 return -ENODEV; /* unknown CS4231 chip? */
1278 spin_lock_irqsave(&chip->reg_lock, flags);
1279 wss_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
1280 wss_outb(chip, CS4231P(STATUS), 0);
1282 spin_unlock_irqrestore(&chip->reg_lock, flags);
1284 if (!(chip->hardware & WSS_HW_AD1848_MASK))
1285 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1286 switch (chip->hardware) {
1287 case WSS_HW_INTERWAVE:
1288 chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
1291 case WSS_HW_CS4236B:
1292 case WSS_HW_CS4237B:
1293 case WSS_HW_CS4238B:
1295 if (hw == WSS_HW_DETECT3)
1296 chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
1298 chip->hardware = WSS_HW_CS4236;
1302 chip->image[CS4231_IFACE_CTRL] =
1303 (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
1304 (chip->single_dma ? CS4231_SINGLE_DMA : 0);
1305 if (chip->hardware != WSS_HW_OPTI93X) {
1306 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1307 chip->image[CS4231_ALT_FEATURE_2] =
1308 chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;
1310 ptr = (unsigned char *) &chip->image;
1311 regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;
1312 snd_wss_mce_down(chip);
1313 spin_lock_irqsave(&chip->reg_lock, flags);
1314 for (i = 0; i < regnum; i++) /* ok.. fill all registers */
1315 snd_wss_out(chip, i, *ptr++);
1316 spin_unlock_irqrestore(&chip->reg_lock, flags);
1317 snd_wss_mce_up(chip);
1318 snd_wss_mce_down(chip);
1322 /* ok.. try check hardware version for CS4236+ chips */
1323 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1324 if (chip->hardware == WSS_HW_CS4236B) {
1325 rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
1326 snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
1327 id = snd_cs4236_ext_in(chip, CS4236_VERSION);
1328 snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
1329 snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
1330 if ((id & 0x1f) == 0x1d) { /* CS4235 */
1331 chip->hardware = WSS_HW_CS4235;
1338 snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
1340 } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
1346 chip->hardware = WSS_HW_CS4236B;
1349 snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
1351 } else if ((id & 0x1f) == 0x08) { /* CS4237B */
1352 chip->hardware = WSS_HW_CS4237B;
1360 snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
1362 } else if ((id & 0x1f) == 0x09) { /* CS4238B */
1363 chip->hardware = WSS_HW_CS4238B;
1370 snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
1372 } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
1373 chip->hardware = WSS_HW_CS4239;
1380 snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
1383 snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
1387 return 0; /* all things are ok.. */
1394 static struct snd_pcm_hardware snd_wss_playback =
1396 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1397 SNDRV_PCM_INFO_MMAP_VALID |
1398 SNDRV_PCM_INFO_RESUME |
1399 SNDRV_PCM_INFO_SYNC_START),
1400 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1401 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1402 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1407 .buffer_bytes_max = (128*1024),
1408 .period_bytes_min = 64,
1409 .period_bytes_max = (128*1024),
1411 .periods_max = 1024,
1415 static struct snd_pcm_hardware snd_wss_capture =
1417 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1418 SNDRV_PCM_INFO_MMAP_VALID |
1419 SNDRV_PCM_INFO_RESUME |
1420 SNDRV_PCM_INFO_SYNC_START),
1421 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1422 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1423 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1428 .buffer_bytes_max = (128*1024),
1429 .period_bytes_min = 64,
1430 .period_bytes_max = (128*1024),
1432 .periods_max = 1024,
1440 static int snd_wss_playback_open(struct snd_pcm_substream *substream)
1442 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1443 struct snd_pcm_runtime *runtime = substream->runtime;
1446 runtime->hw = snd_wss_playback;
1448 /* hardware limitation of older chipsets */
1449 if (chip->hardware & WSS_HW_AD1848_MASK)
1450 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1451 SNDRV_PCM_FMTBIT_S16_BE);
1453 /* hardware bug in InterWave chipset */
1454 if (chip->hardware == WSS_HW_INTERWAVE && chip->dma1 > 3)
1455 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
1457 /* hardware limitation of cheap chips */
1458 if (chip->hardware == WSS_HW_CS4235 ||
1459 chip->hardware == WSS_HW_CS4239)
1460 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1462 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
1463 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
1465 if (chip->claim_dma) {
1466 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
1470 err = snd_wss_open(chip, WSS_MODE_PLAY);
1472 if (chip->release_dma)
1473 chip->release_dma(chip, chip->dma_private_data, chip->dma1);
1474 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1477 chip->playback_substream = substream;
1478 snd_pcm_set_sync(substream);
1479 chip->rate_constraint(runtime);
1483 static int snd_wss_capture_open(struct snd_pcm_substream *substream)
1485 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1486 struct snd_pcm_runtime *runtime = substream->runtime;
1489 runtime->hw = snd_wss_capture;
1491 /* hardware limitation of older chipsets */
1492 if (chip->hardware & WSS_HW_AD1848_MASK)
1493 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1494 SNDRV_PCM_FMTBIT_S16_BE);
1496 /* hardware limitation of cheap chips */
1497 if (chip->hardware == WSS_HW_CS4235 ||
1498 chip->hardware == WSS_HW_CS4239 ||
1499 chip->hardware == WSS_HW_OPTI93X)
1500 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 |
1501 SNDRV_PCM_FMTBIT_S16_LE;
1503 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
1504 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
1506 if (chip->claim_dma) {
1507 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
1511 err = snd_wss_open(chip, WSS_MODE_RECORD);
1513 if (chip->release_dma)
1514 chip->release_dma(chip, chip->dma_private_data, chip->dma2);
1515 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1518 chip->capture_substream = substream;
1519 snd_pcm_set_sync(substream);
1520 chip->rate_constraint(runtime);
1524 static int snd_wss_playback_close(struct snd_pcm_substream *substream)
1526 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1528 chip->playback_substream = NULL;
1529 snd_wss_close(chip, WSS_MODE_PLAY);
1533 static int snd_wss_capture_close(struct snd_pcm_substream *substream)
1535 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1537 chip->capture_substream = NULL;
1538 snd_wss_close(chip, WSS_MODE_RECORD);
1542 static void snd_wss_thinkpad_twiddle(struct snd_wss *chip, int on)
1546 if (!chip->thinkpad_flag)
1549 outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
1550 tmp = inb(AD1848_THINKPAD_CTL_PORT2);
1554 tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
1557 tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
1559 outb(tmp, AD1848_THINKPAD_CTL_PORT2);
1564 /* lowlevel suspend callback for CS4231 */
1565 static void snd_wss_suspend(struct snd_wss *chip)
1568 unsigned long flags;
1570 snd_pcm_suspend_all(chip->pcm);
1571 spin_lock_irqsave(&chip->reg_lock, flags);
1572 for (reg = 0; reg < 32; reg++)
1573 chip->image[reg] = snd_wss_in(chip, reg);
1574 spin_unlock_irqrestore(&chip->reg_lock, flags);
1575 if (chip->thinkpad_flag)
1576 snd_wss_thinkpad_twiddle(chip, 0);
1579 /* lowlevel resume callback for CS4231 */
1580 static void snd_wss_resume(struct snd_wss *chip)
1583 unsigned long flags;
1586 if (chip->thinkpad_flag)
1587 snd_wss_thinkpad_twiddle(chip, 1);
1588 snd_wss_mce_up(chip);
1589 spin_lock_irqsave(&chip->reg_lock, flags);
1590 for (reg = 0; reg < 32; reg++) {
1592 case CS4231_VERSION:
1595 snd_wss_out(chip, reg, chip->image[reg]);
1599 spin_unlock_irqrestore(&chip->reg_lock, flags);
1601 snd_wss_mce_down(chip);
1603 /* The following is a workaround to avoid freeze after resume on TP600E.
1604 This is the first half of copy of snd_wss_mce_down(), but doesn't
1605 include rescheduling. -- iwai
1607 snd_wss_busy_wait(chip);
1608 spin_lock_irqsave(&chip->reg_lock, flags);
1609 chip->mce_bit &= ~CS4231_MCE;
1610 timeout = wss_inb(chip, CS4231P(REGSEL));
1611 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
1612 spin_unlock_irqrestore(&chip->reg_lock, flags);
1613 if (timeout == 0x80)
1614 snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
1615 if ((timeout & CS4231_MCE) == 0 ||
1616 !(chip->hardware & (WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK))) {
1619 snd_wss_busy_wait(chip);
1622 #endif /* CONFIG_PM */
1624 static int snd_wss_free(struct snd_wss *chip)
1626 release_and_free_resource(chip->res_port);
1627 release_and_free_resource(chip->res_cport);
1628 if (chip->irq >= 0) {
1629 disable_irq(chip->irq);
1630 if (!(chip->hwshare & WSS_HWSHARE_IRQ))
1631 free_irq(chip->irq, (void *) chip);
1633 if (!(chip->hwshare & WSS_HWSHARE_DMA1) && chip->dma1 >= 0) {
1634 snd_dma_disable(chip->dma1);
1635 free_dma(chip->dma1);
1637 if (!(chip->hwshare & WSS_HWSHARE_DMA2) &&
1638 chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
1639 snd_dma_disable(chip->dma2);
1640 free_dma(chip->dma2);
1643 snd_device_free(chip->card, chip->timer);
1648 static int snd_wss_dev_free(struct snd_device *device)
1650 struct snd_wss *chip = device->device_data;
1651 return snd_wss_free(chip);
1654 const char *snd_wss_chip_id(struct snd_wss *chip)
1656 switch (chip->hardware) {
1659 case WSS_HW_CS4231A:
1663 case WSS_HW_CS4232A:
1669 case WSS_HW_CS4236B:
1671 case WSS_HW_CS4237B:
1673 case WSS_HW_CS4238B:
1677 case WSS_HW_INTERWAVE:
1678 return "AMD InterWave";
1679 case WSS_HW_OPL3SA2:
1680 return chip->card->shortname;
1683 case WSS_HW_OPTI93X:
1691 case WSS_HW_CMI8330:
1692 return "CMI8330/C3D";
1697 EXPORT_SYMBOL(snd_wss_chip_id);
1699 static int snd_wss_new(struct snd_card *card,
1700 unsigned short hardware,
1701 unsigned short hwshare,
1702 struct snd_wss **rchip)
1704 struct snd_wss *chip;
1707 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1710 chip->hardware = hardware;
1711 chip->hwshare = hwshare;
1713 spin_lock_init(&chip->reg_lock);
1714 mutex_init(&chip->mce_mutex);
1715 mutex_init(&chip->open_mutex);
1717 chip->rate_constraint = snd_wss_xrate;
1718 chip->set_playback_format = snd_wss_playback_format;
1719 chip->set_capture_format = snd_wss_capture_format;
1720 if (chip->hardware == WSS_HW_OPTI93X)
1721 memcpy(&chip->image, &snd_opti93x_original_image,
1722 sizeof(snd_opti93x_original_image));
1724 memcpy(&chip->image, &snd_wss_original_image,
1725 sizeof(snd_wss_original_image));
1726 if (chip->hardware & WSS_HW_AD1848_MASK) {
1727 chip->image[CS4231_PIN_CTRL] = 0;
1728 chip->image[CS4231_TEST_INIT] = 0;
1735 int snd_wss_create(struct snd_card *card,
1737 unsigned long cport,
1738 int irq, int dma1, int dma2,
1739 unsigned short hardware,
1740 unsigned short hwshare,
1741 struct snd_wss **rchip)
1743 static struct snd_device_ops ops = {
1744 .dev_free = snd_wss_dev_free,
1746 struct snd_wss *chip;
1749 err = snd_wss_new(card, hardware, hwshare, &chip);
1757 chip->res_port = request_region(port, 4, "WSS");
1758 if (!chip->res_port) {
1759 snd_printk(KERN_ERR "wss: can't grab port 0x%lx\n", port);
1764 if ((long)cport >= 0) {
1765 chip->res_cport = request_region(cport, 8, "CS4232 Control");
1766 if (!chip->res_cport) {
1768 "wss: can't grab control port 0x%lx\n", cport);
1773 chip->cport = cport;
1774 if (!(hwshare & WSS_HWSHARE_IRQ))
1775 if (request_irq(irq, snd_wss_interrupt, IRQF_DISABLED,
1776 "WSS", (void *) chip)) {
1777 snd_printk(KERN_ERR "wss: can't grab IRQ %d\n", irq);
1782 if (!(hwshare & WSS_HWSHARE_DMA1) && request_dma(dma1, "WSS - 1")) {
1783 snd_printk(KERN_ERR "wss: can't grab DMA1 %d\n", dma1);
1788 if (!(hwshare & WSS_HWSHARE_DMA2) && dma1 != dma2 &&
1789 dma2 >= 0 && request_dma(dma2, "WSS - 2")) {
1790 snd_printk(KERN_ERR "wss: can't grab DMA2 %d\n", dma2);
1794 if (dma1 == dma2 || dma2 < 0) {
1795 chip->single_dma = 1;
1796 chip->dma2 = chip->dma1;
1800 if (hardware == WSS_HW_THINKPAD) {
1801 chip->thinkpad_flag = 1;
1802 chip->hardware = WSS_HW_DETECT; /* reset */
1803 snd_wss_thinkpad_twiddle(chip, 1);
1807 if (snd_wss_probe(chip) < 0) {
1814 if (chip->hardware & WSS_HW_CS4232_MASK) {
1815 if (chip->res_cport == NULL)
1816 snd_printk("CS4232 control port features are not accessible\n");
1820 /* Register device */
1821 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1828 /* Power Management */
1829 chip->suspend = snd_wss_suspend;
1830 chip->resume = snd_wss_resume;
1836 EXPORT_SYMBOL(snd_wss_create);
1838 static struct snd_pcm_ops snd_wss_playback_ops = {
1839 .open = snd_wss_playback_open,
1840 .close = snd_wss_playback_close,
1841 .ioctl = snd_pcm_lib_ioctl,
1842 .hw_params = snd_wss_playback_hw_params,
1843 .hw_free = snd_wss_playback_hw_free,
1844 .prepare = snd_wss_playback_prepare,
1845 .trigger = snd_wss_trigger,
1846 .pointer = snd_wss_playback_pointer,
1849 static struct snd_pcm_ops snd_wss_capture_ops = {
1850 .open = snd_wss_capture_open,
1851 .close = snd_wss_capture_close,
1852 .ioctl = snd_pcm_lib_ioctl,
1853 .hw_params = snd_wss_capture_hw_params,
1854 .hw_free = snd_wss_capture_hw_free,
1855 .prepare = snd_wss_capture_prepare,
1856 .trigger = snd_wss_trigger,
1857 .pointer = snd_wss_capture_pointer,
1860 int snd_wss_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm)
1862 struct snd_pcm *pcm;
1865 err = snd_pcm_new(chip->card, "WSS", device, 1, 1, &pcm);
1869 spin_lock_init(&chip->reg_lock);
1870 mutex_init(&chip->mce_mutex);
1871 mutex_init(&chip->open_mutex);
1873 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_wss_playback_ops);
1874 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_wss_capture_ops);
1877 pcm->private_data = chip;
1878 pcm->info_flags = 0;
1879 if (chip->single_dma)
1880 pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
1881 if (chip->hardware != WSS_HW_INTERWAVE)
1882 pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
1883 strcpy(pcm->name, snd_wss_chip_id(chip));
1885 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1887 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
1894 EXPORT_SYMBOL(snd_wss_pcm);
1896 static void snd_wss_timer_free(struct snd_timer *timer)
1898 struct snd_wss *chip = timer->private_data;
1902 int snd_wss_timer(struct snd_wss *chip, int device, struct snd_timer **rtimer)
1904 struct snd_timer *timer;
1905 struct snd_timer_id tid;
1908 /* Timer initialization */
1909 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1910 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1911 tid.card = chip->card->number;
1912 tid.device = device;
1914 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1916 strcpy(timer->name, snd_wss_chip_id(chip));
1917 timer->private_data = chip;
1918 timer->private_free = snd_wss_timer_free;
1919 timer->hw = snd_wss_timer_table;
1920 chip->timer = timer;
1925 EXPORT_SYMBOL(snd_wss_timer);
1931 static int snd_wss_info_mux(struct snd_kcontrol *kcontrol,
1932 struct snd_ctl_elem_info *uinfo)
1934 static char *texts[4] = {
1935 "Line", "Aux", "Mic", "Mix"
1937 static char *opl3sa_texts[4] = {
1938 "Line", "CD", "Mic", "Mix"
1940 static char *gusmax_texts[4] = {
1941 "Line", "Synth", "Mic", "Mix"
1943 char **ptexts = texts;
1944 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1946 snd_assert(chip->card != NULL, return -EINVAL);
1947 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1949 uinfo->value.enumerated.items = 4;
1950 if (uinfo->value.enumerated.item > 3)
1951 uinfo->value.enumerated.item = 3;
1952 if (!strcmp(chip->card->driver, "GUS MAX"))
1953 ptexts = gusmax_texts;
1954 switch (chip->hardware) {
1955 case WSS_HW_INTERWAVE:
1956 ptexts = gusmax_texts;
1958 case WSS_HW_OPL3SA2:
1959 ptexts = opl3sa_texts;
1962 strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
1966 static int snd_wss_get_mux(struct snd_kcontrol *kcontrol,
1967 struct snd_ctl_elem_value *ucontrol)
1969 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1970 unsigned long flags;
1972 spin_lock_irqsave(&chip->reg_lock, flags);
1973 ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1974 ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1975 spin_unlock_irqrestore(&chip->reg_lock, flags);
1979 static int snd_wss_put_mux(struct snd_kcontrol *kcontrol,
1980 struct snd_ctl_elem_value *ucontrol)
1982 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1983 unsigned long flags;
1984 unsigned short left, right;
1987 if (ucontrol->value.enumerated.item[0] > 3 ||
1988 ucontrol->value.enumerated.item[1] > 3)
1990 left = ucontrol->value.enumerated.item[0] << 6;
1991 right = ucontrol->value.enumerated.item[1] << 6;
1992 spin_lock_irqsave(&chip->reg_lock, flags);
1993 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1994 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1995 change = left != chip->image[CS4231_LEFT_INPUT] ||
1996 right != chip->image[CS4231_RIGHT_INPUT];
1997 snd_wss_out(chip, CS4231_LEFT_INPUT, left);
1998 snd_wss_out(chip, CS4231_RIGHT_INPUT, right);
1999 spin_unlock_irqrestore(&chip->reg_lock, flags);
2003 int snd_wss_info_single(struct snd_kcontrol *kcontrol,
2004 struct snd_ctl_elem_info *uinfo)
2006 int mask = (kcontrol->private_value >> 16) & 0xff;
2008 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2010 uinfo->value.integer.min = 0;
2011 uinfo->value.integer.max = mask;
2014 EXPORT_SYMBOL(snd_wss_info_single);
2016 int snd_wss_get_single(struct snd_kcontrol *kcontrol,
2017 struct snd_ctl_elem_value *ucontrol)
2019 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2020 unsigned long flags;
2021 int reg = kcontrol->private_value & 0xff;
2022 int shift = (kcontrol->private_value >> 8) & 0xff;
2023 int mask = (kcontrol->private_value >> 16) & 0xff;
2024 int invert = (kcontrol->private_value >> 24) & 0xff;
2026 spin_lock_irqsave(&chip->reg_lock, flags);
2027 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
2028 spin_unlock_irqrestore(&chip->reg_lock, flags);
2030 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2033 EXPORT_SYMBOL(snd_wss_get_single);
2035 int snd_wss_put_single(struct snd_kcontrol *kcontrol,
2036 struct snd_ctl_elem_value *ucontrol)
2038 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2039 unsigned long flags;
2040 int reg = kcontrol->private_value & 0xff;
2041 int shift = (kcontrol->private_value >> 8) & 0xff;
2042 int mask = (kcontrol->private_value >> 16) & 0xff;
2043 int invert = (kcontrol->private_value >> 24) & 0xff;
2047 val = (ucontrol->value.integer.value[0] & mask);
2051 spin_lock_irqsave(&chip->reg_lock, flags);
2052 val = (chip->image[reg] & ~(mask << shift)) | val;
2053 change = val != chip->image[reg];
2054 snd_wss_out(chip, reg, val);
2055 spin_unlock_irqrestore(&chip->reg_lock, flags);
2058 EXPORT_SYMBOL(snd_wss_put_single);
2060 int snd_wss_info_double(struct snd_kcontrol *kcontrol,
2061 struct snd_ctl_elem_info *uinfo)
2063 int mask = (kcontrol->private_value >> 24) & 0xff;
2065 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2067 uinfo->value.integer.min = 0;
2068 uinfo->value.integer.max = mask;
2071 EXPORT_SYMBOL(snd_wss_info_double);
2073 int snd_wss_get_double(struct snd_kcontrol *kcontrol,
2074 struct snd_ctl_elem_value *ucontrol)
2076 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2077 unsigned long flags;
2078 int left_reg = kcontrol->private_value & 0xff;
2079 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2080 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2081 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2082 int mask = (kcontrol->private_value >> 24) & 0xff;
2083 int invert = (kcontrol->private_value >> 22) & 1;
2085 spin_lock_irqsave(&chip->reg_lock, flags);
2086 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
2087 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
2088 spin_unlock_irqrestore(&chip->reg_lock, flags);
2090 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2091 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
2095 EXPORT_SYMBOL(snd_wss_get_double);
2097 int snd_wss_put_double(struct snd_kcontrol *kcontrol,
2098 struct snd_ctl_elem_value *ucontrol)
2100 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2101 unsigned long flags;
2102 int left_reg = kcontrol->private_value & 0xff;
2103 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2104 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2105 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2106 int mask = (kcontrol->private_value >> 24) & 0xff;
2107 int invert = (kcontrol->private_value >> 22) & 1;
2109 unsigned short val1, val2;
2111 val1 = ucontrol->value.integer.value[0] & mask;
2112 val2 = ucontrol->value.integer.value[1] & mask;
2117 val1 <<= shift_left;
2118 val2 <<= shift_right;
2119 spin_lock_irqsave(&chip->reg_lock, flags);
2120 if (left_reg != right_reg) {
2121 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
2122 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
2123 change = val1 != chip->image[left_reg] ||
2124 val2 != chip->image[right_reg];
2125 snd_wss_out(chip, left_reg, val1);
2126 snd_wss_out(chip, right_reg, val2);
2128 mask = (mask << shift_left) | (mask << shift_right);
2129 val1 = (chip->image[left_reg] & ~mask) | val1 | val2;
2130 change = val1 != chip->image[left_reg];
2131 snd_wss_out(chip, left_reg, val1);
2133 spin_unlock_irqrestore(&chip->reg_lock, flags);
2136 EXPORT_SYMBOL(snd_wss_put_double);
2138 static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
2139 static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
2140 static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
2142 static struct snd_kcontrol_new snd_ad1848_controls[] = {
2143 WSS_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT,
2145 WSS_DOUBLE_TLV("PCM Playback Volume", 0,
2146 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,
2148 WSS_DOUBLE("Aux Playback Switch", 0,
2149 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2150 WSS_DOUBLE_TLV("Aux Playback Volume", 0,
2151 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
2152 db_scale_5bit_12db_max),
2153 WSS_DOUBLE("Aux Playback Switch", 1,
2154 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2155 WSS_DOUBLE_TLV("Aux Playback Volume", 1,
2156 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
2157 db_scale_5bit_12db_max),
2158 WSS_DOUBLE_TLV("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT,
2159 0, 0, 15, 0, db_scale_rec_gain),
2161 .name = "Capture Source",
2162 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2163 .info = snd_wss_info_mux,
2164 .get = snd_wss_get_mux,
2165 .put = snd_wss_put_mux,
2167 WSS_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
2168 WSS_SINGLE_TLV("Loopback Capture Volume", 0, CS4231_LOOPBACK, 1, 63, 0,
2172 static struct snd_kcontrol_new snd_wss_controls[] = {
2173 WSS_DOUBLE("PCM Playback Switch", 0,
2174 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2175 WSS_DOUBLE("PCM Playback Volume", 0,
2176 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
2177 WSS_DOUBLE("Line Playback Switch", 0,
2178 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2179 WSS_DOUBLE("Line Playback Volume", 0,
2180 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
2181 WSS_DOUBLE("Aux Playback Switch", 0,
2182 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2183 WSS_DOUBLE("Aux Playback Volume", 0,
2184 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
2185 WSS_DOUBLE("Aux Playback Switch", 1,
2186 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2187 WSS_DOUBLE("Aux Playback Volume", 1,
2188 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
2189 WSS_SINGLE("Mono Playback Switch", 0,
2190 CS4231_MONO_CTRL, 7, 1, 1),
2191 WSS_SINGLE("Mono Playback Volume", 0,
2192 CS4231_MONO_CTRL, 0, 15, 1),
2193 WSS_SINGLE("Mono Output Playback Switch", 0,
2194 CS4231_MONO_CTRL, 6, 1, 1),
2195 WSS_SINGLE("Mono Output Playback Bypass", 0,
2196 CS4231_MONO_CTRL, 5, 1, 0),
2197 WSS_DOUBLE("Capture Volume", 0,
2198 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2200 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2201 .name = "Capture Source",
2202 .info = snd_wss_info_mux,
2203 .get = snd_wss_get_mux,
2204 .put = snd_wss_put_mux,
2206 WSS_DOUBLE("Mic Boost", 0,
2207 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2208 WSS_SINGLE("Loopback Capture Switch", 0,
2209 CS4231_LOOPBACK, 0, 1, 0),
2210 WSS_SINGLE("Loopback Capture Volume", 0,
2211 CS4231_LOOPBACK, 2, 63, 1)
2214 static struct snd_kcontrol_new snd_opti93x_controls[] = {
2215 WSS_DOUBLE("Master Playback Switch", 0,
2216 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 7, 7, 1, 1),
2217 WSS_DOUBLE("Master Playback Volume", 0,
2218 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 1, 1, 31, 1),
2219 WSS_DOUBLE("PCM Playback Switch", 0,
2220 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2221 WSS_DOUBLE("PCM Playback Volume", 0,
2222 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 31, 1),
2223 WSS_DOUBLE("FM Playback Switch", 0,
2224 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2225 WSS_DOUBLE("FM Playback Volume", 0,
2226 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 1, 1, 15, 1),
2227 WSS_DOUBLE("Line Playback Switch", 0,
2228 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2229 WSS_DOUBLE("Line Playback Volume", 0,
2230 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 15, 1),
2231 WSS_DOUBLE("Mic Playback Switch", 0,
2232 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 7, 7, 1, 1),
2233 WSS_DOUBLE("Mic Playback Volume", 0,
2234 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 1, 1, 15, 1),
2235 WSS_DOUBLE("Mic Boost", 0,
2236 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2237 WSS_DOUBLE("CD Playback Switch", 0,
2238 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2239 WSS_DOUBLE("CD Playback Volume", 0,
2240 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 1, 1, 15, 1),
2241 WSS_DOUBLE("Aux Playback Switch", 0,
2242 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 7, 7, 1, 1),
2243 WSS_DOUBLE("Aux Playback Volume", 0,
2244 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 1, 1, 15, 1),
2245 WSS_DOUBLE("Capture Volume", 0,
2246 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2248 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2249 .name = "Capture Source",
2250 .info = snd_wss_info_mux,
2251 .get = snd_wss_get_mux,
2252 .put = snd_wss_put_mux,
2256 int snd_wss_mixer(struct snd_wss *chip)
2258 struct snd_card *card;
2262 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
2266 strcpy(card->mixername, chip->pcm->name);
2268 if (chip->hardware == WSS_HW_OPTI93X)
2269 for (idx = 0; idx < ARRAY_SIZE(snd_opti93x_controls); idx++) {
2270 err = snd_ctl_add(card,
2271 snd_ctl_new1(&snd_opti93x_controls[idx],
2276 else if (chip->hardware & WSS_HW_AD1848_MASK)
2277 for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++) {
2278 err = snd_ctl_add(card,
2279 snd_ctl_new1(&snd_ad1848_controls[idx],
2285 for (idx = 0; idx < ARRAY_SIZE(snd_wss_controls); idx++) {
2286 err = snd_ctl_add(card,
2287 snd_ctl_new1(&snd_wss_controls[idx],
2294 EXPORT_SYMBOL(snd_wss_mixer);
2296 const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction)
2298 return direction == SNDRV_PCM_STREAM_PLAYBACK ?
2299 &snd_wss_playback_ops : &snd_wss_capture_ops;
2301 EXPORT_SYMBOL(snd_wss_get_pcm_ops);
2307 static int __init alsa_wss_init(void)
2312 static void __exit alsa_wss_exit(void)
2316 module_init(alsa_wss_init);
2317 module_exit(alsa_wss_exit);