2 * linux/sound/arm/omap/omap-alsa-eac.c
4 * OMAP24xx Enhanced Audio Controller sound driver
6 * Copyright (C) 2006 Nokia Corporation
8 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
12 * Copyright (C) 2004 Texas Instruments, Inc.
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * version 2 as published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but
19 * WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
32 #include <linux/device.h>
33 #include <linux/init.h>
34 #include <linux/kernel.h>
35 #include <linux/err.h>
36 #include <linux/module.h>
37 #include <linux/moduleparam.h>
38 #include <linux/delay.h>
39 #include <linux/platform_device.h>
40 #include <linux/clk.h>
43 #include <asm/arch/eac.h>
45 #include <sound/driver.h>
46 #include <sound/core.h>
47 #include <sound/initval.h>
50 #define EAC_CPCFR1 0x0000
51 #define EAC_CPCFR2 0x0004
52 #define EAC_CPCFR3 0x0008
53 #define EAC_CPCFR4 0x000C
54 #define EAC_CPTCTL 0x0010
55 #define EAC_CPTTADR 0x0014
56 #define EAC_CPTDATL 0x0018
57 #define EAC_CPTDATH 0x001C
58 #define EAC_CPTVSLL 0x0020
59 #define EAC_CPTVSLH 0x0024
60 #define EAC_MPCTR 0x0040
61 #define EAC_MPMCCFR 0x0044
62 #define EAC_BPCTR 0x0060
63 #define EAC_BPMCCFR 0x0064
64 #define EAC_AMSCFR 0x0080
65 #define EAC_AMVCTR 0x0084
66 #define EAC_AM1VCTR 0x0088
67 #define EAC_AM2VCTR 0x008C
68 #define EAC_AM3VCTR 0x0090
69 #define EAC_ASTCTR 0x0094
70 #define EAC_APD1LCR 0x0098
71 #define EAC_APD1RCR 0x009C
72 #define EAC_APD2LCR 0x00A0
73 #define EAC_APD2RCR 0x00A4
74 #define EAC_APD3LCR 0x00A8
75 #define EAC_APD3RCR 0x00AC
76 #define EAC_APD4R 0x00B0
77 #define EAC_ADWR 0x00B4
78 #define EAC_ADRDR 0x00B8
79 #define EAC_AGCFR 0x00BC
80 #define EAC_AGCTR 0x00C0
81 #define EAC_AGCFR2 0x00C4
82 #define EAC_AGCFR3 0x00C8
83 #define EAC_MBPDMACTR 0x00CC
84 #define EAC_MPDDMARR 0x00D0
85 #define EAC_MPDDMAWR 0x00D4
86 #define EAC_MPUDMARR 0x00D8
87 #define EAC_MPUDMAWR 0x00E0
88 #define EAC_BPDDMARR 0x00E4
89 #define EAC_BPDDMAWR 0x00E8
90 #define EAC_BPUDMARR 0x00EC
91 #define EAC_BPUDMAWR 0x00F0
92 #define EAC_VERSION 0x0100
93 #define EAC_SYSCONFIG 0x0104
94 #define EAC_SYSSTATUS 0x0108
97 #define CPTCTL_RXF (1 << 7) /* receive data register full */
98 #define CPTCTL_RXIE (1 << 6) /* receive interrupt enable */
99 #define CPTCTL_TXE (1 << 5) /* transmit register empty */
100 #define CPTCTL_TXIE (1 << 4) /* transmit interrupt enable */
101 #define CPTCTL_CPEN (1 << 3) /* codec port enable */
102 #define CPTCTL_CRST (1 << 0) /* external codec reset */
105 #define CPCFR1_MTSL(val) ((val & 0x1f) << 3) /* number of time slots per frame */
106 #define CPCFR1_MTSL_BITS (0x1f << 3)
107 #define CPCFR1_MODE(val) ((val & 0x7) << 0) /* codec port interface mode */
108 #define CPCFR1_MODE_BITS (0x7 << 0)
111 #define CPCFR2_TSLOL(val) ((val & 0x3) << 6) /* time slot 0 length in number of serial clock (CLK_BIT) cycles */
112 #define CPCFR2_TSLOL_BITS (0x3 << 6)
113 #define CPCFR2_BPTSL(val) ((val & 0x7) << 3) /* number of data bits per audio time slot */
114 #define CPCFR2_BPTSL_BITS (0x7 << 3)
115 #define CPCFR2_TSLL(val) ((val & 0x7) << 0) /* time slot lenght (except slot 0) in number of serial clock cycles */
116 #define CPCFR2_TSLL_BITS (0x7 << 0)
119 #define CPCFR3_DDLY (1 << 7) /* data delay: data bits start according to SYNC signal leading edge */
120 #define CPCFR3_TRSEN (1 << 6) /* 3-state enable: data serial output state during nonvalid audio frames */
121 #define CPCFR3_CLKBP (1 << 5) /* clock polarity */
122 #define CPCFR3_CSYNCP (1 << 4) /* cp_sync(synchro) polarity */
123 #define CPCFR3_CSYNCL (1 << 3) /* csync length */
125 #define CPCFR3_CSCLKD (1 << 1) /* cp_sclk port (serial clock) direction */
126 #define CPCFR3_CSYNCD (1 << 0) /* cp_sync (synchro) direction */
129 #define CPCFR4_ATSL(val) ((val & 0xf) << 4) /* audio time slots for secondary communication address and data values */
130 #define CPCFR4_ATSL_BITS (0xf << 4)
131 #define CPCFR4_CLKS (1 << 3) /* clock source */
132 #define CPCFR4_DIVB(val) ((val & 0x7) << 0) /* cp_sclk driver value */
133 #define CPCFR4_DIVB_BITS (0x7 << 0)
136 #define AGCFR_MN_ST (1 << 10) /* mono/stereo audio file */
137 #define AGCFR_B8_16 (1 << 9) /* 8 bits/16 bits audio file */
138 #define AGCFR_LI_BI (1 << 8) /* audio file endianism */
139 #define AGCFR_FSINT(val) ((val & 0x3) << 6) /* intermediate sample frequency for DMA read and write operations */
140 #define AGCFR_FINST_BITS (0x3 << 6)
142 #define AGCFR_FSINT_8000 (0) /* 8000 Hz */
143 #define AGCFR_FSINT_11025 (1) /* 11025 Hz */
144 #define AGCFR_FSINT_22050 (2) /* 22050 Hz */
145 #define AGCFR_FSINT_44100 (3) /* 44100 Hz */
147 #define AGCFR_AUD_CKSRC(val)((val & 0x3) << 4) /* audio processing clock source */
148 #define AGCFR_AUD_CKSRC_BITS (0x3 << 4)
149 #define AGCFR_M_CKSRC (1 << 3) /* modem interface clock source */
150 #define AGCFR_MCLK_OUT (1 << 1)
151 #define AGCFR_MCLK (1 << 0)
155 #define AGCTR_AUDRD (1 << 15) /* audio ready */
156 #define AGCTR_AUDRDI (1 << 14) /* audio ready interrupt status */
157 #define AGCTR_AUDRDIEN (1 << 13) /* audio ready interrupt enable */
158 #define AGCTR_DMAREN (1 << 12) /* audio files play operation */
159 #define AGCTR_DMAWEN (1 << 11) /* audio file record operation */
160 /* bits 10:4 reserved */
161 #define AGCTR_MCLK_EN (1 << 3) /* internal MCLK enable */
162 #define AGCTR_OSCMCLK_EN (1 << 2) /* OSCMCLK_EN output for MCLK oscillator control */
163 #define AGCTR_AUDEN (1 << 1) /* audio processing enable/disable */
164 #define AGCTR_EACPWD (1 << 0) /* EAC operation */
167 #define AGCFR2_BT_MD_WIDEBAND (1 << 5) /* the BT device and modem AuSPIs wide-band mode */
168 #define AGCFR2_MCLK_I2S_N11M_12M (1 << 4) /* MCLK freq indicator for audio operations */
169 #define AGCFR2_I2S_N44K_48K (1 << 3) /* Frame sample frecuency of I2S codec port, does not generate value */
170 #define AGCFR2_FSINT2(val) ((val & 0x7) << 0) /* intermediate sample frequency for DMA channel read and write operations */
171 #define AGCFR2_FSINT2_BITS (0x7 << 0)
173 #define AGCFR2_FSINT2_8000 (0) /* 8000 Hz */
174 #define AGCFR2_FSINT2_11025 (1) /* 11025 Hz */
175 #define AGCFR2_FSINT2_22050 (2) /* 22050 Hz */
176 #define AGCFR2_FSINT2_44100 (3) /* 44100 Hz */
177 #define AGCFR2_FSINT2_48000 (4) /* 48000 Hz */
178 #define AGCFR2_FSINT2_FSINT (7) /* based on AGCFR/FSINT */
182 #define AGCFR3_CP_TR_DMA (1 << 15) /* codec port transparent DMA (to audio DMAs) */
183 #define AGCFR3_BT_TR_DMA (1 << 14) /* BT transparent DMA (to BT UL write & DL read DMAs */
184 #define AGCFR3_MD_TR_DMA (1 << 13) /* modem transparent DMA (to modem UL write and DL read DMAs) */
185 #define AGCFR3_FSINT(val) ((val & 0xf) << 9) /* FSINT */
186 #define AGCFR3_FSINT_BITS (0xf << 9)
188 #define AGCFR3_FSINT_8000 (0) /* 8000 Hz */
189 #define AGCFR3_FSINT_11025 (1) /* 11025 Hz */
190 #define AGCFR3_FSINT_16000 (2) /* 16000 Hz */
191 #define AGCFR3_FSINT_22050 (3) /* 22050 Hz */
192 #define AGCFR3_FSINT_24000 (4) /* 24000 Hz */
193 #define AGCFR3_FSINT_32000 (5) /* 32000 Hz */
194 #define AGCFR3_FSINT_44100 (6) /* 44100 Hz */
195 #define AGCFR3_FSINT_48000 (7) /* 48000 Hz */
196 #define AGCFR3_FSINT_FSINT (15) /* based on AGCFR2/AGCFR */
199 #define AGCFR3_BT_CKSRC(val) ((val & 0x3) << 7) /* BT port clock selection */
200 #define AGCFR3_BT_CKSRC_BITS (0x3 << 7)
201 #define AGCFR3_MD_CKSRC(val) ((val & 0x3) << 5) /* modem port clock source */
202 #define AGCFR3_MD_CKSRC_BITS (0x3 << 5)
203 #define AGCFR3_AUD_CKSRC(val) ((val & 0x7) << 2) /* audio and codec port clock source */
204 #define AGCFR3_AUD_CKSRC_BITS (0x7 << 2)
205 #define AGCFR3_CLK12MINT_SEL (1 << 1) /* internal 12MHz clock source */
206 #define AGCFR3_MCLKINT_SEL (1 << 0) /* internal codec master clock source */
209 #define AMSCFR_K12 (1 << 11) /* K12 switch open/close */
210 #define AMSCFR_K11 (1 << 10)
211 #define AMSCFR_K10 (1 << 9)
212 #define AMSCFR_K9 (1 << 8)
213 #define AMSCFR_K8 (1 << 7)
214 #define AMSCFR_K7 (1 << 6)
215 #define AMSCFR_K6 (1 << 5)
216 #define AMSCFR_K5 (1 << 4)
217 #define AMSCFR_K4 (1 << 3)
218 #define AMSCFR_K3 (1 << 2)
219 #define AMSCFR_K2 (1 << 1)
220 #define AMSCFR_K1 (1 << 0)
223 #define AMVCTR_GWO_BITS (0xff << 8)
224 #define AMVCTR_GWO(val) ((val & 0xff) << 8) /* Gain on write DMA operation */
225 #define AMVCTR_GRO_BITS (0xff << 0)
226 #define AMVCTR_GRO(val) ((val & 0xff) << 0) /* Gain on read DMA operation */
229 #define AM1VCTR_MUTE (1 << 15) /* mute/no mute on mixer output */
230 #define AM1VCTR_GINB(val) ((val & 0x7f) << 8) /* gain on input B */
231 #define AM1VCTR_GINB_BITS (0x7f << 8)
232 #define AM1VCTR_GINA(val) ((val & 0x7f) << 0) /* gain on input A */
233 #define AM1VCTR_GINA_BITS (0x7f << 0)
236 #define AM2VCTR_MUTE (1 << 15) /* mute/no mute on mixer output */
237 #define AM2VCTR_GINB(val) ((val & 0x7f) << 8) /* gain on input B */
238 #define AM2VCTR_GINB_BITS (0x7f << 8)
239 #define AM2VCTR_GINA(val) ((val & 0x7f) << 0) /* gain on input A */
240 #define AM2VCTR_GINA_BITS (0x7f << 0)
243 #define AM3VCTR_MUTE (1 << 15) /* mute/no mute */
244 #define AM3VCTR_GINB(val) ((val & 0x7f) << 8) /* gain on input B */
245 #define AM3VCTR_GINB_BITS (0x7f << 8)
246 #define AM3VCTR_GINA(val) ((val & 0x7f) << 0) /* gain on input A */
247 #define AM3VCTR_GINA_BITS (0x7f << 0)
250 #define ASTCTR_ATT(val) ((val & 0x7f) << 1) /* Attenuation of side tone */
251 #define ASTCTR_ATT_BITS (0x7f << 1)
252 #define ASTCTR_ATTEN (1 << 0) /* side tone enabled/disabled */
255 /* internal structure of the EAC driver */
259 struct platform_device * pdev;
260 struct eac_platform_data * pdata;
261 struct snd_card * card;
264 struct eac_codec * codec;
266 unsigned clocks_enabled:1;
269 static char *id = SNDRV_DEFAULT_STR1;
270 module_param(id, charp, 0444);
271 MODULE_PARM_DESC(id, "ID string for OMAP24xx EAC");
274 #define MOD_REG_BIT(val, mask, set) do { \
281 static inline void eac_write_reg(struct omap_eac *eac, int idx, u16 val)
283 __raw_writew(val, eac->base + idx);
286 static inline u16 eac_read_reg(struct omap_eac *eac, int idx)
288 return __raw_readw(eac->base + idx);
291 static int eac_get_clocks(struct omap_eac *eac)
293 eac->ick = clk_get(NULL, "eac_ick");
294 if (IS_ERR(eac->ick)) {
295 dev_err(&eac->pdev->dev, "Could not get eac_ick");
299 eac->fck = clk_get(NULL, "eac_fck");
300 if (IS_ERR(eac->fck)) {
301 dev_err(&eac->pdev->dev, "Could not get eac_fck");
309 static void eac_put_clocks(struct omap_eac *eac)
315 static int eac_enable_clocks(struct omap_eac *eac)
319 if (eac->clocks_enabled)
322 if (eac->pdata != NULL && eac->pdata->enable_ext_clocks != NULL) {
323 if ((err = eac->pdata->enable_ext_clocks(&eac->pdev->dev)) != 0)
326 clk_enable(eac->ick);
327 clk_enable(eac->fck);
328 eac->clocks_enabled = 1;
333 static void eac_disable_clocks(struct omap_eac *eac)
335 if (!eac->clocks_enabled)
337 eac->clocks_enabled = 0;
339 clk_disable(eac->fck);
340 clk_disable(eac->ick);
341 if (eac->pdata != NULL && eac->pdata->disable_ext_clocks != NULL)
342 eac->pdata->disable_ext_clocks(&eac->pdev->dev);
345 static int eac_reset(struct omap_eac *eac)
349 /* step 1 (see TRM) */
350 /* first, let's reset the EAC */
351 eac_write_reg(eac, EAC_SYSCONFIG, 0x2);
352 /* step 2 (see TRM) */
353 eac_write_reg(eac, EAC_AGCTR, AGCTR_MCLK_EN | AGCTR_AUDEN);
354 /* step 3 (see TRM) */
355 /* wait until reset done */
357 while (!(eac_read_reg(eac, EAC_SYSSTATUS) & 1)) {
366 static int eac_calc_agcfr3_fsint(int rate)
371 fsint = AGCFR3_FSINT_48000;
372 else if (rate >= 44100)
373 fsint = AGCFR3_FSINT_44100;
374 else if (rate >= 32000)
375 fsint = AGCFR3_FSINT_32000;
376 else if (rate >= 24000)
377 fsint = AGCFR3_FSINT_24000;
378 else if (rate >= 22050)
379 fsint = AGCFR3_FSINT_22050;
380 else if (rate >= 16000)
381 fsint = AGCFR3_FSINT_16000;
382 else if (rate >= 11025)
383 fsint = AGCFR3_FSINT_11025;
385 fsint = AGCFR3_FSINT_8000;
390 static int eac_configure_pcm(struct omap_eac *eac, struct eac_codec *conf)
392 dev_err(&eac->pdev->dev,
393 "EAC codec port configuration for PCM not implemented\n");
398 static int eac_configure_ac97(struct omap_eac *eac, struct eac_codec *conf)
400 dev_err(&eac->pdev->dev,
401 "EAC codec port configuration for AC97 not implemented\n");
406 static int eac_configure_i2s(struct omap_eac *eac, struct eac_codec *conf)
408 u16 cpcfr1, cpcfr2, cpcfr3, cpcfr4;
410 cpcfr1 = eac_read_reg(eac, EAC_CPCFR1);
411 cpcfr2 = eac_read_reg(eac, EAC_CPCFR2);
412 cpcfr3 = eac_read_reg(eac, EAC_CPCFR3);
413 cpcfr4 = eac_read_reg(eac, EAC_CPCFR4);
415 cpcfr1 &= ~(CPCFR1_MODE_BITS | CPCFR1_MTSL_BITS);
416 cpcfr1 |= CPCFR1_MTSL(1); /* 2 timeslots per frame (I2S default) */
418 /* audio time slot configuration for I2S mode */
419 cpcfr2 &= ~(CPCFR2_TSLL_BITS | CPCFR2_BPTSL_BITS | CPCFR2_TSLOL_BITS);
420 cpcfr2 |= CPCFR2_TSLOL(0); /* time slot 0 length same as TSLL */
421 cpcfr2 |= CPCFR2_BPTSL(1); /* 16 data bits per time slot */
422 cpcfr2 |= CPCFR2_TSLL(1); /* time slot length 16 serial clock cycles */
424 /* I2S link configuration */
425 MOD_REG_BIT(cpcfr3, CPCFR3_DDLY,
426 conf->codec_conf.i2s.sync_delay_enable); /* 0/1 clk delay */
427 /* data serial output enabled during nonvalid audio frames, clock
428 * polarity = falling edge, CSYNC lenght equal to time slot0 length */
429 MOD_REG_BIT(cpcfr3, CPCFR3_TRSEN, 1);
430 MOD_REG_BIT(cpcfr3, CPCFR3_CLKBP, 1);
431 MOD_REG_BIT(cpcfr3, CPCFR3_CSYNCL, 1);
433 cpcfr4 &= ~(CPCFR4_DIVB_BITS | CPCFR4_ATSL_BITS);
434 cpcfr4 |= CPCFR4_DIVB(7); /* CP_SCLK = MCLK / 8 */
436 /* configuration for normal I2S or polarity-changed I2S */
437 if (!conf->codec_conf.i2s.polarity_changed_mode) {
438 cpcfr1 |= CPCFR1_MODE(4); /* I2S mode */
439 MOD_REG_BIT(cpcfr3, CPCFR3_CSYNCP, 0); /* CP_SYNC active low */
440 /* audio time slots configuration for I2S */
441 cpcfr4 |= CPCFR4_ATSL(0);
443 cpcfr1 |= CPCFR1_MODE(1); /* PCM mode/polarity-changed I2S */
444 MOD_REG_BIT(cpcfr3, CPCFR3_CSYNCP, 1); /* CP_SYNC active
446 /* audio time slots configuration for polarity-changed I2S */
447 cpcfr4 |= CPCFR4_ATSL(0xf);
450 /* master/slave configuration */
451 if (conf->codec_mode == EAC_CODEC_I2S_MASTER) {
452 /* EAC is master. Set CP_SCLK and CP_SYNC as outputs */
453 MOD_REG_BIT(cpcfr3, CPCFR3_CSCLKD, 0);
454 MOD_REG_BIT(cpcfr3, CPCFR3_CSYNCD, 0);
456 /* EAC is slave. Set CP_SCLK and CP_SYNC as inputs */
457 MOD_REG_BIT(cpcfr3, CPCFR3_CSCLKD, 1);
458 MOD_REG_BIT(cpcfr3, CPCFR3_CSYNCD, 1);
461 eac_write_reg(eac, EAC_CPCFR1, cpcfr1);
462 eac_write_reg(eac, EAC_CPCFR2, cpcfr2);
463 eac_write_reg(eac, EAC_CPCFR3, cpcfr3);
464 eac_write_reg(eac, EAC_CPCFR4, cpcfr4);
469 static int eac_codec_port_init(struct omap_eac *eac, struct eac_codec *conf)
471 u16 agcfr, agcfr2, agcfr3, agctr;
475 /* use internal MCLK gating before doing full configuration for it.
476 * Partial or misconfigured MCLK will cause that access to some of the
477 * EAC registers causes "external abort on linefetch". Same happens
478 * also when using external clock as a MCLK source and if that clock is
479 * either missing or not having a right rate (e.g. half of it) */
480 agcfr3 = eac_read_reg(eac, EAC_AGCFR3);
481 MOD_REG_BIT(agcfr3, AGCFR3_MCLKINT_SEL, 1); /* 96 Mhz / 8.5 */
482 eac_write_reg(eac, EAC_AGCFR3, agcfr3);
484 /* disable codec port, enable access to config registers */
485 cpctl = eac_read_reg(eac, EAC_CPTCTL);
486 MOD_REG_BIT(cpctl, CPTCTL_CPEN, 0);
487 eac_write_reg(eac, EAC_CPTCTL, cpctl);
489 agcfr = eac_read_reg(eac, EAC_AGCFR);
490 agctr = eac_read_reg(eac, EAC_AGCTR);
491 agcfr2 = eac_read_reg(eac, EAC_AGCFR2);
493 /* MCLK source and frequency configuration */
494 MOD_REG_BIT(agcfr, AGCFR_MCLK, 0);
495 switch (conf->mclk_src) {
496 case EAC_MCLK_EXT_2x11289600:
497 MOD_REG_BIT(agcfr, AGCFR_MCLK, 1); /* div by 2 path */
498 MOD_REG_BIT(agcfr, AGCFR_MCLK_OUT, 1); /* div by 2 */
499 case EAC_MCLK_EXT_11289600:
500 MOD_REG_BIT(agcfr, AGCFR_MCLK, 1);
501 MOD_REG_BIT(agcfr2, AGCFR2_I2S_N44K_48K, 0); /* 44.1 kHz */
502 MOD_REG_BIT(agcfr2, AGCFR2_MCLK_I2S_N11M_12M, 0); /* 11.2896 */
503 MOD_REG_BIT(agcfr3, AGCFR3_MCLKINT_SEL, 0);
506 case EAC_MCLK_EXT_2x12288000:
507 MOD_REG_BIT(agcfr, AGCFR_MCLK, 1); /* div by 2 path */
508 MOD_REG_BIT(agcfr, AGCFR_MCLK_OUT, 1); /* div by 2 */
509 case EAC_MCLK_EXT_12288000:
510 MOD_REG_BIT(agcfr2, AGCFR2_I2S_N44K_48K, 1); /* 48 kHz */
511 MOD_REG_BIT(agcfr2, AGCFR2_MCLK_I2S_N11M_12M, 1); /* 12.288 */
512 MOD_REG_BIT(agcfr3, AGCFR3_MCLKINT_SEL, 0);
516 /* internal MCLK gating */
519 MOD_REG_BIT(agctr, AGCTR_MCLK_EN, 1);
520 MOD_REG_BIT(agctr, AGCTR_OSCMCLK_EN, 1); /* oscillator enabled? */
521 /* use MCLK just configured above as audio & codec port clock source */
522 agcfr3 &= ~AGCFR3_AUD_CKSRC_BITS;
523 agcfr3 |= AGCFR3_AUD_CKSRC(0);
525 /* audio data format */
526 MOD_REG_BIT(agcfr, AGCFR_MN_ST, 1); /* stereo file */
527 MOD_REG_BIT(agcfr, AGCFR_B8_16, 1); /* 16 bit audio file */
528 MOD_REG_BIT(agcfr, AGCFR_LI_BI, 0); /* little endian stream */
530 /* there are FSINT configuration bits in AGCFR, AGCFR2 and AGCFR3
531 * registers but it seems that it is just enough to set in AGCFR3
533 agcfr3 &= ~AGCFR3_FSINT_BITS;
534 agcfr3 |= AGCFR3_FSINT(eac_calc_agcfr3_fsint(conf->default_rate));
536 /* transparent DMA enable bits */
537 MOD_REG_BIT(agcfr3, AGCFR3_MD_TR_DMA, 1); /* modem */
538 MOD_REG_BIT(agcfr3, AGCFR3_BT_TR_DMA, 1); /* BT */
539 if (conf->codec_mode != EAC_CODEC_I2S_SLAVE)
540 MOD_REG_BIT(agcfr3, AGCFR3_CP_TR_DMA, 0);
542 MOD_REG_BIT(agcfr3, AGCFR3_CP_TR_DMA, 1);
544 /* step 4 (see TRM) */
545 eac_write_reg(eac, EAC_AGCFR3, agcfr3);
546 /* pre-write AGCTR now (finally in step 10) in order to get MCLK
547 * settings effective (especially when using external MCLK) */
548 eac_write_reg(eac, EAC_AGCTR, agctr);
549 eac_write_reg(eac, EAC_AGCFR2, agcfr2);
551 /* step 5 (see TRM) */
552 eac_write_reg(eac, EAC_AGCFR, agcfr);
554 /* step 6 (see TRM) */
555 /* wait until audio reset done */
557 while (!(eac_read_reg(eac, EAC_SYSSTATUS) & (1 << 3))) {
563 /* step 7 (see TRM) */
564 reg = eac_read_reg(eac, EAC_AMSCFR);
565 MOD_REG_BIT(reg, AMSCFR_K1, 1); /* K1 switch closed */
566 MOD_REG_BIT(reg, AMSCFR_K5, 1); /* K5 switch closed */
567 MOD_REG_BIT(reg, AMSCFR_K2, 0); /* K2 switch open */
568 MOD_REG_BIT(reg, AMSCFR_K6, 0); /* K6 switch open */
569 eac_write_reg(eac, EAC_AMSCFR, reg);
571 /* step 8 (see TRM) */
572 switch (conf->codec_mode) {
574 err = eac_configure_pcm(eac, conf);
577 err = eac_configure_ac97(eac, conf);
580 err = eac_configure_i2s(eac, conf);
584 /* step 9 (see TRM) */
585 MOD_REG_BIT(cpctl, CPTCTL_CPEN, 1); /* codec port enable */
586 MOD_REG_BIT(cpctl, CPTCTL_RXIE, 1); /* receive int enable */
587 MOD_REG_BIT(cpctl, CPTCTL_TXIE, 1); /* transmit int enable */
588 eac_write_reg(eac, EAC_CPTCTL, cpctl);
590 /* step 10 (see TRM) */
591 /* enable playing & recording */
592 MOD_REG_BIT(agctr, AGCTR_DMAREN, 1); /* playing enabled (DMA R) */
593 MOD_REG_BIT(agctr, AGCTR_DMAWEN, 1); /* recording enabled (DMA W) */
594 MOD_REG_BIT(agctr, AGCTR_AUDEN, 1); /* audio processing enabled */
595 eac_write_reg(eac, EAC_AGCTR, agctr);
597 /* audio mixer1, no mute on mixer output, gain = 0 dB */
598 reg = eac_read_reg(eac, EAC_AM1VCTR);
599 MOD_REG_BIT(reg, AM1VCTR_MUTE, 0);
600 reg = ((reg & ~AM1VCTR_GINB_BITS) | (AM1VCTR_GINB(0x67)));
601 eac_write_reg(eac, EAC_AM1VCTR, reg);
603 /* audio mixer3, no mute on mixer output, gain = 0 dB */
604 reg = eac_read_reg(eac, EAC_AM3VCTR);
605 MOD_REG_BIT(reg, AM3VCTR_MUTE, 0);
606 reg = ((reg & ~AM3VCTR_GINB_BITS) | (AM3VCTR_GINB(0x67)));
607 eac_write_reg(eac, EAC_AM3VCTR, reg);
609 /* audio side tone disabled */
610 eac_write_reg(eac, EAC_ASTCTR, 0x0);
615 int eac_set_mode(struct device *dev, int play, int rec)
617 struct omap_eac *eac = dev_get_drvdata(dev);
620 printk(KERN_DEBUG "EAC mode: play %s, rec %s\n",
621 play ? "enabled" : "disabled",
622 rec ? "enabled" : "disabled");
625 mutex_lock(&eac->mutex);
627 /* activate clocks */
628 eac_enable_clocks(eac);
631 if (eac->codec != NULL && eac->codec->set_power != NULL)
632 eac->codec->set_power(eac->codec->private_data,
636 if (eac->codec != NULL && eac->codec->set_power != NULL)
637 eac->codec->set_power(eac->codec->private_data, 0, 0);
639 /* de-activate clocks */
640 eac_disable_clocks(eac);
642 mutex_unlock(&eac->mutex);
647 int eac_register_codec(struct device *dev, struct eac_codec *codec)
649 struct omap_eac *eac = dev_get_drvdata(dev);
650 struct snd_card *card = eac->card;
653 BUG_ON(eac->codec != NULL);
655 mutex_lock(&eac->mutex);
657 eac_enable_clocks(eac);
658 err = eac_codec_port_init(eac, codec);
659 eac_disable_clocks(eac);
660 mutex_unlock(&eac->mutex);
664 /* register mixer controls implemented by a codec driver */
665 if (codec->register_controls != NULL) {
666 err = codec->register_controls(codec->private_data, card);
671 if (codec->short_name != NULL) {
672 sprintf(card->longname, "%s with codec %s", card->shortname,
674 strcpy(card->mixername, codec->short_name);
677 err = snd_card_register(card);
681 void eac_unregister_codec(struct device *dev)
683 struct omap_eac *eac = dev_get_drvdata(dev);
685 BUG_ON(eac->codec == NULL);
686 eac_set_mode(dev, 0, 0);
687 snd_card_disconnect(eac->card);
691 static int __devinit eac_probe(struct platform_device *pdev)
693 struct eac_platform_data *pdata = pdev->dev.platform_data;
694 struct snd_card *card;
695 struct omap_eac *eac;
696 struct resource *res;
699 eac = kzalloc(sizeof(*eac), GFP_KERNEL);
703 mutex_init(&eac->mutex);
705 platform_set_drvdata(pdev, eac);
706 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
711 eac->base = (void __iomem *)io_p2v(res->start);
714 /* pre-initialize EAC hw */
715 err = eac_get_clocks(eac);
718 err = eac_enable_clocks(eac);
722 err = eac_reset(eac);
726 dev_info(&pdev->dev, "EAC version: %d.%d\n",
727 eac_read_reg(eac, EAC_VERSION) >> 4,
728 eac_read_reg(eac, EAC_VERSION) & 0x0f);
729 eac_disable_clocks(eac);
731 /* create soundcard instance */
732 card = snd_card_new(-1, id, THIS_MODULE, 0);
738 strcpy(card->driver, "EAC");
739 strcpy(card->shortname, "OMAP24xx EAC");
741 sprintf(card->longname, "%s", card->shortname);
742 strcpy(card->mixername, "EAC Mixer");
744 if (eac->pdata->init) {
745 err = eac->pdata->init(&pdev->dev);
747 printk("init %d\n", err);
757 eac_disable_clocks(eac);
765 static int __devexit eac_remove(struct platform_device *pdev)
767 struct omap_eac *eac = platform_get_drvdata(pdev);
768 struct snd_card *card = eac->card;
772 eac_disable_clocks(eac);
775 platform_set_drvdata(pdev, NULL);
780 static struct platform_driver eac_driver = {
782 .name = "omap24xx-eac",
783 .bus = &platform_bus_type,
786 .remove = eac_remove,
789 int __init eac_init(void)
791 return platform_driver_register(&eac_driver);
794 void __exit eac_exit(void)
796 platform_driver_unregister(&eac_driver);
799 module_init(eac_init);
800 module_exit(eac_exit);
801 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
802 MODULE_LICENSE("GPL");