2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <asm/atomic.h>
43 MLX4_FLAG_MSI_X = 1 << 0,
44 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
52 MLX4_BOARD_ID_LEN = 64
56 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
57 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
58 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
59 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
60 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
61 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
62 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
63 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
64 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
65 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
66 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
67 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
68 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
72 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
73 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
74 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
75 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
76 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
80 MLX4_EVENT_TYPE_COMP = 0x00,
81 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
82 MLX4_EVENT_TYPE_COMM_EST = 0x02,
83 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
84 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
85 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
86 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
87 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
88 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
89 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
90 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
91 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
92 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
93 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
94 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
95 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
96 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
97 MLX4_EVENT_TYPE_CMD = 0x0a
101 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
102 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
106 MLX4_PERM_LOCAL_READ = 1 << 10,
107 MLX4_PERM_LOCAL_WRITE = 1 << 11,
108 MLX4_PERM_REMOTE_READ = 1 << 12,
109 MLX4_PERM_REMOTE_WRITE = 1 << 13,
110 MLX4_PERM_ATOMIC = 1 << 14
114 MLX4_OPCODE_NOP = 0x00,
115 MLX4_OPCODE_SEND_INVAL = 0x01,
116 MLX4_OPCODE_RDMA_WRITE = 0x08,
117 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
118 MLX4_OPCODE_SEND = 0x0a,
119 MLX4_OPCODE_SEND_IMM = 0x0b,
120 MLX4_OPCODE_LSO = 0x0e,
121 MLX4_OPCODE_RDMA_READ = 0x10,
122 MLX4_OPCODE_ATOMIC_CS = 0x11,
123 MLX4_OPCODE_ATOMIC_FA = 0x12,
124 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
125 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
126 MLX4_OPCODE_BIND_MW = 0x18,
127 MLX4_OPCODE_FMR = 0x19,
128 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
129 MLX4_OPCODE_CONFIG_CMD = 0x1f,
131 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
132 MLX4_RECV_OPCODE_SEND = 0x01,
133 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
134 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
136 MLX4_CQE_OPCODE_ERROR = 0x1e,
137 MLX4_CQE_OPCODE_RESIZE = 0x16,
141 MLX4_STAT_RATE_OFFSET = 5
145 MLX4_MTT_FLAG_PRESENT = 1
148 enum mlx4_qp_region {
149 MLX4_QP_REGION_FW = 0,
150 MLX4_QP_REGION_ETH_ADDR,
151 MLX4_QP_REGION_FC_ADDR,
152 MLX4_QP_REGION_FC_EXCH,
156 enum mlx4_special_vlan_idx {
157 MLX4_NO_VLAN_IDX = 0,
163 MLX4_NUM_FEXCH = 64 * 1024,
166 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
168 return (major << 32) | (minor << 16) | subminor;
174 int vl_cap[MLX4_MAX_PORTS + 1];
175 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
176 u64 def_mac[MLX4_MAX_PORTS + 1];
177 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
178 int gid_table_len[MLX4_MAX_PORTS + 1];
179 int pkey_table_len[MLX4_MAX_PORTS + 1];
180 int local_ca_ack_delay;
183 int bf_regs_per_page;
190 int max_qp_init_rdma;
191 int max_qp_dest_rdma;
204 int fmr_reserved_mtts;
220 u16 stat_rate_support;
221 u8 port_width_cap[MLX4_MAX_PORTS + 1];
223 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
225 int reserved_qps_base[MLX4_NUM_QP_REGION];
231 struct mlx4_buf_list {
237 struct mlx4_buf_list direct;
238 struct mlx4_buf_list *page_list;
251 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
254 struct mlx4_db_pgdir {
255 struct list_head list;
256 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
257 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
258 unsigned long *bits[2];
263 struct mlx4_ib_user_db_page;
268 struct mlx4_db_pgdir *pgdir;
269 struct mlx4_ib_user_db_page *user_page;
276 struct mlx4_hwq_resources {
294 struct mlx4_mpt_entry *mpt;
296 dma_addr_t dma_handle;
309 void (*comp) (struct mlx4_cq *);
310 void (*event) (struct mlx4_cq *, enum mlx4_event);
312 struct mlx4_uar *uar;
323 struct completion free;
327 void (*event) (struct mlx4_qp *, enum mlx4_event);
332 struct completion free;
336 void (*event) (struct mlx4_srq *, enum mlx4_event);
344 struct completion free;
356 __be32 sl_tclass_flowlabel;
361 struct pci_dev *pdev;
363 struct mlx4_caps caps;
364 struct radix_tree_root qp_table_tree;
366 char board_id[MLX4_BOARD_ID_LEN];
369 struct mlx4_init_port_param {
383 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
384 struct mlx4_buf *buf);
385 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
386 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
388 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
389 return buf->direct.buf + offset;
391 return buf->page_list[offset >> PAGE_SHIFT].buf +
392 (offset & (PAGE_SIZE - 1));
395 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
396 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
398 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
399 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
401 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
402 struct mlx4_mtt *mtt);
403 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
404 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
406 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
407 int npages, int page_shift, struct mlx4_mr *mr);
408 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
409 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
410 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
411 int start_index, int npages, u64 *page_list);
412 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
413 struct mlx4_buf *buf);
415 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
416 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
418 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
419 int size, int max_direct);
420 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
423 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
424 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
426 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
428 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
429 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
431 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
432 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
434 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
435 u64 db_rec, struct mlx4_srq *srq);
436 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
437 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
438 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
440 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
441 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
443 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
444 int block_mcast_loopback);
445 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
447 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
448 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
450 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
451 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
453 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
454 int npages, u64 iova, u32 *lkey, u32 *rkey);
455 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
456 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
457 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
458 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
459 u32 *lkey, u32 *rkey);
460 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
461 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
463 #endif /* MLX4_DEVICE_H */