2 * include/linux/mfd/asic3.h
4 * Compaq ASIC3 headers.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2007 OpendHand.
17 #include <linux/types.h>
19 struct asic3_platform_data {
28 } gpio_a, gpio_b, gpio_c, gpio_d;
30 unsigned int bus_shift;
32 unsigned int irq_base;
34 unsigned int gpio_base;
37 #define ASIC3_NUM_GPIO_BANKS 4
38 #define ASIC3_GPIOS_PER_BANK 16
39 #define ASIC3_NUM_GPIOS 64
40 #define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
42 #define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
44 #define ASIC3_GPIO_BANK_A 0
45 #define ASIC3_GPIO_BANK_B 1
46 #define ASIC3_GPIO_BANK_C 2
47 #define ASIC3_GPIO_BANK_D 3
49 #define ASIC3_GPIO(bank, gpio) \
50 ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
51 #define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
52 /* All offsets below are specified with this address bus shift */
53 #define ASIC3_DEFAULT_ADDR_SHIFT 2
55 #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg)
56 #define ASIC3_GPIO_OFFSET(base, reg) \
57 (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg)
59 #define ASIC3_GPIO_A_Base 0x0000
60 #define ASIC3_GPIO_B_Base 0x0100
61 #define ASIC3_GPIO_C_Base 0x0200
62 #define ASIC3_GPIO_D_Base 0x0300
64 #define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
65 #define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
66 (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
67 #define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
68 #define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_Base + (((gpio) >> 4) * 0x0100))
69 #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_Base + ((bank) * 0x100))
71 #define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */
72 #define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */
73 #define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */
74 #define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */
75 #define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */
76 #define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */
77 #define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */
78 #define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */
79 #define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */
80 #define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */
81 #define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */
82 #define ASIC3_GPIO_SleepConf 0x2c /*
83 * R/W bit 1: autosleep
84 * 0: disable gposlpout in normal mode,
85 * enable gposlpout in sleep mode.
87 #define ASIC3_GPIO_Status 0x30 /* R Pin status */
89 #define ASIC3_SPI_Base 0x0400
90 #define ASIC3_SPI_Control 0x0000
91 #define ASIC3_SPI_TxData 0x0004
92 #define ASIC3_SPI_RxData 0x0008
93 #define ASIC3_SPI_Int 0x000c
94 #define ASIC3_SPI_Status 0x0010
96 #define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */
98 #define ASIC3_PWM_0_Base 0x0500
99 #define ASIC3_PWM_1_Base 0x0600
100 #define ASIC3_PWM_TimeBase 0x0000
101 #define ASIC3_PWM_PeriodTime 0x0004
102 #define ASIC3_PWM_DutyTime 0x0008
104 #define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
105 #define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
107 #define ASIC3_LED_0_Base 0x0700
108 #define ASIC3_LED_1_Base 0x0800
109 #define ASIC3_LED_2_Base 0x0900
110 #define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */
111 #define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */
112 #define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */
113 #define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */
115 /* LED TimeBase bits - match ASIC2 */
116 #define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */
117 /* Note: max = 5 on hx4700 */
118 /* 0: maximum time base */
119 /* 1: maximum time base / 2 */
120 /* n: maximum time base / 2^n */
122 #define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */
123 #define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
124 #define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
126 #define ASIC3_CLOCK_Base 0x0A00
127 #define ASIC3_CLOCK_CDEX 0x00
128 #define ASIC3_CLOCK_SEL 0x04
130 #define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */
131 #define CLOCK_CDEX_SOURCE0 (1 << 0)
132 #define CLOCK_CDEX_SOURCE1 (1 << 1)
133 #define CLOCK_CDEX_SPI (1 << 2)
134 #define CLOCK_CDEX_OWM (1 << 3)
135 #define CLOCK_CDEX_PWM0 (1 << 4)
136 #define CLOCK_CDEX_PWM1 (1 << 5)
137 #define CLOCK_CDEX_LED0 (1 << 6)
138 #define CLOCK_CDEX_LED1 (1 << 7)
139 #define CLOCK_CDEX_LED2 (1 << 8)
141 /* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
142 #define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */
143 #define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */
144 #define CLOCK_CDEX_SMBUS (1 << 11)
145 #define CLOCK_CDEX_CONTROL_CX (1 << 12)
147 #define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */
148 #define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */
150 #define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */
151 #define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */
153 /* R/W: INT clock source control (32.768 kHz) */
154 #define CLOCK_SEL_CX (1 << 2)
157 #define ASIC3_INTR_Base 0x0B00
159 #define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */
160 #define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */
161 #define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */
162 #define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */
164 #define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
165 #define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
166 #define ASIC3_INTMASK_MASK0 (1 << 2)
167 #define ASIC3_INTMASK_MASK1 (1 << 3)
168 #define ASIC3_INTMASK_MASK2 (1 << 4)
169 #define ASIC3_INTMASK_MASK3 (1 << 5)
170 #define ASIC3_INTMASK_MASK4 (1 << 6)
171 #define ASIC3_INTMASK_MASK5 (1 << 7)
173 #define ASIC3_INTR_PERIPHERAL_A (1 << 0)
174 #define ASIC3_INTR_PERIPHERAL_B (1 << 1)
175 #define ASIC3_INTR_PERIPHERAL_C (1 << 2)
176 #define ASIC3_INTR_PERIPHERAL_D (1 << 3)
177 #define ASIC3_INTR_LED0 (1 << 4)
178 #define ASIC3_INTR_LED1 (1 << 5)
179 #define ASIC3_INTR_LED2 (1 << 6)
180 #define ASIC3_INTR_SPI (1 << 7)
181 #define ASIC3_INTR_SMBUS (1 << 8)
182 #define ASIC3_INTR_OWM (1 << 9)
184 #define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */
185 #define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */
188 /* Basic control of the SD ASIC */
189 #define ASIC3_SDHWCTRL_Base 0x0E00
190 #define ASIC3_SDHWCTRL_SDConf 0x00
192 #define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
193 #define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
194 #define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */
195 #define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */
197 /* SD card write protection: 0=high */
198 #define ASIC3_SDHWCTRL_LEVWP (1 << 4)
199 #define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */
201 /* SD card power supply ctrl 1=enable */
202 #define ASIC3_SDHWCTRL_SDPWR (1 << 6)
204 #define ASIC3_EXTCF_Base 0x1100
206 #define ASIC3_EXTCF_Select 0x00
207 #define ASIC3_EXTCF_Reset 0x04
209 #define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
210 #define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
211 #define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */
212 #define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */
213 #define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */
214 #define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */
215 #define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */
216 #define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */
217 #define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */
218 #define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */
219 #define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */
220 #define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */
221 #define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14)
222 #define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
224 /*********************************************
225 * The Onewire interface registers
233 *********************************************/
235 #define ASIC3_OWM_Base 0xC00
237 #define ASIC3_OWM_CMD 0x00
238 #define ASIC3_OWM_DAT 0x04
239 #define ASIC3_OWM_INTR 0x08
240 #define ASIC3_OWM_INTEN 0x0C
241 #define ASIC3_OWM_CLKDIV 0x10
243 #define ASIC3_OWM_CMD_ONEWR (1 << 0)
244 #define ASIC3_OWM_CMD_SRA (1 << 1)
245 #define ASIC3_OWM_CMD_DQO (1 << 2)
246 #define ASIC3_OWM_CMD_DQI (1 << 3)
248 #define ASIC3_OWM_INTR_PD (1 << 0)
249 #define ASIC3_OWM_INTR_PDR (1 << 1)
250 #define ASIC3_OWM_INTR_TBE (1 << 2)
251 #define ASIC3_OWM_INTR_TEMP (1 << 3)
252 #define ASIC3_OWM_INTR_RBF (1 << 4)
254 #define ASIC3_OWM_INTEN_EPD (1 << 0)
255 #define ASIC3_OWM_INTEN_IAS (1 << 1)
256 #define ASIC3_OWM_INTEN_ETBE (1 << 2)
257 #define ASIC3_OWM_INTEN_ETMT (1 << 3)
258 #define ASIC3_OWM_INTEN_ERBF (1 << 4)
260 #define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */
261 #define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */
264 /*****************************************************************************
265 * The SD configuration registers are at a completely different location
266 * in memory. They are divided into three sets of registers:
268 * SD_CONFIG Core configuration register
269 * SD_CTRL Control registers for SD operations
270 * SDIO_CTRL Control registers for SDIO operations
272 *****************************************************************************/
273 #define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */
275 #define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */
277 /* [0:8] SD Control Register Base Address */
278 #define ASIC3_SD_CONFIG_Addr0 0x20
280 /* [9:31] SD Control Register Base Address */
281 #define ASIC3_SD_CONFIG_Addr1 0x24
283 /* R/O: interrupt assigned to pin */
284 #define ASIC3_SD_CONFIG_IntPin 0x78
287 * Set to 0x1f to clock SD controller, 0 otherwise.
288 * At 0x82 - Gated Clock Ctrl
290 #define ASIC3_SD_CONFIG_ClkStop 0x80
292 /* Control clock of SD controller */
293 #define ASIC3_SD_CONFIG_ClockMode 0x84
294 #define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */
295 #define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */
297 /* auto power up after card inserted */
298 #define ASIC3_SD_CONFIG_SDHC_Power2 0x92
300 /* auto power down when card removed */
301 #define ASIC3_SD_CONFIG_SDHC_Power3 0x94
302 #define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98
303 #define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */
304 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */
305 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/
307 /* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
308 #define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8
309 #define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */
311 /* Bit 1: double buffer/single buffer */
312 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0
314 /* Memory access enable (set to 1 to access SD Controller) */
315 #define SD_CONFIG_COMMAND_MAE (1<<1)
317 #define SD_CONFIG_CLK_ENABLE_ALL 0x1f
319 #define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */
320 #define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */
322 /* two bits - number of cycles for card detection */
323 #define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3)
326 #define ASIC3_SD_CTRL_Base 0x1000
328 #define ASIC3_SD_CTRL_Cmd 0x00
329 #define ASIC3_SD_CTRL_Arg0 0x08
330 #define ASIC3_SD_CTRL_Arg1 0x0C
331 #define ASIC3_SD_CTRL_StopInternal 0x10
332 #define ASIC3_SD_CTRL_TransferSectorCount 0x14
333 #define ASIC3_SD_CTRL_Response0 0x18
334 #define ASIC3_SD_CTRL_Response1 0x1C
335 #define ASIC3_SD_CTRL_Response2 0x20
336 #define ASIC3_SD_CTRL_Response3 0x24
337 #define ASIC3_SD_CTRL_Response4 0x28
338 #define ASIC3_SD_CTRL_Response5 0x2C
339 #define ASIC3_SD_CTRL_Response6 0x30
340 #define ASIC3_SD_CTRL_Response7 0x34
341 #define ASIC3_SD_CTRL_CardStatus 0x38
342 #define ASIC3_SD_CTRL_BufferCtrl 0x3C
343 #define ASIC3_SD_CTRL_IntMaskCard 0x40
344 #define ASIC3_SD_CTRL_IntMaskBuffer 0x44
345 #define ASIC3_SD_CTRL_CardClockCtrl 0x48
346 #define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C
347 #define ASIC3_SD_CTRL_MemCardOptionSetup 0x50
348 #define ASIC3_SD_CTRL_ErrorStatus0 0x58
349 #define ASIC3_SD_CTRL_ErrorStatus1 0x5C
350 #define ASIC3_SD_CTRL_DataPort 0x60
351 #define ASIC3_SD_CTRL_TransactionCtrl 0x68
352 #define ASIC3_SD_CTRL_SoftwareReset 0x1C0
354 #define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0)
356 #define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8)
358 #define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15)
359 #define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8)
360 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7)
361 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6)
362 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5)
363 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4)
364 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3)
365 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2)
366 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1)
367 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0)
368 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0)
370 #define MEM_CARD_OPTION_REQUIRED 0x000e
371 #define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4)
372 #define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14)
373 #define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15)
374 #define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0
376 #define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f)
377 #define SD_CTRL_COMMAND_TYPE_CMD (0 << 6)
378 #define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6)
379 #define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6)
380 #define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8)
381 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8)
382 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8)
383 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8)
384 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8)
385 #define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11)
386 #define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12)
387 #define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12)
388 #define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13)
389 #define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14)
391 #define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0)
392 #define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8)
394 #define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0)
395 #define SD_CTRL_CARDSTATUS_RW_END (1 << 2)
396 #define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3)
397 #define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4)
398 #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5)
399 #define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7)
400 #define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8)
401 #define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9)
402 #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10)
404 #define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0)
405 #define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1)
406 #define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2)
407 #define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3)
408 #define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4)
409 #define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5)
410 #define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6)
411 #define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7)
412 #define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8)
413 #define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9)
414 #define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13)
415 #define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14)
416 #define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15)
418 #define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0)
419 #define SD_CTRL_INTMASKCARD_RW_END (1 << 2)
420 #define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3)
421 #define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4)
422 #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
423 #define SD_CTRL_INTMASKCARD_UNK6 (1 << 6)
424 #define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7)
425 #define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8)
426 #define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9)
427 #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
429 #define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0)
430 #define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1)
431 #define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2)
432 #define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3)
433 #define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4)
434 #define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5)
435 #define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6)
436 #define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7)
437 #define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8)
438 #define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9)
439 #define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13)
440 #define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14)
441 #define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15)
443 #define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0)
444 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
445 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3)
446 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4)
447 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5)
448 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8)
449 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9)
450 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10)
451 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11)
453 #define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0)
454 #define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4)
455 #define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5)
456 #define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6)
458 #define ASIC3_SDIO_CTRL_Base 0x1200
460 #define ASIC3_SDIO_CTRL_Cmd 0x00
461 #define ASIC3_SDIO_CTRL_CardPortSel 0x04
462 #define ASIC3_SDIO_CTRL_Arg0 0x08
463 #define ASIC3_SDIO_CTRL_Arg1 0x0C
464 #define ASIC3_SDIO_CTRL_TransferBlockCount 0x14
465 #define ASIC3_SDIO_CTRL_Response0 0x18
466 #define ASIC3_SDIO_CTRL_Response1 0x1C
467 #define ASIC3_SDIO_CTRL_Response2 0x20
468 #define ASIC3_SDIO_CTRL_Response3 0x24
469 #define ASIC3_SDIO_CTRL_Response4 0x28
470 #define ASIC3_SDIO_CTRL_Response5 0x2C
471 #define ASIC3_SDIO_CTRL_Response6 0x30
472 #define ASIC3_SDIO_CTRL_Response7 0x34
473 #define ASIC3_SDIO_CTRL_CardStatus 0x38
474 #define ASIC3_SDIO_CTRL_BufferCtrl 0x3C
475 #define ASIC3_SDIO_CTRL_IntMaskCard 0x40
476 #define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44
477 #define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C
478 #define ASIC3_SDIO_CTRL_CardOptionSetup 0x50
479 #define ASIC3_SDIO_CTRL_ErrorStatus0 0x54
480 #define ASIC3_SDIO_CTRL_ErrorStatus1 0x58
481 #define ASIC3_SDIO_CTRL_DataPort 0x60
482 #define ASIC3_SDIO_CTRL_TransactionCtrl 0x68
483 #define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C
484 #define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70
485 #define ASIC3_SDIO_CTRL_HostInformation 0x74
486 #define ASIC3_SDIO_CTRL_ErrorCtrl 0x78
487 #define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
488 #define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
490 #define ASIC3_MAP_SIZE 0x2000
492 #endif /* __ASIC3_H__ */