2 * include/linux/i2c/menelaus.h
4 * Functions to access Menelaus power management chip
7 #ifndef __ASM_ARCH_MENELAUS_H
8 #define __ASM_ARCH_MENELAUS_H
10 #define MENELAUS_I2C_ADDRESS 0x72
12 #define MENELAUS_REV 0x01
13 #define MENELAUS_VCORE_CTRL1 0x02
14 #define MENELAUS_VCORE_CTRL2 0x03
15 #define MENELAUS_VCORE_CTRL3 0x04
16 #define MENELAUS_VCORE_CTRL4 0x05
17 #define MENELAUS_VCORE_CTRL5 0x06
18 #define MENELAUS_DCDC_CTRL1 0x07
19 #define MENELAUS_DCDC_CTRL2 0x08
20 #define MENELAUS_DCDC_CTRL3 0x09
21 #define MENELAUS_LDO_CTRL1 0x0A
22 #define MENELAUS_LDO_CTRL2 0x0B
23 #define MENELAUS_LDO_CTRL3 0x0C
24 #define MENELAUS_LDO_CTRL4 0x0D
25 #define MENELAUS_LDO_CTRL5 0x0E
26 #define MENELAUS_LDO_CTRL6 0x0F
27 #define MENELAUS_LDO_CTRL7 0x10
28 #define MENELAUS_LDO_CTRL8 0x11
29 #define MENELAUS_SLEEP_CTRL1 0x12
30 #define MENELAUS_SLEEP_CTRL2 0x13
31 #define MENELAUS_DEVICE_OFF 0x14
32 #define MENELAUS_OSC_CTRL 0x15
33 #define MENELAUS_DETECT_CTRL 0x16
34 #define MENELAUS_INT_MASK1 0x17
35 #define MENELAUS_INT_MASK2 0x18
36 #define MENELAUS_INT_STATUS1 0x19
37 #define MENELAUS_INT_STATUS2 0x1A
38 #define MENELAUS_INT_ACK1 0x1B
39 #define MENELAUS_INT_ACK2 0x1C
40 #define MENELAUS_GPIO_CTRL 0x1D
41 #define MENELAUS_GPIO_IN 0x1E
42 #define MENELAUS_GPIO_OUT 0x1F
43 #define MENELAUS_BBSMS 0x20
44 #define MENELAUS_RTC_CTRL 0x21
45 #define MENELAUS_RTC_UPDATE 0x22
46 #define MENELAUS_RTC_SEC 0x23
47 #define MENELAUS_RTC_MIN 0x24
48 #define MENELAUS_RTC_HR 0x25
49 #define MENELAUS_RTC_DAY 0x26
50 #define MENELAUS_RTC_MON 0x27
51 #define MENELAUS_RTC_YR 0x28
52 #define MENELAUS_RTC_WKDAY 0x29
53 #define MENELAUS_RTC_AL_SEC 0x2A
54 #define MENELAUS_RTC_AL_MIN 0x2B
55 #define MENELAUS_RTC_AL_HR 0x2C
56 #define MENELAUS_RTC_AL_DAY 0x2D
57 #define MENELAUS_RTC_AL_MON 0x2E
58 #define MENELAUS_RTC_AL_YR 0x2F
59 #define MENELAUS_RTC_COMP_MSB 0x30
60 #define MENELAUS_RTC_COMP_LSB 0x31
61 #define MENELAUS_S1_PULL_EN 0x32
62 #define MENELAUS_S1_PULL_DIR 0x33
63 #define MENELAUS_S2_PULL_EN 0x34
64 #define MENELAUS_S2_PULL_DIR 0x35
65 #define MENELAUS_MCT_CTRL1 0x36
66 #define MENELAUS_MCT_CTRL2 0x37
67 #define MENELAUS_MCT_CTRL3 0x38
68 #define MENELAUS_MCT_PIN_ST 0x39
69 #define MENELAUS_DEBOUNCE1 0x3A
71 #define IH_MENELAUS_IRQS 12
72 #define MENELAUS_MMC_S1CD_IRQ 0 /* MMC slot 1 card change */
73 #define MENELAUS_MMC_S2CD_IRQ 1 /* MMC slot 2 card change */
74 #define MENELAUS_MMC_S1D1_IRQ 2 /* MMC DAT1 low in slot 1 */
75 #define MENELAUS_MMC_S2D1_IRQ 3 /* MMC DAT1 low in slot 2 */
76 #define MENELAUS_LOWBAT_IRQ 4 /* Low battery */
77 #define MENELAUS_HOTDIE_IRQ 5 /* Hot die detect */
78 #define MENELAUS_UVLO_IRQ 6 /* UVLO detect */
79 #define MENELAUS_TSHUT_IRQ 7 /* Thermal shutdown */
80 #define MENELAUS_RTCTMR_IRQ 8 /* RTC timer */
81 #define MENELAUS_RTCALM_IRQ 9 /* RTC alarm */
82 #define MENELAUS_RTCERR_IRQ 10 /* RTC error */
83 #define MENELAUS_PSHBTN_IRQ 11 /* Push button */
84 #define MENELAUS_RESERVED12_IRQ 12 /* Reserved */
85 #define MENELAUS_RESERVED13_IRQ 13 /* Reserved */
86 #define MENELAUS_RESERVED14_IRQ 14 /* Reserved */
87 #define MENELAUS_RESERVED15_IRQ 15 /* Reserved */
89 /* VCORE_CTRL1 register */
90 #define VCORE_CTRL1_BYP_COMP (1 << 5)
91 #define VCORE_CTRL1_HW_NSW (1 << 7)
93 /* GPIO_CTRL register */
94 #define GPIO_CTRL_SLOTSELEN (1 << 5)
95 #define GPIO_CTRL_SLPCTLEN (1 << 6)
96 #define GPIO1_DIR_INPUT (1 << 0)
97 #define GPIO2_DIR_INPUT (1 << 1)
98 #define GPIO3_DIR_INPUT (1 << 2)
100 /* MCT_CTRL1 register */
101 #define MCT_CTRL1_S1_CMD_OD (1 << 2)
102 #define MCT_CTRL1_S2_CMD_OD (1 << 3)
104 /* MCT_CTRL2 register */
105 #define MCT_CTRL2_VS2_SEL_D0 (1 << 0)
106 #define MCT_CTRL2_VS2_SEL_D1 (1 << 1)
107 #define MCT_CTRL2_S1CD_BUFEN (1 << 4)
108 #define MCT_CTRL2_S2CD_BUFEN (1 << 5)
109 #define MCT_CTRL2_S1CD_DBEN (1 << 6)
110 #define MCT_CTRL2_S2CD_BEN (1 << 7)
112 /* MCT_CTRL3 register */
113 #define MCT_CTRL3_SLOT1_EN (1 << 0)
114 #define MCT_CTRL3_SLOT2_EN (1 << 1)
115 #define MCT_CTRL3_S1_AUTO_EN (1 << 2)
116 #define MCT_CTRL3_S2_AUTO_EN (1 << 3)
118 /* MCT_PIN_ST register */
119 #define MCT_PIN_ST_S1_CD_ST (1 << 0)
120 #define MCT_PIN_ST_S2_CD_ST (1 << 1)
124 struct menelaus_platform_data {
125 int (*late_init)(struct device *dev);
128 extern int menelaus_register_mmc_callback(void (*callback)(void *data,
131 extern void menelaus_unregister_mmc_callback(void);
132 extern int menelaus_set_mmc_opendrain(int slot, int enable);
133 extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
134 extern int menelaus_enable_slot(int slot, int enable);
136 extern int menelaus_set_vmem(unsigned int mV);
137 extern int menelaus_set_vio(unsigned int mV);
138 extern int menelaus_set_vmmc(unsigned int mV);
139 extern int menelaus_set_vaux(unsigned int mV);
140 extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
141 extern int menelaus_set_slot_sel(int enable);
142 extern int menelaus_get_slot_pin_states(void);
143 extern int menelaus_set_vcore_sw(unsigned int mV);
144 extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
146 #define EN_VPLL_SLEEP (1 << 7)
147 #define EN_VMMC_SLEEP (1 << 6)
148 #define EN_VAUX_SLEEP (1 << 5)
149 #define EN_VIO_SLEEP (1 << 4)
150 #define EN_VMEM_SLEEP (1 << 3)
151 #define EN_DC3_SLEEP (1 << 2)
152 #define EN_DC2_SLEEP (1 << 1)
153 #define EN_VC_SLEEP (1 << 0)
155 extern int menelaus_set_regulator_sleep(int enable, u32 val);
157 #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
158 #define omap_has_menelaus() 1
160 #define omap_has_menelaus() 0