2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/kref.h>
27 #include <linux/completion.h>
28 #include <linux/rcupdate.h>
29 #include <linux/dma-mapping.h>
32 * enum dma_state - resource PNP/power management state
33 * @DMA_RESOURCE_SUSPEND: DMA device going into low power state
34 * @DMA_RESOURCE_RESUME: DMA device returning to full power
35 * @DMA_RESOURCE_AVAILABLE: DMA device available to the system
36 * @DMA_RESOURCE_REMOVED: DMA device removed from the system
41 DMA_RESOURCE_AVAILABLE,
46 * enum dma_state_client - state of the channel in the client
47 * @DMA_ACK: client would like to use, or was using this channel
48 * @DMA_DUP: client has already seen this channel, or is not using this channel
49 * @DMA_NAK: client does not want to see any more channels
51 enum dma_state_client {
58 * typedef dma_cookie_t - an opaque DMA cookie
60 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
62 typedef s32 dma_cookie_t;
64 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
67 * enum dma_status - DMA transaction status
68 * @DMA_SUCCESS: transaction completed successfully
69 * @DMA_IN_PROGRESS: transaction not yet processed
70 * @DMA_ERROR: transaction failed
79 * enum dma_transaction_type - DMA transaction types/indexes
81 enum dma_transaction_type {
94 /* last transaction type for creation of the capabilities mask */
95 #define DMA_TX_TYPE_END (DMA_INTERRUPT + 1)
98 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
101 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
104 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
105 * @refcount: local_t used for open-coded "bigref" counting
106 * @memcpy_count: transaction counter
107 * @bytes_transferred: byte counter
110 struct dma_chan_percpu {
113 unsigned long memcpy_count;
114 unsigned long bytes_transferred;
118 * struct dma_chan - devices supply DMA channels, clients use them
119 * @device: ptr to the dma device who supplies this channel, always !%NULL
120 * @cookie: last cookie value returned to client
121 * @chan_id: channel ID for sysfs
122 * @class_dev: class device for sysfs
123 * @refcount: kref, used in "bigref" slow-mode
124 * @slow_ref: indicates that the DMA channel is free
125 * @rcu: the DMA channel's RCU head
126 * @device_node: used to add this to the device chan list
127 * @local: per-cpu pointer to a struct dma_chan_percpu
130 struct dma_device *device;
137 struct kref refcount;
141 struct list_head device_node;
142 struct dma_chan_percpu *local;
145 #define to_dma_chan(p) container_of(p, struct dma_chan, dev)
147 void dma_chan_cleanup(struct kref *kref);
149 static inline void dma_chan_get(struct dma_chan *chan)
151 if (unlikely(chan->slow_ref))
152 kref_get(&chan->refcount);
154 local_inc(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
159 static inline void dma_chan_put(struct dma_chan *chan)
161 if (unlikely(chan->slow_ref))
162 kref_put(&chan->refcount, dma_chan_cleanup);
164 local_dec(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
170 * typedef dma_event_callback - function pointer to a DMA event callback
171 * For each channel added to the system this routine is called for each client.
172 * If the client would like to use the channel it returns '1' to signal (ack)
173 * the dmaengine core to take out a reference on the channel and its
174 * corresponding device. A client must not 'ack' an available channel more
175 * than once. When a channel is removed all clients are notified. If a client
176 * is using the channel it must 'ack' the removal. A client must not 'ack' a
177 * removed channel more than once.
178 * @client - 'this' pointer for the client context
179 * @chan - channel to be acted upon
180 * @state - available or removed
183 typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client,
184 struct dma_chan *chan, enum dma_state state);
187 * struct dma_client - info on the entity making use of DMA services
188 * @event_callback: func ptr to call when something happens
189 * @cap_mask: only return channels that satisfy the requested capabilities
190 * a value of zero corresponds to any capability
191 * @global_node: list_head for global dma_client_list
194 dma_event_callback event_callback;
195 dma_cap_mask_t cap_mask;
196 struct list_head global_node;
199 typedef void (*dma_async_tx_callback)(void *dma_async_param);
201 * struct dma_async_tx_descriptor - async transaction descriptor
202 * ---dma generic offload fields---
203 * @cookie: tracking cookie for this transaction, set to -EBUSY if
204 * this tx is sitting on a dependency list
205 * @ack: the descriptor can not be reused until the client acknowledges
206 * receipt, i.e. has has a chance to establish any dependency chains
207 * @phys: physical address of the descriptor
208 * @tx_list: driver common field for operations that require multiple
210 * @chan: target channel for this operation
211 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
212 * @callback: routine to call after this operation is complete
213 * @callback_param: general parameter to pass to the callback routine
214 * ---async_tx api specific fields---
215 * @depend_list: at completion this list of transactions are submitted
216 * @depend_node: allow this transaction to be executed after another
217 * transaction has completed, possibly on another channel
218 * @parent: pointer to the next level up in the dependency chain
219 * @lock: protect the dependency list
221 struct dma_async_tx_descriptor {
225 struct list_head tx_list;
226 struct dma_chan *chan;
227 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
228 dma_async_tx_callback callback;
229 void *callback_param;
230 struct list_head depend_list;
231 struct list_head depend_node;
232 struct dma_async_tx_descriptor *parent;
237 * struct dma_device - info on the entity supplying DMA services
238 * @chancnt: how many DMA channels are supported
239 * @channels: the list of struct dma_chan
240 * @global_node: list_head for global dma_device_list
241 * @cap_mask: one or more dma_capability flags
242 * @max_xor: maximum number of xor sources, 0 if no capability
243 * @refcount: reference count
244 * @done: IO completion struct
245 * @dev_id: unique device ID
246 * @dev: struct device reference for dma mapping api
247 * @device_alloc_chan_resources: allocate resources and return the
248 * number of allocated descriptors
249 * @device_free_chan_resources: release DMA channel's resources
250 * @device_prep_dma_memcpy: prepares a memcpy operation
251 * @device_prep_dma_xor: prepares a xor operation
252 * @device_prep_dma_zero_sum: prepares a zero_sum operation
253 * @device_prep_dma_memset: prepares a memset operation
254 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
255 * @device_dependency_added: async_tx notifies the channel about new deps
256 * @device_issue_pending: push pending transactions to hardware
260 unsigned int chancnt;
261 struct list_head channels;
262 struct list_head global_node;
263 dma_cap_mask_t cap_mask;
266 struct kref refcount;
267 struct completion done;
272 int (*device_alloc_chan_resources)(struct dma_chan *chan);
273 void (*device_free_chan_resources)(struct dma_chan *chan);
275 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
276 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
277 size_t len, int int_en);
278 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
279 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
280 unsigned int src_cnt, size_t len, int int_en);
281 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
282 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
283 size_t len, u32 *result, int int_en);
284 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
285 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
287 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
288 struct dma_chan *chan);
290 void (*device_dependency_added)(struct dma_chan *chan);
291 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
292 dma_cookie_t cookie, dma_cookie_t *last,
294 void (*device_issue_pending)(struct dma_chan *chan);
297 /* --- public DMA engine API --- */
299 void dma_async_client_register(struct dma_client *client);
300 void dma_async_client_unregister(struct dma_client *client);
301 void dma_async_client_chan_request(struct dma_client *client);
302 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
303 void *dest, void *src, size_t len);
304 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
305 struct page *page, unsigned int offset, void *kdata, size_t len);
306 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
307 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
308 unsigned int src_off, size_t len);
309 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
310 struct dma_chan *chan);
313 async_tx_ack(struct dma_async_tx_descriptor *tx)
318 #define first_dma_cap(mask) __first_dma_cap(&(mask))
319 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
321 return min_t(int, DMA_TX_TYPE_END,
322 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
325 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
326 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
328 return min_t(int, DMA_TX_TYPE_END,
329 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
332 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
334 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
336 set_bit(tx_type, dstp->bits);
339 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
341 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
343 return test_bit(tx_type, srcp->bits);
346 #define for_each_dma_cap_mask(cap, mask) \
347 for ((cap) = first_dma_cap(mask); \
348 (cap) < DMA_TX_TYPE_END; \
349 (cap) = next_dma_cap((cap), (mask)))
352 * dma_async_issue_pending - flush pending transactions to HW
353 * @chan: target DMA channel
355 * This allows drivers to push copies to HW in batches,
356 * reducing MMIO writes where possible.
358 static inline void dma_async_issue_pending(struct dma_chan *chan)
360 return chan->device->device_issue_pending(chan);
363 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
366 * dma_async_is_tx_complete - poll for transaction completion
368 * @cookie: transaction identifier to check status of
369 * @last: returns last completed cookie, can be NULL
370 * @used: returns last issued cookie, can be NULL
372 * If @last and @used are passed in, upon return they reflect the driver
373 * internal state and can be used with dma_async_is_complete() to check
374 * the status of multiple cookies without re-checking hardware state.
376 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
377 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
379 return chan->device->device_is_tx_complete(chan, cookie, last, used);
382 #define dma_async_memcpy_complete(chan, cookie, last, used)\
383 dma_async_is_tx_complete(chan, cookie, last, used)
386 * dma_async_is_complete - test a cookie against chan state
387 * @cookie: transaction identifier to test status of
388 * @last_complete: last know completed transaction
389 * @last_used: last cookie value handed out
391 * dma_async_is_complete() is used in dma_async_memcpy_complete()
392 * the test logic is seperated for lightweight testing of multiple cookies
394 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
395 dma_cookie_t last_complete, dma_cookie_t last_used)
397 if (last_complete <= last_used) {
398 if ((cookie <= last_complete) || (cookie > last_used))
401 if ((cookie <= last_complete) && (cookie > last_used))
404 return DMA_IN_PROGRESS;
407 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
409 /* --- DMA device --- */
411 int dma_async_device_register(struct dma_device *device);
412 void dma_async_device_unregister(struct dma_device *device);
414 /* --- Helper iov-locking functions --- */
416 struct dma_page_list {
422 struct dma_pinned_list {
424 struct dma_page_list page_list[0];
427 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
428 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
430 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
431 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
432 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
433 struct dma_pinned_list *pinned_list, struct page *page,
434 unsigned int offset, size_t len);
436 #endif /* DMAENGINE_H */