include/asm-x86/spinlock.h

   1 #ifndef ASM_X86__SPINLOCK_H
   2 #define ASM_X86__SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <asm/processor.h>
   8 #include <linux/compiler.h>
   9 #include <asm/paravirt.h>
  10 /*
  11  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  12  *
  13  * Simple spin lock operations.  There are two variants, one clears IRQ's
  14  * on the local processor, one does not.
  15  *
  16  * These are fair FIFO ticket locks, which are currently limited to 256
  17  * CPUs.
  18  *
  19  * (the type definitions are in asm/spinlock_types.h)
  20  */
  21
  22 #ifdef CONFIG_X86_32
  23 # define LOCK_PTR_REG "a"
  24 # define REG_PTR_MODE "k"
  25 #else
  26 # define LOCK_PTR_REG "D"
  27 # define REG_PTR_MODE "q"
  28 #endif
  29
  30 #if defined(CONFIG_X86_32) && \
  31         (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
  32 /*
  33  * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
  34  * (PPro errata 66, 92)
  35  */
  36 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX
  37 #else
  38 # define UNLOCK_LOCK_PREFIX
  39 #endif
  40
  41 /*
  42  * Ticket locks are conceptually two parts, one indicating the current head of
  43  * the queue, and the other indicating the current tail. The lock is acquired
  44  * by atomically noting the tail and incrementing it by one (thus adding
  45  * ourself to the queue and noting our position), then waiting until the head
  46  * becomes equal to the the initial value of the tail.
  47  *
  48  * We use an xadd covering *both* parts of the lock, to increment the tail and
  49  * also load the position of the head, which takes care of memory ordering
  50  * issues and should be optimal for the uncontended case. Note the tail must be
  51  * in the high part, because a wide xadd increment of the low part would carry
  52  * up and contaminate the high part.
  53  *
  54  * With fewer than 2^8 possible CPUs, we can use x86's partial registers to
  55  * save some instructions and make the code more elegant. There really isn't
  56  * much between them in performance though, especially as locks are out of line.
  57  */
  58 #if (NR_CPUS < 256)
  59 #define TICKET_SHIFT 8
  60
  61 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
  62 {
  63         short inc = 0x0100;
  64
  65         asm volatile (
  66                 LOCK_PREFIX "xaddw %w0, %1\n"
  67                 "1:\t"
  68                 "cmpb %h0, %b0\n\t"
  69                 "je 2f\n\t"
  70                 "rep ; nop\n\t"
  71                 "movb %1, %b0\n\t"
  72                 /* don't need lfence here, because loads are in-order */
  73                 "jmp 1b\n"
  74                 "2:"
  75                 : "+Q" (inc), "+m" (lock->slock)
  76                 :
  77                 : "memory", "cc");
  78 }
  79
  80 static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
  81 {
  82         int tmp, new;
  83
  84         asm volatile("movzwl %2, %0\n\t"
  85                      "cmpb %h0,%b0\n\t"
  86                      "leal 0x100(%" REG_PTR_MODE "0), %1\n\t"
  87                      "jne 1f\n\t"
  88                      LOCK_PREFIX "cmpxchgw %w1,%2\n\t"
  89                      "1:"
  90                      "sete %b1\n\t"
  91                      "movzbl %b1,%0\n\t"
  92                      : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
  93                      :
  94                      : "memory", "cc");
  95
  96         return tmp;
  97 }
  98
  99 static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
 100 {
 101         asm volatile(UNLOCK_LOCK_PREFIX "incb %0"
 102                      : "+m" (lock->slock)
 103                      :
 104                      : "memory", "cc");
 105 }
 106 #else
 107 #define TICKET_SHIFT 16
 108
 109 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
 110 {
 111         int inc = 0x00010000;
 112         int tmp;
 113
 114         asm volatile(LOCK_PREFIX "xaddl %0, %1\n"
 115                      "movzwl %w0, %2\n\t"
 116                      "shrl $16, %0\n\t"
 117                      "1:\t"
 118                      "cmpl %0, %2\n\t"
 119                      "je 2f\n\t"
 120                      "rep ; nop\n\t"
 121                      "movzwl %1, %2\n\t"
 122                      /* don't need lfence here, because loads are in-order */
 123                      "jmp 1b\n"
 124                      "2:"
 125                      : "+r" (inc), "+m" (lock->slock), "=&r" (tmp)
 126                      :
 127                      : "memory", "cc");
 128 }
 129
 130 static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
 131 {
 132         int tmp;
 133         int new;
 134
 135         asm volatile("movl %2,%0\n\t"
 136                      "movl %0,%1\n\t"
 137                      "roll $16, %0\n\t"
 138                      "cmpl %0,%1\n\t"
 139                      "leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t"
 140                      "jne 1f\n\t"
 141                      LOCK_PREFIX "cmpxchgl %1,%2\n\t"
 142                      "1:"
 143                      "sete %b1\n\t"
 144                      "movzbl %b1,%0\n\t"
 145                      : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
 146                      :
 147                      : "memory", "cc");
 148
 149         return tmp;
 150 }
 151
 152 static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
 153 {
 154         asm volatile(UNLOCK_LOCK_PREFIX "incw %0"
 155                      : "+m" (lock->slock)
 156                      :
 157                      : "memory", "cc");
 158 }
 159 #endif
 160
 161 static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
 162 {
 163         int tmp = ACCESS_ONCE(lock->slock);
 164
 165         return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1 << TICKET_SHIFT) - 1));
 166 }
 167
 168 static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
 169 {
 170         int tmp = ACCESS_ONCE(lock->slock);
 171
 172         return (((tmp >> TICKET_SHIFT) - tmp) & ((1 << TICKET_SHIFT) - 1)) > 1;
 173 }
 174
 175 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
 176
 177 #ifdef CONFIG_PARAVIRT
 178 /*
 179  * Define virtualization-friendly old-style lock byte lock, for use in
 180  * pv_lock_ops if desired.
 181  *
 182  * This differs from the pre-2.6.24 spinlock by always using xchgb
 183  * rather than decb to take the lock; this allows it to use a
 184  * zero-initialized lock structure.  It also maintains a 1-byte
 185  * contention counter, so that we can implement
 186  * __byte_spin_is_contended.
 187  */
 188 struct __byte_spinlock {
 189         s8 lock;
 190         s8 spinners;
 191 };
 192
 193 static inline int __byte_spin_is_locked(raw_spinlock_t *lock)
 194 {
 195         struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
 196         return bl->lock != 0;
 197 }
 198
 199 static inline int __byte_spin_is_contended(raw_spinlock_t *lock)
 200 {
 201         struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
 202         return bl->spinners != 0;
 203 }
 204
 205 static inline void __byte_spin_lock(raw_spinlock_t *lock)
 206 {
 207         struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
 208         s8 val = 1;
 209
 210         asm("1: xchgb %1, %0\n"
 211             "   test %1,%1\n"
 212             "   jz 3f\n"
 213             "   " LOCK_PREFIX "incb %2\n"
 214             "2: rep;nop\n"
 215             "   cmpb $1, %0\n"
 216             "   je 2b\n"
 217             "   " LOCK_PREFIX "decb %2\n"
 218             "   jmp 1b\n"
 219             "3:"
 220             : "+m" (bl->lock), "+q" (val), "+m" (bl->spinners): : "memory");
 221 }
 222
 223 static inline int __byte_spin_trylock(raw_spinlock_t *lock)
 224 {
 225         struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
 226         u8 old = 1;
 227
 228         asm("xchgb %1,%0"
 229             : "+m" (bl->lock), "+q" (old) : : "memory");
 230
 231         return old == 0;
 232 }
 233
 234 static inline void __byte_spin_unlock(raw_spinlock_t *lock)
 235 {
 236         struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
 237         smp_wmb();
 238         bl->lock = 0;
 239 }
 240 #else  /* !CONFIG_PARAVIRT */
 241 static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
 242 {
 243         return __ticket_spin_is_locked(lock);
 244 }
 245
 246 static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
 247 {
 248         return __ticket_spin_is_contended(lock);
 249 }
 250
 251 static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
 252 {
 253         __ticket_spin_lock(lock);
 254 }
 255
 256 static __always_inline int __raw_spin_trylock(raw_spinlock_t *lock)
 257 {
 258         return __ticket_spin_trylock(lock);
 259 }
 260
 261 static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
 262 {
 263         __ticket_spin_unlock(lock);
 264 }
 265 #endif  /* CONFIG_PARAVIRT */
 266
 267 static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
 268 {
 269         while (__raw_spin_is_locked(lock))
 270                 cpu_relax();
 271 }
 272
 273 /*
 274  * Read-write spinlocks, allowing multiple readers
 275  * but only one writer.
 276  *
 277  * NOTE! it is quite common to have readers in interrupts
 278  * but no interrupt writers. For those circumstances we
 279  * can "mix" irq-safe locks - any writer needs to get a
 280  * irq-safe write-lock, but readers can get non-irqsafe
 281  * read-locks.
 282  *
 283  * On x86, we implement read-write locks as a 32-bit counter
 284  * with the high bit (sign) being the "contended" bit.
 285  */
 286
 287 /**
 288  * read_can_lock - would read_trylock() succeed?
 289  * @lock: the rwlock in question.
 290  */
 291 static inline int __raw_read_can_lock(raw_rwlock_t *lock)
 292 {
 293         return (int)(lock)->lock > 0;
 294 }
 295
 296 /**
 297  * write_can_lock - would write_trylock() succeed?
 298  * @lock: the rwlock in question.
 299  */
 300 static inline int __raw_write_can_lock(raw_rwlock_t *lock)
 301 {
 302         return (lock)->lock == RW_LOCK_BIAS;
 303 }
 304
 305 static inline void __raw_read_lock(raw_rwlock_t *rw)
 306 {
 307         asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
 308                      "jns 1f\n"
 309                      "call __read_lock_failed\n\t"
 310                      "1:\n"
 311                      ::LOCK_PTR_REG (rw) : "memory");
 312 }
 313
 314 static inline void __raw_write_lock(raw_rwlock_t *rw)
 315 {
 316         asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
 317                      "jz 1f\n"
 318                      "call __write_lock_failed\n\t"
 319                      "1:\n"
 320                      ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
 321 }
 322
 323 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 324 {
 325         atomic_t *count = (atomic_t *)lock;
 326
 327         atomic_dec(count);
 328         if (atomic_read(count) >= 0)
 329                 return 1;
 330         atomic_inc(count);
 331         return 0;
 332 }
 333
 334 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 335 {
 336         atomic_t *count = (atomic_t *)lock;
 337
 338         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 339                 return 1;
 340         atomic_add(RW_LOCK_BIAS, count);
 341         return 0;
 342 }
 343
 344 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 345 {
 346         asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
 347 }
 348
 349 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 350 {
 351         asm volatile(LOCK_PREFIX "addl %1, %0"
 352                      : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
 353 }
 354
 355 #define _raw_spin_relax(lock)   cpu_relax()
 356 #define _raw_read_relax(lock)   cpu_relax()
 357 #define _raw_write_relax(lock)  cpu_relax()
 358
 359 #endif /* ASM_X86__SPINLOCK_H */