include/asm-x86/spinlock.h

   1 #ifndef _X86_SPINLOCK_H_
   2 #define _X86_SPINLOCK_H_
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <asm/processor.h>
   8 #include <linux/compiler.h>
   9 #include <asm/paravirt.h>
  10 /*
  11  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  12  *
  13  * Simple spin lock operations.  There are two variants, one clears IRQ's
  14  * on the local processor, one does not.
  15  *
  16  * These are fair FIFO ticket locks, which are currently limited to 256
  17  * CPUs.
  18  *
  19  * (the type definitions are in asm/spinlock_types.h)
  20  */
  21
  22 #ifdef CONFIG_X86_32
  23 # define LOCK_PTR_REG "a"
  24 #else
  25 # define LOCK_PTR_REG "D"
  26 #endif
  27
  28 #if defined(CONFIG_X86_32) && \
  29         (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
  30 /*
  31  * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
  32  * (PPro errata 66, 92)
  33  */
  34 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX
  35 #else
  36 # define UNLOCK_LOCK_PREFIX
  37 #endif
  38
  39 /*
  40  * Ticket locks are conceptually two parts, one indicating the current head of
  41  * the queue, and the other indicating the current tail. The lock is acquired
  42  * by atomically noting the tail and incrementing it by one (thus adding
  43  * ourself to the queue and noting our position), then waiting until the head
  44  * becomes equal to the the initial value of the tail.
  45  *
  46  * We use an xadd covering *both* parts of the lock, to increment the tail and
  47  * also load the position of the head, which takes care of memory ordering
  48  * issues and should be optimal for the uncontended case. Note the tail must be
  49  * in the high part, because a wide xadd increment of the low part would carry
  50  * up and contaminate the high part.
  51  *
  52  * With fewer than 2^8 possible CPUs, we can use x86's partial registers to
  53  * save some instructions and make the code more elegant. There really isn't
  54  * much between them in performance though, especially as locks are out of line.
  55  */
  56 #if (NR_CPUS < 256)
  57 static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
  58 {
  59         int tmp = ACCESS_ONCE(lock->slock);
  60
  61         return (((tmp >> 8) & 0xff) != (tmp & 0xff));
  62 }
  63
  64 static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
  65 {
  66         int tmp = ACCESS_ONCE(lock->slock);
  67
  68         return (((tmp >> 8) & 0xff) - (tmp & 0xff)) > 1;
  69 }
  70
  71 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
  72 {
  73         short inc = 0x0100;
  74
  75         asm volatile (
  76                 LOCK_PREFIX "xaddw %w0, %1\n"
  77                 "1:\t"
  78                 "cmpb %h0, %b0\n\t"
  79                 "je 2f\n\t"
  80                 "rep ; nop\n\t"
  81                 "movb %1, %b0\n\t"
  82                 /* don't need lfence here, because loads are in-order */
  83                 "jmp 1b\n"
  84                 "2:"
  85                 : "+Q" (inc), "+m" (lock->slock)
  86                 :
  87                 : "memory", "cc");
  88 }
  89
  90 static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
  91 {
  92         int tmp;
  93         short new;
  94
  95         asm volatile("movw %2,%w0\n\t"
  96                      "cmpb %h0,%b0\n\t"
  97                      "jne 1f\n\t"
  98                      "movw %w0,%w1\n\t"
  99                      "incb %h1\n\t"
 100                      "lock ; cmpxchgw %w1,%2\n\t"
 101                      "1:"
 102                      "sete %b1\n\t"
 103                      "movzbl %b1,%0\n\t"
 104                      : "=&a" (tmp), "=Q" (new), "+m" (lock->slock)
 105                      :
 106                      : "memory", "cc");
 107
 108         return tmp;
 109 }
 110
 111 static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
 112 {
 113         asm volatile(UNLOCK_LOCK_PREFIX "incb %0"
 114                      : "+m" (lock->slock)
 115                      :
 116                      : "memory", "cc");
 117 }
 118 #else
 119 static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
 120 {
 121         int tmp = ACCESS_ONCE(lock->slock);
 122
 123         return (((tmp >> 16) & 0xffff) != (tmp & 0xffff));
 124 }
 125
 126 static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
 127 {
 128         int tmp = ACCESS_ONCE(lock->slock);
 129
 130         return (((tmp >> 16) & 0xffff) - (tmp & 0xffff)) > 1;
 131 }
 132
 133 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
 134 {
 135         int inc = 0x00010000;
 136         int tmp;
 137
 138         asm volatile("lock ; xaddl %0, %1\n"
 139                      "movzwl %w0, %2\n\t"
 140                      "shrl $16, %0\n\t"
 141                      "1:\t"
 142                      "cmpl %0, %2\n\t"
 143                      "je 2f\n\t"
 144                      "rep ; nop\n\t"
 145                      "movzwl %1, %2\n\t"
 146                      /* don't need lfence here, because loads are in-order */
 147                      "jmp 1b\n"
 148                      "2:"
 149                      : "+Q" (inc), "+m" (lock->slock), "=r" (tmp)
 150                      :
 151                      : "memory", "cc");
 152 }
 153
 154 static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
 155 {
 156         int tmp;
 157         int new;
 158
 159         asm volatile("movl %2,%0\n\t"
 160                      "movl %0,%1\n\t"
 161                      "roll $16, %0\n\t"
 162                      "cmpl %0,%1\n\t"
 163                      "jne 1f\n\t"
 164                      "addl $0x00010000, %1\n\t"
 165                      "lock ; cmpxchgl %1,%2\n\t"
 166                      "1:"
 167                      "sete %b1\n\t"
 168                      "movzbl %b1,%0\n\t"
 169                      : "=&a" (tmp), "=r" (new), "+m" (lock->slock)
 170                      :
 171                      : "memory", "cc");
 172
 173         return tmp;
 174 }
 175
 176 static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
 177 {
 178         asm volatile(UNLOCK_LOCK_PREFIX "incw %0"
 179                      : "+m" (lock->slock)
 180                      :
 181                      : "memory", "cc");
 182 }
 183 #endif
 184
 185 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
 186
 187 #ifndef CONFIG_PARAVIRT
 188 static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
 189 {
 190         return __ticket_spin_is_locked(lock);
 191 }
 192
 193 static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
 194 {
 195         return __ticket_spin_is_contended(lock);
 196 }
 197
 198 static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
 199 {
 200         __ticket_spin_lock(lock);
 201 }
 202
 203 static __always_inline int __raw_spin_trylock(raw_spinlock_t *lock)
 204 {
 205         return __ticket_spin_trylock(lock);
 206 }
 207
 208 static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
 209 {
 210         __ticket_spin_unlock(lock);
 211 }
 212 #endif  /* CONFIG_PARAVIRT */
 213
 214 static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
 215 {
 216         while (__raw_spin_is_locked(lock))
 217                 cpu_relax();
 218 }
 219
 220 /*
 221  * Read-write spinlocks, allowing multiple readers
 222  * but only one writer.
 223  *
 224  * NOTE! it is quite common to have readers in interrupts
 225  * but no interrupt writers. For those circumstances we
 226  * can "mix" irq-safe locks - any writer needs to get a
 227  * irq-safe write-lock, but readers can get non-irqsafe
 228  * read-locks.
 229  *
 230  * On x86, we implement read-write locks as a 32-bit counter
 231  * with the high bit (sign) being the "contended" bit.
 232  */
 233
 234 /**
 235  * read_can_lock - would read_trylock() succeed?
 236  * @lock: the rwlock in question.
 237  */
 238 static inline int __raw_read_can_lock(raw_rwlock_t *lock)
 239 {
 240         return (int)(lock)->lock > 0;
 241 }
 242
 243 /**
 244  * write_can_lock - would write_trylock() succeed?
 245  * @lock: the rwlock in question.
 246  */
 247 static inline int __raw_write_can_lock(raw_rwlock_t *lock)
 248 {
 249         return (lock)->lock == RW_LOCK_BIAS;
 250 }
 251
 252 static inline void __raw_read_lock(raw_rwlock_t *rw)
 253 {
 254         asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
 255                      "jns 1f\n"
 256                      "call __read_lock_failed\n\t"
 257                      "1:\n"
 258                      ::LOCK_PTR_REG (rw) : "memory");
 259 }
 260
 261 static inline void __raw_write_lock(raw_rwlock_t *rw)
 262 {
 263         asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
 264                      "jz 1f\n"
 265                      "call __write_lock_failed\n\t"
 266                      "1:\n"
 267                      ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
 268 }
 269
 270 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 271 {
 272         atomic_t *count = (atomic_t *)lock;
 273
 274         atomic_dec(count);
 275         if (atomic_read(count) >= 0)
 276                 return 1;
 277         atomic_inc(count);
 278         return 0;
 279 }
 280
 281 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 282 {
 283         atomic_t *count = (atomic_t *)lock;
 284
 285         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 286                 return 1;
 287         atomic_add(RW_LOCK_BIAS, count);
 288         return 0;
 289 }
 290
 291 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 292 {
 293         asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
 294 }
 295
 296 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 297 {
 298         asm volatile(LOCK_PREFIX "addl %1, %0"
 299                      : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
 300 }
 301
 302 #define _raw_spin_relax(lock)   cpu_relax()
 303 #define _raw_read_relax(lock)   cpu_relax()
 304 #define _raw_write_relax(lock)  cpu_relax()
 305
 306 #endif