2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef ASM_X86__I387_H
11 #define ASM_X86__I387_H
13 #include <linux/sched.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/regset.h>
17 #include <asm/processor.h>
18 #include <asm/sigcontext.h>
20 #include <asm/uaccess.h>
21 #include <asm/xsave.h>
23 extern unsigned int sig_xstate_size;
24 extern void fpu_init(void);
25 extern void mxcsr_feature_mask_init(void);
26 extern int init_fpu(struct task_struct *child);
27 extern asmlinkage void math_state_restore(void);
28 extern void init_thread_xstate(void);
30 extern user_regset_active_fn fpregs_active, xfpregs_active;
31 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
32 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
34 #ifdef CONFIG_IA32_EMULATION
35 extern unsigned int sig_xstate_ia32_size;
38 extern int save_i387_xstate_ia32(void __user *buf);
39 extern int restore_i387_xstate_ia32(void __user *buf);
42 #define X87_FSW_ES (1 << 7) /* Exception Summary */
46 /* Ignore delayed exceptions from user space */
47 static inline void tolerant_fwait(void)
49 asm volatile("1: fwait\n"
51 _ASM_EXTABLE(1b, 2b));
54 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
58 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
60 ".section .fixup,\"ax\"\n"
61 "3: movl $-1,%[err]\n"
66 #if 0 /* See comment in __save_init_fpu() below. */
67 : [fx] "r" (fx), "m" (*fx), "0" (0));
69 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
74 static inline int restore_fpu_checking(struct task_struct *tsk)
76 if (task_thread_info(tsk)->status & TS_XSAVE)
77 return xrstor_checking(&tsk->thread.xstate->xsave);
79 return fxrstor_checking(&tsk->thread.xstate->fxsave);
82 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
83 is pending. Clear the x87 state here by setting it to fixed
84 values. The kernel data segment can be sometimes 0 and sometimes
85 new user value. Both should be ok.
86 Use the PDA as safe address because it should be already in L1. */
87 static inline void clear_fpu_state(struct task_struct *tsk)
89 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
90 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
93 * xsave header may indicate the init state of the FP.
95 if ((task_thread_info(tsk)->status & TS_XSAVE) &&
96 !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
99 if (unlikely(fx->swd & X87_FSW_ES))
100 asm volatile("fnclex");
101 alternative_input(ASM_NOP8 ASM_NOP2,
102 " emms\n" /* clear stack tags */
103 " fildl %%gs:0", /* load to clear state */
104 X86_FEATURE_FXSAVE_LEAK);
107 static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
111 asm volatile("1: rex64/fxsave (%[fx])\n\t"
113 ".section .fixup,\"ax\"\n"
114 "3: movl $-1,%[err]\n"
118 : [err] "=r" (err), "=m" (*fx)
119 #if 0 /* See comment in __fxsave_clear() below. */
120 : [fx] "r" (fx), "0" (0));
122 : [fx] "cdaSDb" (fx), "0" (0));
125 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
127 /* No need to clear here because the caller clears USED_MATH */
131 static inline void fxsave(struct task_struct *tsk)
133 /* Using "rex64; fxsave %0" is broken because, if the memory operand
134 uses any extended registers for addressing, a second REX prefix
135 will be generated (to the assembler, rex64 followed by semicolon
136 is a separate instruction), and hence the 64-bitness is lost. */
138 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
139 starting with gas 2.16. */
140 __asm__ __volatile__("fxsaveq %0"
141 : "=m" (tsk->thread.xstate->fxsave));
143 /* Using, as a workaround, the properly prefixed form below isn't
144 accepted by any binutils version so far released, complaining that
145 the same type of prefix is used twice if an extended register is
146 needed for addressing (fix submitted to mainline 2005-11-21). */
147 __asm__ __volatile__("rex64/fxsave %0"
148 : "=m" (tsk->thread.xstate->fxsave));
150 /* This, however, we can work around by forcing the compiler to select
151 an addressing mode that doesn't require extended registers. */
152 __asm__ __volatile__("rex64/fxsave (%1)"
153 : "=m" (tsk->thread.xstate->fxsave)
154 : "cdaSDb" (&tsk->thread.xstate->fxsave));
158 static inline void __save_init_fpu(struct task_struct *tsk)
160 if (task_thread_info(tsk)->status & TS_XSAVE)
165 clear_fpu_state(tsk);
166 task_thread_info(tsk)->status &= ~TS_USEDFPU;
169 #else /* CONFIG_X86_32 */
171 extern void finit(void);
173 static inline void tolerant_fwait(void)
175 asm volatile("fnclex ; fwait");
178 static inline void restore_fpu(struct task_struct *tsk)
180 if (task_thread_info(tsk)->status & TS_XSAVE) {
181 xrstor_checking(&tsk->thread.xstate->xsave);
185 * The "nop" is needed to make the instructions the same
192 "m" (tsk->thread.xstate->fxsave));
195 /* We need a safe address that is cheap to find and that is already
196 in L1 during context switch. The best choices are unfortunately
197 different for UP and SMP */
199 #define safe_address (__per_cpu_offset[0])
201 #define safe_address (kstat_cpu(0).cpustat.user)
205 * These must be called with preempt disabled
207 static inline void __save_init_fpu(struct task_struct *tsk)
209 if (task_thread_info(tsk)->status & TS_XSAVE) {
210 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
211 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
216 * xsave header may indicate the init state of the FP.
218 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
221 if (unlikely(fx->swd & X87_FSW_ES))
222 asm volatile("fnclex");
225 * we can do a simple return here or be paranoid :)
230 /* Use more nops than strictly needed in case the compiler
233 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
235 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
237 [fx] "m" (tsk->thread.xstate->fxsave),
238 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
240 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
241 is pending. Clear the x87 state here by setting it to fixed
242 values. safe_address is a random variable that should be in L1 */
244 GENERIC_NOP8 GENERIC_NOP2,
245 "emms\n\t" /* clear stack tags */
246 "fildl %[addr]", /* set F?P to defined value */
247 X86_FEATURE_FXSAVE_LEAK,
248 [addr] "m" (safe_address));
250 task_thread_info(tsk)->status &= ~TS_USEDFPU;
253 #endif /* CONFIG_X86_64 */
256 * Signal frame handlers...
258 extern int save_i387_xstate(void __user *buf);
259 extern int restore_i387_xstate(void __user *buf);
261 static inline void __unlazy_fpu(struct task_struct *tsk)
263 if (task_thread_info(tsk)->status & TS_USEDFPU) {
264 __save_init_fpu(tsk);
267 tsk->fpu_counter = 0;
270 static inline void __clear_fpu(struct task_struct *tsk)
272 if (task_thread_info(tsk)->status & TS_USEDFPU) {
274 task_thread_info(tsk)->status &= ~TS_USEDFPU;
279 static inline void kernel_fpu_begin(void)
281 struct thread_info *me = current_thread_info();
283 if (me->status & TS_USEDFPU)
284 __save_init_fpu(me->task);
289 static inline void kernel_fpu_end(void)
297 static inline void save_init_fpu(struct task_struct *tsk)
299 __save_init_fpu(tsk);
303 #define unlazy_fpu __unlazy_fpu
304 #define clear_fpu __clear_fpu
306 #else /* CONFIG_X86_32 */
309 * These disable preemption on their own and are safe
311 static inline void save_init_fpu(struct task_struct *tsk)
314 __save_init_fpu(tsk);
319 static inline void unlazy_fpu(struct task_struct *tsk)
326 static inline void clear_fpu(struct task_struct *tsk)
333 #endif /* CONFIG_X86_64 */
336 * i387 state interaction
338 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
341 return tsk->thread.xstate->fxsave.cwd;
343 return (unsigned short)tsk->thread.xstate->fsave.cwd;
347 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
350 return tsk->thread.xstate->fxsave.swd;
352 return (unsigned short)tsk->thread.xstate->fsave.swd;
356 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
359 return tsk->thread.xstate->fxsave.mxcsr;
361 return MXCSR_DEFAULT;
365 #endif /* ASM_X86__I387_H */