1 #ifndef _PARISC_BITOPS_H
2 #define _PARISC_BITOPS_H
4 #include <linux/compiler.h>
5 #include <asm/types.h> /* for BITS_PER_LONG/SHIFT_PER_LONG */
6 #include <asm/byteorder.h>
7 #include <asm/atomic.h>
10 * HP-PARISC specific bit operations
11 * for a detailed description of the functions please refer
12 * to include/asm-i386/bitops.h or kerneldoc
15 #define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
18 #define smp_mb__before_clear_bit() smp_mb()
19 #define smp_mb__after_clear_bit() smp_mb()
21 /* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
22 * on use of volatile and __*_bit() (set/clear/change):
23 * *_bit() want use of volatile.
24 * __*_bit() are "relaxed" and don't use spinlock or volatile.
27 static __inline__ void set_bit(int nr, volatile unsigned long * addr)
29 unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
32 addr += (nr >> SHIFT_PER_LONG);
33 _atomic_spin_lock_irqsave(addr, flags);
35 _atomic_spin_unlock_irqrestore(addr, flags);
38 static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
40 unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
43 addr += (nr >> SHIFT_PER_LONG);
44 _atomic_spin_lock_irqsave(addr, flags);
46 _atomic_spin_unlock_irqrestore(addr, flags);
49 static __inline__ void change_bit(int nr, volatile unsigned long * addr)
51 unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
54 addr += (nr >> SHIFT_PER_LONG);
55 _atomic_spin_lock_irqsave(addr, flags);
57 _atomic_spin_unlock_irqrestore(addr, flags);
60 static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
62 unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
67 addr += (nr >> SHIFT_PER_LONG);
68 _atomic_spin_lock_irqsave(addr, flags);
70 set = (old & mask) ? 1 : 0;
73 _atomic_spin_unlock_irqrestore(addr, flags);
78 static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
80 unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
85 addr += (nr >> SHIFT_PER_LONG);
86 _atomic_spin_lock_irqsave(addr, flags);
88 set = (old & mask) ? 1 : 0;
91 _atomic_spin_unlock_irqrestore(addr, flags);
96 static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
98 unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
102 addr += (nr >> SHIFT_PER_LONG);
103 _atomic_spin_lock_irqsave(addr, flags);
105 *addr = oldbit ^ mask;
106 _atomic_spin_unlock_irqrestore(addr, flags);
108 return (oldbit & mask) ? 1 : 0;
111 #include <asm-generic/bitops/non-atomic.h>
116 * __ffs - find first bit in word. returns 0 to "BITS_PER_LONG-1".
117 * @word: The word to search
119 * __ffs() return is undefined if no bit is set.
121 * 32-bit fast __ffs by LaMont Jones "lamont At hp com".
122 * 64-bit enhancement by Grant Grundler "grundler At parisc-linux org".
123 * (with help from willy/jejb to get the semantics right)
125 * This algorithm avoids branches by making use of nullification.
126 * One side effect of "extr" instructions is it sets PSW[N] bit.
127 * How PSW[N] (nullify next insn) gets set is determined by the
128 * "condition" field (eg "<>" or "TR" below) in the extr* insn.
129 * Only the 1st and one of either the 2cd or 3rd insn will get executed.
130 * Each set of 3 insn will get executed in 2 cycles on PA8x00 vs 16 or so
131 * cycles for each mispredicted branch.
134 static __inline__ unsigned long __ffs(unsigned long x)
141 " extrd,u,*<> %0,63,32,%%r0\n"
142 " extrd,u,*TR %0,31,32,%0\n" /* move top 32-bits down */
147 " extru,<> %0,31,16,%%r0\n"
148 " extru,TR %0,15,16,%0\n" /* xxxx0000 -> 0000xxxx */
150 " extru,<> %0,31,8,%%r0\n"
151 " extru,TR %0,23,8,%0\n" /* 0000xx00 -> 000000xx */
153 " extru,<> %0,31,4,%%r0\n"
154 " extru,TR %0,27,4,%0\n" /* 000000x0 -> 0000000x */
156 " extru,<> %0,31,2,%%r0\n"
157 " extru,TR %0,29,2,%0\n" /* 0000000y, 1100b -> 0011b */
159 " extru,= %0,31,1,%%r0\n" /* check last bit */
161 : "+r" (x), "=r" (ret) );
165 #include <asm-generic/bitops/ffz.h>
168 * ffs: find first bit set. returns 1 to BITS_PER_LONG or 0 (if none set)
169 * This is defined the same way as the libc and compiler builtin
170 * ffs routines, therefore differs in spirit from the above ffz (man ffs).
172 static __inline__ int ffs(int x)
174 return x ? (__ffs((unsigned long)x) + 1) : 0;
178 * fls: find last (most significant) bit set.
179 * fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
182 static __inline__ int fls(int x)
190 " extru,<> %0,15,16,%%r0\n"
191 " zdep,TR %0,15,16,%0\n" /* xxxx0000 */
193 " extru,<> %0,7,8,%%r0\n"
194 " zdep,TR %0,23,24,%0\n" /* xx000000 */
196 " extru,<> %0,3,4,%%r0\n"
197 " zdep,TR %0,27,28,%0\n" /* x0000000 */
199 " extru,<> %0,1,2,%%r0\n"
200 " zdep,TR %0,29,30,%0\n" /* y0000000 (y&3 = 0) */
202 " extru,= %0,0,1,%%r0\n"
203 " addi 1,%1,%1\n" /* if y & 8, add 1 */
204 : "+r" (x), "=r" (ret) );
209 #include <asm-generic/bitops/fls64.h>
210 #include <asm-generic/bitops/hweight.h>
211 #include <asm-generic/bitops/sched.h>
213 #endif /* __KERNEL__ */
215 #include <asm-generic/bitops/find.h>
219 #include <asm-generic/bitops/ext2-non-atomic.h>
221 /* '3' is bits per byte */
222 #define LE_BYTE_ADDR ((sizeof(unsigned long) - 1) << 3)
224 #define ext2_set_bit_atomic(l,nr,addr) \
225 test_and_set_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
226 #define ext2_clear_bit_atomic(l,nr,addr) \
227 test_and_clear_bit( (nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
229 #endif /* __KERNEL__ */
231 #include <asm-generic/bitops/minix-le.h>
233 #endif /* _PARISC_BITOPS_H */