include/asm-i386/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <linux/bitops.h> /* for LOCK_PREFIX */
   8
   9 #ifdef __KERNEL__
  10
  11 struct task_struct;     /* one of the stranger aspects of C forward declarations.. */
  12 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
  13
  14 /*
  15  * Saving eflags is important. It switches not only IOPL between tasks,
  16  * it also protects other tasks from NT leaking through sysenter etc.
  17  */
  18 #define switch_to(prev,next,last) do {                                  \
  19         unsigned long esi,edi;                                          \
  20         asm volatile("pushfl\n\t"               /* Save flags */        \
  21                      "pushl %%ebp\n\t"                                  \
  22                      "movl %%esp,%0\n\t"        /* save ESP */          \
  23                      "movl %5,%%esp\n\t"        /* restore ESP */       \
  24                      "movl $1f,%1\n\t"          /* save EIP */          \
  25                      "pushl %6\n\t"             /* restore EIP */       \
  26                      "jmp __switch_to\n"                                \
  27                      "1:\t"                                             \
  28                      "popl %%ebp\n\t"                                   \
  29                      "popfl"                                            \
  30                      :"=m" (prev->thread.esp),"=m" (prev->thread.eip),  \
  31                       "=a" (last),"=S" (esi),"=D" (edi)                 \
  32                      :"m" (next->thread.esp),"m" (next->thread.eip),    \
  33                       "2" (prev), "d" (next));                          \
  34 } while (0)
  35
  36 #define _set_base(addr,base) do { unsigned long __pr; \
  37 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  38         "rorl $16,%%edx\n\t" \
  39         "movb %%dl,%2\n\t" \
  40         "movb %%dh,%3" \
  41         :"=&d" (__pr) \
  42         :"m" (*((addr)+2)), \
  43          "m" (*((addr)+4)), \
  44          "m" (*((addr)+7)), \
  45          "0" (base) \
  46         ); } while(0)
  47
  48 #define _set_limit(addr,limit) do { unsigned long __lr; \
  49 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  50         "rorl $16,%%edx\n\t" \
  51         "movb %2,%%dh\n\t" \
  52         "andb $0xf0,%%dh\n\t" \
  53         "orb %%dh,%%dl\n\t" \
  54         "movb %%dl,%2" \
  55         :"=&d" (__lr) \
  56         :"m" (*(addr)), \
  57          "m" (*((addr)+6)), \
  58          "0" (limit) \
  59         ); } while(0)
  60
  61 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
  62 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
  63
  64 /*
  65  * Load a segment. Fall back on loading the zero
  66  * segment if something goes wrong..
  67  */
  68 #define loadsegment(seg,value)                  \
  69         asm volatile("\n"                       \
  70                 "1:\t"                          \
  71                 "mov %0,%%" #seg "\n"           \
  72                 "2:\n"                          \
  73                 ".section .fixup,\"ax\"\n"      \
  74                 "3:\t"                          \
  75                 "pushl $0\n\t"                  \
  76                 "popl %%" #seg "\n\t"           \
  77                 "jmp 2b\n"                      \
  78                 ".previous\n"                   \
  79                 ".section __ex_table,\"a\"\n\t" \
  80                 ".align 4\n\t"                  \
  81                 ".long 1b,3b\n"                 \
  82                 ".previous"                     \
  83                 : :"rm" (value))
  84
  85 /*
  86  * Save a segment register away
  87  */
  88 #define savesegment(seg, value) \
  89         asm volatile("mov %%" #seg ",%0":"=rm" (value))
  90
  91
  92 static inline void native_clts(void)
  93 {
  94         asm volatile ("clts");
  95 }
  96
  97 static inline unsigned long native_read_cr0(void)
  98 {
  99         unsigned long val;
 100         asm volatile("movl %%cr0,%0\n\t" :"=r" (val));
 101         return val;
 102 }
 103
 104 static inline void native_write_cr0(unsigned long val)
 105 {
 106         asm volatile("movl %0,%%cr0": :"r" (val));
 107 }
 108
 109 static inline unsigned long native_read_cr2(void)
 110 {
 111         unsigned long val;
 112         asm volatile("movl %%cr2,%0\n\t" :"=r" (val));
 113         return val;
 114 }
 115
 116 static inline void native_write_cr2(unsigned long val)
 117 {
 118         asm volatile("movl %0,%%cr2": :"r" (val));
 119 }
 120
 121 static inline unsigned long native_read_cr3(void)
 122 {
 123         unsigned long val;
 124         asm volatile("movl %%cr3,%0\n\t" :"=r" (val));
 125         return val;
 126 }
 127
 128 static inline void native_write_cr3(unsigned long val)
 129 {
 130         asm volatile("movl %0,%%cr3": :"r" (val));
 131 }
 132
 133 static inline unsigned long native_read_cr4(void)
 134 {
 135         unsigned long val;
 136         asm volatile("movl %%cr4,%0\n\t" :"=r" (val));
 137         return val;
 138 }
 139
 140 static inline unsigned long native_read_cr4_safe(void)
 141 {
 142         unsigned long val;
 143         /* This could fault if %cr4 does not exist */
 144         asm("1: movl %%cr4, %0          \n"
 145                 "2:                             \n"
 146                 ".section __ex_table,\"a\"      \n"
 147                 ".long 1b,2b                    \n"
 148                 ".previous                      \n"
 149                 : "=r" (val): "0" (0));
 150         return val;
 151 }
 152
 153 static inline void native_write_cr4(unsigned long val)
 154 {
 155         asm volatile("movl %0,%%cr4": :"r" (val));
 156 }
 157
 158 static inline void native_wbinvd(void)
 159 {
 160         asm volatile("wbinvd": : :"memory");
 161 }
 162
 163
 164 #ifdef CONFIG_PARAVIRT
 165 #include <asm/paravirt.h>
 166 #else
 167 #define read_cr0()      (native_read_cr0())
 168 #define write_cr0(x)    (native_write_cr0(x))
 169 #define read_cr2()      (native_read_cr2())
 170 #define write_cr2(x)    (native_write_cr2(x))
 171 #define read_cr3()      (native_read_cr3())
 172 #define write_cr3(x)    (native_write_cr3(x))
 173 #define read_cr4()      (native_read_cr4())
 174 #define read_cr4_safe() (native_read_cr4_safe())
 175 #define write_cr4(x)    (native_write_cr4(x))
 176 #define wbinvd()        (native_wbinvd())
 177
 178 /* Clear the 'TS' bit */
 179 #define clts()          (native_clts())
 180
 181 #endif/* CONFIG_PARAVIRT */
 182
 183 /* Set the 'TS' bit */
 184 #define stts() write_cr0(8 | read_cr0())
 185
 186 #endif  /* __KERNEL__ */
 187
 188 static inline unsigned long get_limit(unsigned long segment)
 189 {
 190         unsigned long __limit;
 191         __asm__("lsll %1,%0"
 192                 :"=r" (__limit):"r" (segment));
 193         return __limit+1;
 194 }
 195
 196 #define nop() __asm__ __volatile__ ("nop")
 197
 198 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 199
 200 #define tas(ptr) (xchg((ptr),1))
 201
 202 struct __xchg_dummy { unsigned long a[100]; };
 203 #define __xg(x) ((struct __xchg_dummy *)(x))
 204
 205
 206 #ifdef CONFIG_X86_CMPXCHG64
 207
 208 /*
 209  * The semantics of XCHGCMP8B are a bit strange, this is why
 210  * there is a loop and the loading of %%eax and %%edx has to
 211  * be inside. This inlines well in most cases, the cached
 212  * cost is around ~38 cycles. (in the future we might want
 213  * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
 214  * might have an implicit FPU-save as a cost, so it's not
 215  * clear which path to go.)
 216  *
 217  * cmpxchg8b must be used with the lock prefix here to allow
 218  * the instruction to be executed atomically, see page 3-102
 219  * of the instruction set reference 24319102.pdf. We need
 220  * the reader side to see the coherent 64bit value.
 221  */
 222 static inline void __set_64bit (unsigned long long * ptr,
 223                 unsigned int low, unsigned int high)
 224 {
 225         __asm__ __volatile__ (
 226                 "\n1:\t"
 227                 "movl (%0), %%eax\n\t"
 228                 "movl 4(%0), %%edx\n\t"
 229                 "lock cmpxchg8b (%0)\n\t"
 230                 "jnz 1b"
 231                 : /* no outputs */
 232                 :       "D"(ptr),
 233                         "b"(low),
 234                         "c"(high)
 235                 :       "ax","dx","memory");
 236 }
 237
 238 static inline void __set_64bit_constant (unsigned long long *ptr,
 239                                                  unsigned long long value)
 240 {
 241         __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
 242 }
 243 #define ll_low(x)       *(((unsigned int*)&(x))+0)
 244 #define ll_high(x)      *(((unsigned int*)&(x))+1)
 245
 246 static inline void __set_64bit_var (unsigned long long *ptr,
 247                          unsigned long long value)
 248 {
 249         __set_64bit(ptr,ll_low(value), ll_high(value));
 250 }
 251
 252 #define set_64bit(ptr,value) \
 253 (__builtin_constant_p(value) ? \
 254  __set_64bit_constant(ptr, value) : \
 255  __set_64bit_var(ptr, value) )
 256
 257 #define _set_64bit(ptr,value) \
 258 (__builtin_constant_p(value) ? \
 259  __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
 260  __set_64bit(ptr, ll_low(value), ll_high(value)) )
 261
 262 #endif
 263
 264 /*
 265  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 266  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 267  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 268  */
 269 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 270 {
 271         switch (size) {
 272                 case 1:
 273                         __asm__ __volatile__("xchgb %b0,%1"
 274                                 :"=q" (x)
 275                                 :"m" (*__xg(ptr)), "0" (x)
 276                                 :"memory");
 277                         break;
 278                 case 2:
 279                         __asm__ __volatile__("xchgw %w0,%1"
 280                                 :"=r" (x)
 281                                 :"m" (*__xg(ptr)), "0" (x)
 282                                 :"memory");
 283                         break;
 284                 case 4:
 285                         __asm__ __volatile__("xchgl %0,%1"
 286                                 :"=r" (x)
 287                                 :"m" (*__xg(ptr)), "0" (x)
 288                                 :"memory");
 289                         break;
 290         }
 291         return x;
 292 }
 293
 294 /*
 295  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 296  * store NEW in MEM.  Return the initial value in MEM.  Success is
 297  * indicated by comparing RETURN with OLD.
 298  */
 299
 300 #ifdef CONFIG_X86_CMPXCHG
 301 #define __HAVE_ARCH_CMPXCHG 1
 302 #define cmpxchg(ptr,o,n)\
 303         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 304                                         (unsigned long)(n),sizeof(*(ptr))))
 305 #define sync_cmpxchg(ptr,o,n)\
 306         ((__typeof__(*(ptr)))__sync_cmpxchg((ptr),(unsigned long)(o),\
 307                                         (unsigned long)(n),sizeof(*(ptr))))
 308 #define cmpxchg_local(ptr,o,n)\
 309         ((__typeof__(*(ptr)))__cmpxchg_local((ptr),(unsigned long)(o),\
 310                                         (unsigned long)(n),sizeof(*(ptr))))
 311 #endif
 312
 313 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 314                                       unsigned long new, int size)
 315 {
 316         unsigned long prev;
 317         switch (size) {
 318         case 1:
 319                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 320                                      : "=a"(prev)
 321                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 322                                      : "memory");
 323                 return prev;
 324         case 2:
 325                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 326                                      : "=a"(prev)
 327                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 328                                      : "memory");
 329                 return prev;
 330         case 4:
 331                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
 332                                      : "=a"(prev)
 333                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 334                                      : "memory");
 335                 return prev;
 336         }
 337         return old;
 338 }
 339
 340 /*
 341  * Always use locked operations when touching memory shared with a
 342  * hypervisor, since the system may be SMP even if the guest kernel
 343  * isn't.
 344  */
 345 static inline unsigned long __sync_cmpxchg(volatile void *ptr,
 346                                             unsigned long old,
 347                                             unsigned long new, int size)
 348 {
 349         unsigned long prev;
 350         switch (size) {
 351         case 1:
 352                 __asm__ __volatile__("lock; cmpxchgb %b1,%2"
 353                                      : "=a"(prev)
 354                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 355                                      : "memory");
 356                 return prev;
 357         case 2:
 358                 __asm__ __volatile__("lock; cmpxchgw %w1,%2"
 359                                      : "=a"(prev)
 360                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 361                                      : "memory");
 362                 return prev;
 363         case 4:
 364                 __asm__ __volatile__("lock; cmpxchgl %1,%2"
 365                                      : "=a"(prev)
 366                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 367                                      : "memory");
 368                 return prev;
 369         }
 370         return old;
 371 }
 372
 373 static inline unsigned long __cmpxchg_local(volatile void *ptr,
 374                         unsigned long old, unsigned long new, int size)
 375 {
 376         unsigned long prev;
 377         switch (size) {
 378         case 1:
 379                 __asm__ __volatile__("cmpxchgb %b1,%2"
 380                                      : "=a"(prev)
 381                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 382                                      : "memory");
 383                 return prev;
 384         case 2:
 385                 __asm__ __volatile__("cmpxchgw %w1,%2"
 386                                      : "=a"(prev)
 387                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 388                                      : "memory");
 389                 return prev;
 390         case 4:
 391                 __asm__ __volatile__("cmpxchgl %1,%2"
 392                                      : "=a"(prev)
 393                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 394                                      : "memory");
 395                 return prev;
 396         }
 397         return old;
 398 }
 399
 400 #ifndef CONFIG_X86_CMPXCHG
 401 /*
 402  * Building a kernel capable running on 80386. It may be necessary to
 403  * simulate the cmpxchg on the 80386 CPU. For that purpose we define
 404  * a function for each of the sizes we support.
 405  */
 406
 407 extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
 408 extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
 409 extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
 410
 411 static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
 412                                       unsigned long new, int size)
 413 {
 414         switch (size) {
 415         case 1:
 416                 return cmpxchg_386_u8(ptr, old, new);
 417         case 2:
 418                 return cmpxchg_386_u16(ptr, old, new);
 419         case 4:
 420                 return cmpxchg_386_u32(ptr, old, new);
 421         }
 422         return old;
 423 }
 424
 425 #define cmpxchg(ptr,o,n)                                                \
 426 ({                                                                      \
 427         __typeof__(*(ptr)) __ret;                                       \
 428         if (likely(boot_cpu_data.x86 > 3))                              \
 429                 __ret = __cmpxchg((ptr), (unsigned long)(o),            \
 430                                         (unsigned long)(n), sizeof(*(ptr))); \
 431         else                                                            \
 432                 __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
 433                                         (unsigned long)(n), sizeof(*(ptr))); \
 434         __ret;                                                          \
 435 })
 436 #define cmpxchg_local(ptr,o,n)                                          \
 437 ({                                                                      \
 438         __typeof__(*(ptr)) __ret;                                       \
 439         if (likely(boot_cpu_data.x86 > 3))                              \
 440                 __ret = __cmpxchg_local((ptr), (unsigned long)(o),      \
 441                                         (unsigned long)(n), sizeof(*(ptr))); \
 442         else                                                            \
 443                 __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
 444                                         (unsigned long)(n), sizeof(*(ptr))); \
 445         __ret;                                                          \
 446 })
 447 #endif
 448
 449 #ifdef CONFIG_X86_CMPXCHG64
 450
 451 static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
 452                                       unsigned long long new)
 453 {
 454         unsigned long long prev;
 455         __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
 456                              : "=A"(prev)
 457                              : "b"((unsigned long)new),
 458                                "c"((unsigned long)(new >> 32)),
 459                                "m"(*__xg(ptr)),
 460                                "0"(old)
 461                              : "memory");
 462         return prev;
 463 }
 464
 465 static inline unsigned long long __cmpxchg64_local(volatile void *ptr,
 466                         unsigned long long old, unsigned long long new)
 467 {
 468         unsigned long long prev;
 469         __asm__ __volatile__("cmpxchg8b %3"
 470                              : "=A"(prev)
 471                              : "b"((unsigned long)new),
 472                                "c"((unsigned long)(new >> 32)),
 473                                "m"(*__xg(ptr)),
 474                                "0"(old)
 475                              : "memory");
 476         return prev;
 477 }
 478
 479 #define cmpxchg64(ptr,o,n)\
 480         ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
 481                                         (unsigned long long)(n)))
 482 #define cmpxchg64_local(ptr,o,n)\
 483         ((__typeof__(*(ptr)))__cmpxchg64_local((ptr),(unsigned long long)(o),\
 484                                         (unsigned long long)(n)))
 485 #endif
 486
 487 /*
 488  * Force strict CPU ordering.
 489  * And yes, this is required on UP too when we're talking
 490  * to devices.
 491  *
 492  * For now, "wmb()" doesn't actually do anything, as all
 493  * Intel CPU's follow what Intel calls a *Processor Order*,
 494  * in which all writes are seen in the program order even
 495  * outside the CPU.
 496  *
 497  * I expect future Intel CPU's to have a weaker ordering,
 498  * but I'd also expect them to finally get their act together
 499  * and add some real memory barriers if so.
 500  *
 501  * Some non intel clones support out of order store. wmb() ceases to be a
 502  * nop for these.
 503  */
 504
 505
 506 /*
 507  * Actually only lfence would be needed for mb() because all stores done
 508  * by the kernel should be already ordered. But keep a full barrier for now.
 509  */
 510
 511 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 512 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 513
 514 /**
 515  * read_barrier_depends - Flush all pending reads that subsequents reads
 516  * depend on.
 517  *
 518  * No data-dependent reads from memory-like regions are ever reordered
 519  * over this barrier.  All reads preceding this primitive are guaranteed
 520  * to access memory (but not necessarily other CPUs' caches) before any
 521  * reads following this primitive that depend on the data return by
 522  * any of the preceding reads.  This primitive is much lighter weight than
 523  * rmb() on most CPUs, and is never heavier weight than is
 524  * rmb().
 525  *
 526  * These ordering constraints are respected by both the local CPU
 527  * and the compiler.
 528  *
 529  * Ordering is not guaranteed by anything other than these primitives,
 530  * not even by data dependencies.  See the documentation for
 531  * memory_barrier() for examples and URLs to more information.
 532  *
 533  * For example, the following code would force ordering (the initial
 534  * value of "a" is zero, "b" is one, and "p" is "&a"):
 535  *
 536  * <programlisting>
 537  *      CPU 0                           CPU 1
 538  *
 539  *      b = 2;
 540  *      memory_barrier();
 541  *      p = &b;                         q = p;
 542  *                                      read_barrier_depends();
 543  *                                      d = *q;
 544  * </programlisting>
 545  *
 546  * because the read of "*q" depends on the read of "p" and these
 547  * two reads are separated by a read_barrier_depends().  However,
 548  * the following code, with the same initial values for "a" and "b":
 549  *
 550  * <programlisting>
 551  *      CPU 0                           CPU 1
 552  *
 553  *      a = 2;
 554  *      memory_barrier();
 555  *      b = 3;                          y = b;
 556  *                                      read_barrier_depends();
 557  *                                      x = a;
 558  * </programlisting>
 559  *
 560  * does not enforce ordering, since there is no data dependency between
 561  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 562  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 563  * in cases like this where there are no data dependencies.
 564  **/
 565
 566 #define read_barrier_depends()  do { } while(0)
 567
 568 #ifdef CONFIG_X86_OOSTORE
 569 /* Actually there are no OOO store capable CPUs for now that do SSE,
 570    but make it already an possibility. */
 571 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 572 #else
 573 #define wmb()   __asm__ __volatile__ ("": : :"memory")
 574 #endif
 575
 576 #ifdef CONFIG_SMP
 577 #define smp_mb()        mb()
 578 #define smp_rmb()       rmb()
 579 #define smp_wmb()       wmb()
 580 #define smp_read_barrier_depends()      read_barrier_depends()
 581 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 582 #else
 583 #define smp_mb()        barrier()
 584 #define smp_rmb()       barrier()
 585 #define smp_wmb()       barrier()
 586 #define smp_read_barrier_depends()      do { } while(0)
 587 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 588 #endif
 589
 590 #include <linux/irqflags.h>
 591
 592 /*
 593  * disable hlt during certain critical i/o operations
 594  */
 595 #define HAVE_DISABLE_HLT
 596 void disable_hlt(void);
 597 void enable_hlt(void);
 598
 599 extern int es7000_plat;
 600 void cpu_idle_wait(void);
 601
 602 /*
 603  * On SMP systems, when the scheduler does migration-cost autodetection,
 604  * it needs a way to flush as much of the CPU's caches as possible:
 605  */
 606 static inline void sched_cacheflush(void)
 607 {
 608         wbinvd();
 609 }
 610
 611 extern unsigned long arch_align_stack(unsigned long sp);
 612 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 613
 614 void default_idle(void);
 615
 616 #endif